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In this work, we investigate mushroom type phase-change material (PCM) memory cells based on Ge2Sb2Te5. We use low-angle annular dark field (LAADF) STEM imaging and energy dispersive X-ray spectroscopy (EDX) to study changes in microstructure and elemental distributions in the PCM cells before and after SET and RESET conditions. We describe the microscope settings required to reveal the amorphous dome in the RESET state and present an application example involving the failure analysis of a PCM test array made with devices fabricated at IBM’s Albany AI Hardware Research Center.

There are several variants of artificial intelligence (AI) hardware structures that are under study by the semiconductor industry for potential use in complementary metal–oxide–semiconductor (CMOS) designs. This paper discusses some of the failure analysis challenges that have appeared in discrete test structures and test arrays developed as part of an exploratory phase-change memory (PCM) program at IBM's Albany AI Hardware Research Center.

A novel nanosecond (ns) laser anneal (multiple laser shots at sub-melting low laser energy) was employed to reduce the blanket sheet resistance of Ru thin films deposited by physical vapor deposition (PVD). The laser anneal was conducted after PVD Ru deposition and then followed up with a standard 400°C anneal in a forming gas environment. Blanket sheet R decreased by 30% for the laser + furnace annealed Ru films, whereas the drop for just 400°C furnace annealed Ru films was only 18%. Multiple laser exposures at an optimized laser fluence was identified as a key factor in enabling this benefit at BEOL compatible thermal budget suitable for scaled-down Ru interconnects.

AlOx was selectively deposited on top of SiCOH in 32 nm pitch Cu-SiCOH pattern to form a Fully Aligned Via (FAV) test structure. Selective deposition process performance and its integration into the 5nm BEOL FAV structure were evaluated. The selective AlOx deposition involves multistep process including surface treatment, selective Self-Aligned Molecules (SAM) bonding to inhibit Cu metal surface, and the selective growth of AlOx on top of SiCOH dielectric using Chemical vapor deposition process with various precursors and process conditions below 300°C. Thin selective AlOx of 4–6 nm thickness show excellent selectivity on SiCOH over Co capped Cu-SiCOH patterned structures with various spacing. The Via Chain electrical yields were measured on 32 nm pitch structures by AlOx selective deposition and are comparable to the established FAV process by Cu wet recess. This indicates that the Selective AlOx deposition process is highly selective on SiCOH dielectric surface without defect formation in the Co Capped Cu surfaces.

Stacked Gate-All-Around (GAA) nanosheet pFETs with compressively strained Si 1-x Ge x channel have been fabricated to explore their electrical benefits. The Si 1-x Ge x NS channel structure with high crystalline quality and 1GPa compressive stress has been realized for the first time. Systematic study has been performed to understand the effect of epitaxial Si 1-x Ge x thickness, Ge fraction, and Si cap thickness on the Si 1-x Ge x NS channel device characteristics. It is found that the compressively strained Si 1-x Ge x NS channel provides a 100% uplift in peak hole mobility with a corresponding channel resistance reduction of 40% while maintaining an excellent subthreshold slope of below 70 mV/dec.

We present the first Embedded Spin-Transfer-Torque MRAM (eMRAM) technology in a 14 nm CMOS node. A novel integration supports the highest eMRAM density (0.0273 um2 cell size), optimal magnetic tunnel junction (MTJ) placement between M1-M2 for performance and density, and the lowest-cost integration scheme, with only 3 added mask levels (2 critical + 1 non-critical) and a single added electrode module. An advanced 400°C-compatible MTJ stack is read and written by innovative reference-cell sensing circuitry. We demonstrate digital functionality and write performance down to 4 ns, with companion parametric analysis for magnetoresistance, switching voltage, retention, and endurance cycling. Finally, we checked the 14 nm eMRAM hardware BEOL EM and TDDB at the critical levels, verifying good reliability after the embedding process.

The continuously growing demands in high-density memories drive the rapid development of advanced memory technologies. In this work, we investigate the HfOx-based resistive switching memory (ReRAM) stack structure at nanoscale by high resolution TEM (HRTEM) and energy dispersive X-ray spectroscopy (EDX) before and after the forming process. Two identical ReRAM devices under different electrical test conditions are investigated. For the ReRAM device tested under a regular voltage bias, material redistribution and better bottom electrode contact are observed. In contrast, for the ReRAM device tested under an opposite voltage bias, different microstructure change occurs. Finite element simulations are performed to study the temperature distributions of the ReRAM cell with filaments formed at various locations relative to the bottom electrode. The applied electric field as well as the thermal heat are the driving forces for the microstructure and chemical modifications of the bottom electrode in ReRAM deceives.

Ring Oscillators (ROs) are used for yield learning during the research phase of a CMO technology. We performed cross-sections and showed that the open and short defects are in the middle of line (MOL) gate structures. The defects which are related to MOL or prior processes, as well as the design and density, will be discussed in the paper.

In this paper, horizontal gate-all-around (hGAA) devices with a SiGe cladded nanosheet (NS) channel have been explored for their potential benefits of Vt modulation and improved NBTI. The SiGe cladded NS channel was formed through trimming of the Si NS channel followed by selective SiGe epitaxial growth. Selective Si NS channel trimming of 1 - 2 nm per side with low roughness and conformal SiGe cladding epitaxial growth of 2 - 3 nm with good crystallinity were demonstrated. It is shown that a SiGe cladding NS channel provides a reduction of threshold voltage (Vt) and improved reliability. It is also shown that a conformal Si cap grown on the SiGe cladded NS channel suppresses the interface trap density (Dit).

We report that n-dipole and p-dipole (dual dipoles) can be co-integrated to provide a more flexible volumeless multiple threshold voltage(multi-Vt) solution in FinFET and Nanosheet (NS) technologies. The p-dipole process for dual dipoles co-integration is identified. When the Vt shift is less than 100m V, the mobility is slightly degraded, but other properties are not clearly affected. The improved pFET performance is from the Vt reduction. The dipole co-integration also provides a novel method for Vt definition via dipole Vt compensation. Our selective dipole enablement can implement near bandedge (BE) multi- Vt for high performance application.

In Nanosheet (NS) device architecture, it is much more challenging than FinFET to develop a suitable multiple threshold voltage (multi-Vt) integration with more restrictive requirement on the dimensions due to the critical dimension scaling and complex structure. In this abstract, we reported an innovative integration scheme to enable volumeless multi-Vt and metal multi-Vt to provide the multi-Vt solutions in NS technology for high performance computing (HPC) and low-power applications. We developed a new volumeless multi-Vt for NS to solve the device geometry constraint and offer more margin and the opportunity for further sheet-to-sheet spacing (Tsus) reduction. Furthermore, metal gate boundary control (MGBC) was developed to enable variable NS widths on the same wafer to satisfy both HPC and low-power applications.

In this paper, full bottom dielectric isolation (BDI) is first demonstrated on horizontally stacked Nanosheet device structures with Lmetal 12 nm. The comparison of full BDI scheme vs punch through stopper (PTS) scheme has been systematically studied. By comparing off-state leakage current, short channel behavior and effective capacitance (Ceff) for both schemes, we show that BDI could potentially provide: 1) good immunity of sub-channel leakage due to process variation (from parasitic "fat-Fin" which is unique in Nanosheet structure); 2) power-performance co-optimization.

We combine advanced transmission electron microscopy (TEM) and numerical models to draw the evolution of strains over the integration of horizontally stacked Gate-All-Around Nanosheet transistors (GAANS). In particular, we measured compressive strains of -0.5% to -1% after channel release in transistors at 10 nm design rule. With support on model calculations, we speculate that the effect is related to a compressive inter-layer dielectric (ILD). As another method to manipulate channel stresses, in a specifically designed GAANS we demonstrate a transition from compressive to tensile strain introduced by a gate stack/contact test modules. Finally, a demonstration of GAANS Si-channel cladded with SiGe opens a way for the co-integration of compressive SiGe channels with limited modification of the integration flow. The findings provide insights and guidelines for strain engineering in GAANS.

Breakdown and bias temperature instability for n/pFETs are studied on a wide composition of SiGe channels on different strain relaxation buffers. This study represents the first in-depth look at AC/DC PBTI trends of low Ge% SiGe nFinFETs. Dielectric breakdown is shown to be largely independent of channel composition over the region studied. Finally, we calculate the end-of-life performance benefit compared to Si, demonstrating the potential benefit of CMOS SiGe as a technology element.

This paper analyzes and compares three different types of detectors, including CMOS power detectors, bipolar power detectors, and super-regenerative detectors, deployed in the literature for integrated microwave/mm-wave imaging systems in mainstream silicon technologies. Each detector has unique working mechanism and demonstrates different behavior with respects to bias conditions, input signal power, as well as bandwidth responses. Two Figure-of-Merits for both wideband and narrowband imaging have been defined to quantify the detector performance comparison. CMOS and Bipolar detectors are good for passive imaging, while super regenerative detectors are superior for active imaging. The analytical results have been verified by both simulation and measurement results. These analyses intend to provide design insights and guidance for integrated microwave/mm-wave imaging power detectors.

For the first time, high electron mobility in tensile-strained SiGe channel nFinFETs outperforming Si is reported to explore the feasibility of high performance SiGe CMOS. To examine the electron mobility behaviors in SiGe channel, a series of tensile-strained SiGe nFinFETs are fabricated on various strain relaxed buffer layers by taking into account the minimum threading dislocation density and strain engineering. For SiGe $(\text{Ge} > 20\%)$ nFinFETs, we identify the existence of additional electron trapping site close to the conduction band edge in IL/HK, leading to the abnormal Vt shift, PBTI degradation, and low electron mobility. We also fabricated short-channel SiGe nFinFETs, which exhibit excellent cut-off behavior and electrostatics (SS ∼65mV/dec and DIBL ∼18mV at $\mathrm{V}_{\text{DD}}=0.7\mathrm{V}$ ). In addition, the dynamic performance of tensile-strained SiGe CMOS against Si CMOS is evaluated by TCAD simulation based on experimental data.

The impacts of ruthenium and cobalt liners on copper resistivity have been investigated at beyond 7nm dimensions. Liner metal conduction was carefully evaluated in a Cu resistivity derivation using the temperature coefficient of resistivity (TCR) approach. Cu resistivity with Ru liner is higher than with a Co liner by 10-15%, which is verified by RC plot. The resistivity difference is attributed to interface scattering and possibly grain boundary scattering. Interface ab initio calculations show 3-7% increase of Cu resistivity from Co liner to Ru liner.

As BEOL pitch continues to aggressively scale, contributions from pattern dimension and edge placement constrict the available geometry of interconnects. In particular, the critical minimum insulator spacing which defines a technologies max operating voltage is now limited by Vx to Mx spacing. This spacing has historically been a challenge since the introduction of self-aligned vias due to the loss of CD and chamfer control in the non-self-aligned direction. As pitch continued to shrink from self-aligned via introduction around the 22 nm node, the fraction of via CD control and edge placement compared to the dielectric spacing between interconnects has continued to grow. Alone this trend could be combated by increasing the dielectric spacing, however, the exponential increase in Cu resistivity (under scaling) has forced BEOL technologies into strong line/space asymmetry to keep line resistance under control. At pitches below 32 nm these factors reach a tipping point, either design to exponentially increasing line resistance or lower the technology Vmax. Both approaches cause performance degradation to achieve pitch scaling

A high-speed, track-and-hold amplifier and interleaved CMOS sample-and-hold circuit are implemented in an InP-on-CMOS fabrication process. Conventional 50- $\Omega $ interchip interconnects between III-V and CMOS circuits are eliminated with heterogeneous integration of III-V on CMOS, yielding higher performance circuits at lower power consumption. The track-and-hold amplifier is based on a double-switching feedback architecture using 250 nm InP HBTs and achieves an IIP3 of 19 dBm at a sampling rate of 30 GS/s. To the author's knowledge, this is the first published result of a high-speed track-and-hold amplifier in an InP BiCMOS process and the first implementation of a feedback linearized track-and-hold at a sampling rate above 2 GS/s. Additionally, a novel HBT buffer with feedback is demonstrated to offer high linearity and low power for driving time-interleaved CMOS sample-and-hold circuits. A 90 nm time-interleaved CMOS sample-and-hold circuit is demonstrated to achieve better than $-$ 53 dBc ${\rm HD}_3$ at a sampling rate of 5 GS/s while consuming roughly 24 mW per channel.

Programmable active bandpass filters (BPFs) have been designed in a chip-scale heterogeneous integration technology, which intimately integrates InP HBTs on a deep scaled CMOS technology. Therefore, the active BPF can leverage both high performance of InP HBT and high density and programmability of CMOS. Two BPF prototypes, consisting of a programmable gain amplifier (PGA), a fifth- or third-order BPF core, and a buffer, have been designed and fabricated. The BPF center frequency can be switched from 0.8 to 2.2 GHz with 150-MHz passband and delivers ${>}{\hbox{55}}$ -dB out-of-band (OOB) rejection for the fifth-order one. Four gain steps: 0, 6, 12, and 16 dB, are enabled by the front PGA to trade off noise and linearity performances. Due to the ${>} {\hbox{300}}$ -GHz ${ f}_{ T}$ of InP HBTs, the BPF cores can leverage active-RC architecture for high linearity owing to the close-loop implementation. The fifth-order BPF prototype occupies a 1.5 $\,\times\,$ 1.02 mm $^{2}$ area together with pads and draws 106/121 mA from a 3.3-V power supply for 0.8/2.2-GHz bands, respectively, which demonstrates OOB output third-order intercept points (OIP3s) of 22.69/21.25 dBm for 0.8/2.2-GHz bands at the high gain mode. The measurement results suggest the fifth-order BPF core achieves 36.69/35.25-dBm OOB OIP3s. In addition, the designed third-order programmable BPF has been successfully used as a technology yield vehicle to assist the BiCMOS technology development.

Pre-strained fin-patterned Si/SiGe multilayer structures for sub-7 nm stacked gate-all-around Si-technology transistors that have been grown onto bulk-Si, virtually relaxed SiGe, strained Silicon-On-Insulator, and compressive SiGe-On-Insulator were investigated. From strain maps with a nanometer spatial resolution obtained by transmission electron microscopy, we developed 3D quantitative numerical models describing the mechanics of the structures. While elastic interactions describe every other system reported here, the patterning on the compressive SiGe-On-Insulator substrate that is fabricated by Ge-condensation results in relaxation along the semiconductor/insulator interface, revealing a latent plasticity mechanism. As a consequence, Si layers with a uniaxial stress of 1.4 GPa are obtained, bringing fresh perspectives for strain engineering in advanced devices. These findings could be extended to other semiconductor technologies.

Converting SOI to sSOI through Amorphization and Crystallization: Material Analysis and Device Demonstration S. Maitrejean,a,z N. Loubet,b E. Augendre,a P. Morin,b S. Reboh,c N. Bernier,c R. Wacquez,a B. Lherron,b A. Bonnevialle,c,d Q. Liu,b J. M. Hartmann,c,∗ H. He,e A. Halimaoui,d J. Li,e S. Pilorget,b J. Kanyandekwe,b L. Grenouillet,c F. Chafik,b Y. Morand,d C. Le Royer,c O. Faynot,a M. Celik,b B. Doris,e and B. De Salvoa

Strained Si 1−x Ge x channel pFinFETs and planar pFETs are fabricated on a strain relaxed buffer virtual substrate to comparatively study the electrical impact of strain and Ge content in the Si 1−x Ge x channel. By comparing the transistor electrical properties of Si 1−x Ge x pFETs on SRB with Si 1−x Ge x pFETs on Si substrate, we successfully decouple the influence of strain and Ge content in the Si 1−x Ge x channel on device performance such as gate stack quality, reliability, and carrier transport. Based on these understandings, dual channel Si/Si 1−x Ge x FinFETs on the SRB with the optimized surface orientation is proposed to further improve the device performance.

A fully aligned via (FAV) integration scheme is introduced and demonstrated at 36 nm metal pitch, with extendibility to beyond the 7 nm node. Selective chemistries were developed to recess Cu and W wires and their associated barrier liner materials, so as to create local topography with no adverse effects on these wiring levels or their dielectrics. Dielectric cap layers were optimized for excellent via RIE selectivity, to act as via guiding structures during subsequent level pattern definition. This combination mitigates via overlay and critical dimension (CD) errors. FAV integration can enable line/via area scaling for 70% lower line resistances and 30% larger via contact areas at the same node. Concurrently, FAV improves TDDB reliability through increased minimum insulator spacing, and EM reliability by maximizing via/wire contact area.

For beyond 7 nm node BEOL, line resistance (R) is assessed among four metallization schemes: Ru; Co; Cu with TaN/Ru barrier, and Cu with through-cobalt self-forming barrier (tCoSFB) [1]. Line-R vs. linewidth of Cu fine wires with TaN/Ru barrier crosses over with barrier-less Ru and Co wires for beyond-7 nm node dimensions, whereas Cu with tCoSFB remains competitive, with the lowest line R for 7 nm and beyond. Our study suggests promise of this last scheme to meet requirements in line R and EM reliability.

In this paper, for the first time we demonstrate that horizontally stacked gate-all-around (GAA) Nanosheet structure is a good candidate for the replacement of FinFET at the 5nm technology node and beyond. It offers increased W eff per active footprint and better performance compared to FinFET, and with a less complex patterning strategy, leveraging EUV lithography. Good electrostatics are reported at L g =12nm and aggressive 44/48nm CPP (Contacted Poly Pitch) ground rules. We demonstrate work function metal (WFM) replacement and multiple threshold voltages, compatible with aggressive sheet to sheet spacing for wide stacked sheets. Stiction of sheets in long-channel devices is eliminated. Dielectric isolation is shown on standard bulk substrate for sub-sheet leakage control. Wrap-around contact (WAC) is evaluated for extrinsic resistance reduction.

Co/Cu composite interconnect systems were studied. Since wide Cu lines require a diffusion barrier which is simultaneously applied also to fine Co lines to reduce Co volume fraction, through-Cobalt Self-Formed-Barrier (tCoSFB) was employed to thin down TaN barrier to

Historically, compound semiconductors have enjoyed the benefit of material properties that lend themselves to high performance electron devices, but the ability to fabricate complex, high transistor count ICs is limited by the relative immaturity of the material system and small commercial market. Silicon based devices have made significant advances in device performance, but have not yet matched compound semiconductor device performance. However, a large commercial market has allowed the silicon system to mature and produce billion transistor count ICs in high volume. It would be advantageous to combine the merits of both compound semiconductors and silicon based CMOS/BiCMOS to enable a new class of high performance ICs. This work will review HRL's efforts in wafer scale integration of an advanced 250nm, 350GHz fT/fMAX InP DHBT technology with RF-CMOS technologies whose device proximity; heterogeneous interconnect density; and additional technology features both leverage and provide additional value to conventional silicon technologies.

For the first time, we report integration of air spacers with FinFET technology at 10nm node dimensions. The benefit of parasitic capacitance reduction by air spacers has been successfully demonstrated both at transistor level (15–25% reduction in overlap capacitance (C OT )) and at ring oscillator level (10–15% reduction in effective capacitance (Cf)). Key process challenges and device implications of integrating air spacers in FinFET are identified. We propose a partial air spacer scheme, in which air spacers are formed only above fin top and sandwiched by two dielectric liners, as a viable option to adopt air spacers in FinFET technology with minimal risks to yield and reliability.

We present a 7nm technology with the tightest contacted poly pitch (CPP) of 44/48nm and metallization pitch of 36nm ever reported in FinFET technology. To overcome optical lithography limits, Extreme Ultraviolet Lithography (EUV) has been introduced for multiple critical levels for the first time. Dual strained channels have been also implemented to enhance mobility for high performance applications.

InP DHBTs are receiving a great deal of attention for its potential in the yet, undefined, 5G systems. In this paper, "waterfall" curves are evaluated for InP DHBTs at 900MHz and show that it can provide an improvement in PAE at low voltages (10% better than GaAs or SiGe HBTs). RF Knee MAG/MSG metrics at 5.4GHz and 15.4 GHz as compared to GaAs HBTs were also measured. These measurements indicate in some bias regions, InP can provide a large advantage in RF Gain compared to GaAs. These results demonstrate that InP DHBTs have significant potential for envelope tracking (ET) and average power tracking (APT) at conventional frequencies (

For the first time, we have demonstrated a 32nm high-k/metal gate (HK-MG) low power CMOS platform technology with low standby leakage transistors and functional high-density SRAM with a cell size of 0.157 μm2. Record NMOS/PMOS drive currents of 1000/575 μA/μm, respectively, have been achieved at 1 nA/μm off-current and 1.1V Vdd with a low cost process. With this high performance transistor, Vdd can be further scaled to 1.0V for active power reduction. Through aggressive EOT scaling and band-edge work-function metal gate stacks, appropriate Vts and superior short channel control has been achieved for both NMOS and PMOS at L gate=30nm. Compared to SiON-Poly, 30% RO delay reduction has been demonstrated with HK-MG devices. 40% Vt mismatch reduction has been shown with the Tinv scaling. Furthermore, it has been shown that the 1/f noise and transistor reliability exceed the technology requirements. © 2008 IEEE.

SiGe for channel material has been explored as a major technology element after the introduction of FINFET into CMOS technology [1–4]. Research on long channel FETs and discrete short channel FETs demonstrated benefits in mobility [1–4] and reliability [2]. Given the disruption that SiGe FIN brings, every aspect associated with SiGe FIN needs to be carefully studied towards technology insertion. In this paper, we report the latest SiGe-based FINFET CMOS technology development. CMOS FINFETs with Si-FIN nFET and SiGe-FIN pFET is demonstrated as a viable technology solution for both server and mobile applications at 10nm node and beyond.

We discuss the transition to Ti based silicides for source-drain (SD) contacts for 3D FinFET devices starting from the 14nm node & beyond. Reductions in n-FET & p-FET contact resistances are reported with the optimization of metallization process & dopant concentrations. The optimization of SiGe epitaxy and addition of a thin interfacial NiPt(10%) are found to significantly improve p-FET contact performance.

The noise performance of an InP BiCMOS process is presented. The process builds on IBM 90-nm RF CMOS and features heterogeneously integrated 250-nm InP DHBTs with f t /fmax values of ~300 GHz. Noise models have been extracted and the predicted performance agrees well with measurement. The results indicate that this technology is an excellent option for future millimeter-wave low-noise applications.

Modulation of Cu interconnect microstructure in a low-k dielectric was achieved at an elevated anneal temperature of 250 °C. In contrast to the unpassivated conventional structure, a TaN metal passivation layer was deposited on the plated Cu overburden surface before annealing at the elevated temperature to prevent stress migration reliability degradation. As compared with the conventional structure annealed at 100 °C, the elevated annealing process enabled further Cu grain growth, which then resulted in an increased Cu grain size and improved electromigration resistance in the interconnects.

Uniaxial tensile strain in the channel enhances electron mobility and hence the drive current in an N-type field-effect transistor (NFET). For enhancement of NFET drive current via channel strain, the incorporation of embedded silicon carbon (eSi:C) alloys in the source/drain region has been investigated extensively. We have explored epitaxially grown embedded Si:C alloys for NFET source / drain stressor. The use of epitaxially grown intrinsic Si:C has a significant disadvantage due to incompatability with downstream processing. In situ phosphorus doped Si:C shows much more promise, especially from a strain retention perspective post growth.

Differential amplifiers incorporating the advantages of both Si and III-V technologies have been fabricated in a wafer scale, heterogeneously integrated, process using both 250 nm InP DHBTs and 130 nm CMOS. These ICs demonstrated gain-bandwidth product of 40-130 GHz and low frequency gain > 45 dB . The use of InP DHBTs supports a > 6.9 V differential output swing and a slew rate > 4 times 104V/mus to be achieved with as low as 40 mW dissipated power. A novel on-chip buffer circuit is used to facilitate the on-wafer characterization of these amplifiers. To the authors' knowledge, this is the first demonstration of a high performance IC building block in a heterogeneously integrated process technology.

On the Compound Semiconductor Devices and CMOS (CoSMOS) program, HRL Laboratories, LLC is developing technology for intimate integration of silicon complementary metal-oxide- semiconductor (CMOS) devices with 400 GHz InP heterogeneous bipolar transistor (HBTs) to form complex integrated circuits. This research is investigating innovative microfabrication approaches, including adhesive bonding techniques, for transistor-scale integration of compound semiconductor and silicon-based transistors. We have successfully fabricated large area HBT's on thin (~1 µm) InP epitaxial layers transferred to silicon substrates with a die to wafer bonding process that preserves the growth orientation of the epitaxial layers bonded to the target substrate.

The high operating power density and aggressively scaled geometries associated with 400+ GHz InP-Based DHBTs present a new challenge in device design and thermal management. In order to assess the effects of self-heating on the RF performance, S -parameters of six InP DHBTs with varying emitter dimensions were measured over a 75 °C ambient temperature range. An 8–10% increase in peak f T is observed as the temperature is reduced. Data analysis indicates that reductions in the base and collector transit times and the base–emitter charging times are responsible for the peak f T improvement. The calculated electron velocities exceed 6 × 10 7 cm/s, indicating velocity overshoot plays a critical role in the reduction of the transit times. When emitter scaling are considered, the total transit time variation is directly correlated to the rise in junction temperature. Using previously measured thermal resistance values, a 77–116 °C minimum junction temperature rise is estimated from self-heating. Therefore, the 8–10% increase in peak f T is a reasonable estimate of the performance to be recovered by minimizing self-heating. Improved intra-device thermal management through device design is an important supplement to geometry scaling as a means to enhance device performance.

Recent attempts to achieve 400 GHz or higher fT and f MAX with InP heterojunction bipolar transistors (HBTs) have resulted in aggressive scaling into the deep submicrometer regime. In order to alleviate some of the traditional mesa scaling rules, several groups have explored selectively implanted buried subcollectors (SIBS) as a means to decouple the intrinsic and extrinsic collector design. This allows tauC to be minimized without incurring a large total CBC increase, and hence, a net improvement in fT and fMAX is achieved. This paper represents the first investigation into the series resistance and capacitance characteristics of submicrometer-width SIBS regions (as narrow as 350 nm) for InP double HBTs. Although the SIBS resistance is higher than that of epitaxially grown layers, the SIBS concept is able to provide good dopant activation and a significant decrease in CBC. S-parameter measurements are presented to clarify the impact of SIBS geometry variations, caused by both intentional device design and process variations, on fT and fMAX. Parasitic resistances and high background doping limit the fT improvement, but the CBC reduction is sufficient to demonstrate a 30% increase in fMAX. Results indicate that further improvements in fT and fMAX using the SIBS concept will be possible

Traditional compound semiconductor HBT technologies do not allow for the independent design of the intrinsic and extrinsic collector regions commonly found in Si BJT and SiGe HBT technologies. By using a selectively implanted buried sub-collector (SIBS) to optimize the intrinsic collector for reduced transit time and extrinsic collector for reduced capacitance, InP DHBTs technologies can finally have the same flexibility. An improved 200 GHz InP DHBT technology for broadband amplifiers with good forward Gummel characteristics and a DC current gain exceeding 100 is presented. SIBS also allows the fabrication of two types of HBTs, one with a peak fT/fMAX of 208 GHz/225 GHz at IC = 26.2 mA and one with a peak fT/fMAX of 148 GHz/237 GHz at IC = 16.6 mA, on a single wafer, giving the circuit designer additional flexibility. A state of the art traveling wave amplifier with a 61 GHz 3 dB-bandwidth, 29 dB differential gain, and only 2.5 W total power dissipation is presented. At a 45 Gb/s data rate, a 11 V differential output swing is demonstrated while maintaining