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A comprehensive quantitative root cause study of defect evolution leading to memory window closure from a charge balance and charge trapping perspective throughout all phases of a Si channel Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect-transistor (FEFET) is reported. Starting with the first write pulse, an excessive SiO2 interlayer field is revealed that triggers the creation of defect levels Dit in excess of 1015 cm−2 eV−1 at the HZO–SiO2 interface screening ferroelectric (FE) polarization while enabling FE switching. Under subsequent early bipolar fatigue cycling (up to 104 cycles), defect creation commences at the SiO2–Si interface due to the high injected hole fluence (0.39 C/m2) during each stress pulse causing negative bias instability (NBI), which shifts the threshold voltage of the erase state VT,ERS by −0.3 V with accrual of permanently captured charge Nit of up to +5 × 10−3 C/m2 (3 × 1012 cm−2). Subsequently, Nit NBI generation at the SiO2–Si interface accelerates reaching levels of +7 × 10−2 C/m2, locking both FEFET program and erase drain current vs gate–source-voltage (ID–VGS) characteristics in the FEFET on-state inducing memory window closure at 105 cycles while FE switching (switched polarization Psw = 0.34 C/m2) remains essentially intact. These findings guide the down-selection toward suitable semiconductor/FE systems for charge balanced, reliable, and high endurance FEFETs. [ABSTRACT FROM AUTHOR]

The article focuses on devices Spin Torque Majority Gates (STMG) and Spin Wave Majority Gates (SWMG) device based on spintronic phenomena developed by the Interuniversity Micro-Electronics Center (IMEC) to bring changes in computing and scaling. Topics discussed include challenges faced by the complementary metal-oxide semiconductor (CMOS) device density scaling; process of information encoding in STMG and SWMG; CMOS based and spin logic devices to enhance and complement.

This paper reports a teaching experiment in which two students engaged in tasks that challenged them to describe a final state for a variety of infinite iterative processes. The results from the study indicate that the students used multiple reasoning strategies for addressing these tasks. Refinements in the students' reasoning occurred as students constructed relationships between the problems they were solving and problems they had solved previously, applying some of the reasoning strategies that they used for one problem to make sense of or solve another problem. We discuss how these findings relate to the existing body of research on infinite iterative processes. [ABSTRACT FROM AUTHOR]

Quasi-particles with fractional charge and statistics, as well as modified Coulomb interactions, exist in a two-dimensional electron system in the fractional quantum Hall (FQH) regime. Theoretical models of the FQH state at filling fraction v = 5/2 make the further prediction that the wave function can encode the interchange of two quasi-particles, making this state relevant for topological quantum computing. We show that bias-dependent tunneling across a narrow constriction at v = 5/2 exhibits temperature scaling and, from fits to the theoretical scaling form, extract values for the effective charge and the interaction parameter of the quasi-particles. Ranges of values obtained are consistent with those predicted by certain models of the 5/2 state. [ABSTRACT FROM AUTHOR]

Recent theories suggest that the quasiparticles that populate certain quantum Hall states should exhibit exotic braiding statistics that could be used to build topological quantum gates. Confined systems that support such states at a filling fraction ν=5/2 are of particular interest for testing these predictions. Here, we report transport measurements of just such a system, which consists of a quantum point contact (QPC) in a two-dimensional GaAs/AlGaAs electron gas that itself exhibits a well-developed fractional quantum Hall effect at a bulk filling fraction νbulk=5/2. We observe plateau-like features at an effective filling fraction of νQPC=5/2 for lithographic contact widths of 1.2 μm and 0.8 μm, but not 0.5 μm. Transport near νQPC=5/2 in the QPCs is consistent with a picture of chiral Luttinger-liquid edge states with inter-edge tunnelling, suggesting that an incompressible state at νQPC=5/2 forms in this confined geometry. [ABSTRACT FROM AUTHOR]

In this article, a 0.7 nm thick monolayer MoS2 nanosheet gate-all-around field effect transistors (NS-GAAFETs) with conformal high- κ metal gate deposition are demonstrated. The device with 40 nm channel length exhibits a high on-state current density of ~410 μ A μ m−1 with a large on/off ratio of 6 × 108 at drain voltage = 1 V. The extracted contact resistance is 0.48 ± 0.1 kΩ μ m in monolayer MoS2 NS-GAAFETs, thereby showing the channel-dominated performance with the channel length scaling from 80 to 40 nm. The successful demonstration of device performance in this work verifies the integration potential of transition metal dichalcogenides for future logic transistor applications. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

To continue with the scaling of high-performance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III–V materials, such as In0.53Ga0.47As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In0.53Ga0.47As, monolayer black phosphorus (BP), and WS2-based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In0.53Ga0.47As for planar device architectures. However, compared to modern s-Si and In0.53Ga0.47As Fin and NW FETs, monolayer BP and WS2 double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes. [ABSTRACT FROM AUTHOR]

In this work, we develop an ultrathin epitaxial h-AlN as an interfacial layer (IL) between HfO2 and monolayer WS2 channel by atomic layer deposition (ALD). The growth of ultrathin dielectrics using ALD has been challenging due to the dangling-bond-free surface of 2D materials. By utilizing sub-1 nm h-AlN as an IL and depositing HfO2 high-k dielectric, we were able to form a uniform and atomically flat gate dielectric without voids. The resulting structure exhibits an equivalent oxide thickness as low as 1 nm and ultra-low leakage currents of ∼10−6 A/cm2. The fabricated top-gate WS2 transistors demonstrate on-off ratios of around 106 and subthreshold swing as low as 93 mV/dec. Furthermore, we have verified the feasibility of using h-AlN IL for a gate-all-around structure. Our work presents a CMOS-compatible low-temperature ALD process for integrating gate dielectrics, offering excellent thickness scalability and uniform coverage around monolayer WS2 nanosheets. The combination of high-quality two-dimensional dielectrics and semiconductors will contribute to the development of future high-performance and low-power electronic devices. [ABSTRACT FROM AUTHOR]

A correction to the article "Refinements in mathematics undergraduate students' reasoning on completed infinite iterative processes" that is published in this issue is presented.

Anisotropic growth of two-dimensional (2D) tungsten disulfide (WS2) crystals occurs during atomic layer deposition (ALD) from WS2 seeds at predetermined locations on large area dielectric substrates. The number of ALD reaction cycles determines the lateral dimensions of the WS2 crystals. This 2D synthesis approach is compatible with temperature sensitive structures due to the low deposition temperature and can be extended to other 2D materials and heterostructures thereof. The crystallinity of the seed and the selectivity of ALD precursors toward seeds and underlying starting surface affect the structural quality of the 2D crystals. [ABSTRACT FROM AUTHOR]

In the context of neuromorphic computation, spintronic memristors are investigated for their use as synaptic weights. In this paper, we propose and experimentally demonstrate a resistive synaptic device based on ten magnetic tunnel junctions (MTJs) connected in a serial configuration. Our device exhibits multiple resistance levels that support its use as a synaptic element. It allows for two operating knobs: external magnetic field and voltage pulses (Spin-Transfer Torque). Moreover, it can be operated in different ways. When varying continuously the amplitude of the voltage pulse and/or the magnetic field, eleven resistance states can be reached. In contrast, if the initial state of the chain is reset between every step, a very large number of levels are reached. Ideally, a total of 2 N resistance levels could be accessible. This coincides well with the desired analog-like behavior in ideal memristors. Since this device consists of a scalable number of N MTJs, and MTJ technology is continuously optimized and improved, the proposed memristor shows promise as a scalable synapse solution for neuromorphic hardware implementations. [ABSTRACT FROM AUTHOR]

Conventional junctionless (JL) multi-gate (MuG) field-effect transistors(FETs) require extremely scaled channels to deliver high on-state current with low short-channel effect related leakage. In this letter, using ultra-thin 2D materials (e.g., monolayer MoS2), we present comparison of short-channel effects in JL, and inversion-mode (IM) FETs. We show that JL FETs exhibit better sub-threshold slope (S.S.) and drain-induced-barrier-lowering (DIBL) in comparison to IM FETs due to reduced peak electric field at the junctions. But, threshold voltage (VT) roll-off with channel length downscaling is found to be significantly higher in JL FETs than IM FETs, due to higher source/drain controlled charges (dE/dx) in the channel. Further, we show that although VT roll-off in JL FETs improves by increasing the gate control, i.e., by scaling the oxide, or channel thickness, the sensitivity of threshold voltage on structural parameters is found out to be high. [ABSTRACT FROM AUTHOR]

Achieving low resistance contacts to graphene is a common concern for graphene device performance and hybrid graphene/metal interconnects. In this work, we have used the circular Transfer Length Method (cTLM) to electrically characterize Ag, Au, Ni, Ti, and Pd as contact metals to graphene. The consistency of the obtained results was verified with the characterization of up to 72 cTLM structures per metal. Within our study, the noble metals Au, Ag and Pd, which form a weaker bond with graphene, are shown to result in lower contact resistance (Rc) values compared to the more reactive Ni and Ti. X-ray Photo Electron Spectroscopy and Transmission Electron Microscopy characterization for the latter have shown the formation of Ti and Ni carbides. Graphene/Pd contacts show a distinct intermediate behavior. The weak carbide formation signature and the low Rc values measured agree with theoretical predictions of an intermediate state of weak chemisorption of Pd on graphene. [ABSTRACT FROM AUTHOR]

In this work, we report on the sensitivity of photo-electrical detection of magnetic resonances (PDMR) for magnetometry measurement using low density nitrogen vacancy (NV) ensembles in CVD-grown diamond. We demonstrate that the selection of the laser excitation wavelength is of importance for achieving optimal magnetic field sensitivity. The PDMR sensitivity obtained using a yellow-green (561 nm) laser surpasses the performances of a green laser (532 nm), by suppressing the photoionization of defects other than NV centers (such as P1 centers). It consequently allows to carry out the PDMR measurements at lower laser powers with increased magnetic resonance contrast. Noticeably for both the green and the yellow-green illuminations, PDMR leads to an improved sensitivity to magnetic fields in the selected conditions compared to optically detected magnetic resonance. [ABSTRACT FROM AUTHOR]

We present an investigation on the role of temperature and electric field as driving forces in the initiation of the resistive switching processes. The impact of temperature in both on- and off-states is analyzed in detail, using an electrothermal numerical model formulation. dc and pulsed temperature-dependent data, collected on scaled crossbar test structure cells, serially connected with an on-chip control transistor, are used to extract material information and are furthermore analyzed in conjunction with model outputs. With these results, further discussion is presented, suggesting points of attention for scaled cell design in the below-10-nm realm. [ABSTRACT FROM AUTHOR]

The functionality of a cross-shaped Spin Torque Majority Gate (STMG) is primarily limited by the pinning of a domain wall (DW) at the center of the device. Here, an analytical model is built to calculate the conditions for such a pinning and to deduce the operating range. The assumptions of the model and the conclusions are validated by micromagnetic simulations. The total magnetic energy of the DW state is derived. By minimizing this energy with respect to two degrees of freedom, the DW stability condition is obtained. We find that the lateral length of the STMG is the critical dimension: it must be smaller than about five times the DW width. This result is confirmed by micromagnetic simulations with a high accuracy. In process, we solved a more fundamental problem: the macrospin limit of a finite ferromagnet containing one pinning site. We found the correction of the usual DW width expression due to finite length of wires. [ABSTRACT FROM AUTHOR]

Perpendicular Magnetic Anisotropy (PMA) is a key requirement for state of the art Magnetic Random Access Memories (MRAM). Currently, PMA has been widely reported in standard Magnetic Tunnel Junction material stacks using MgO as a dielectric. In this contribution, we present the first report of PMA at the interface with a high-j dielectric grown by Atomic Layer Deposition, HfO2. The PMA appears after annealing a HfO2\Co\Pt\Ru stack in N2 with the Keff of 0.25 mJ/m² as determined by Vibrating Sample Magnetometry. X-Ray Diffraction and Transmission Electron Microscopy show that the appearance of PMA coincides with interdiffusion and the epitaxial ordering of the Co\Pt bilayer. High-κ dielectrics are especially interesting for Voltage Control of Magnetic Anisotropy applications and are of potential interest for low-power MRAM and spintronics technologies. [ABSTRACT FROM AUTHOR]

Charge trapping is arguably the most important detrimental mechanism distorting the ideal characteristics of MOS transistors, and nonradiative multiphonon (NMP) models have been demonstrated to provide a very accurate description. For the calculation of the NMP rates at room temperature or above, simple semiclassical approximations have been successfully used to describe this intricate mechanism. However, for the computation of charge transition rates at cryogenic temperatures, it is necessary to use the full quantum mechanical description based on Fermi’s golden rule. Since this is computationally expensive and often not feasible, we discuss an efficient method based on the Wentzel–Kramers–Brillouin (WKB) approximation in combination with the saddle point method and benchmark this approximation against the full model. We show that the approximation delivers excellent results and can, hence, be used to model charge trapping behavior at cryogenic temperatures. [ABSTRACT FROM AUTHOR]

We present time-zero characterization and an investigation on bias temperature instability (BTI) degradation between 4 and 300 K on large area high- ${k}$ CMOS devices. Our measurements show that negative BTI (NBTI) on pMOSFETs freezes out when approaching cryogenic temperatures, whereas there is still significant positive BTI (PBTI) degradation in nMOSFETs even at 4 K. To explain this behavior, we use an efficient implementation of the quantum mechanical nonradiative multiphonon charge trapping model presented in Part I and extract two separate trap bands in the SiO2 and HfO2 layer. We show that NBTI is dominated by defects in the SiO2 layer, whereas PBTI arises mainly from defects in the HfO2 layer, which are weakly recoverable and do not freeze out at low temperatures due to dominant nuclear tunneling at the defect site. [ABSTRACT FROM AUTHOR]

The article focuses on the properties and technological application of two-dimensional (2D) crystals such as graphene and transition metal dichalcogenides. Topics include the capacity of graphene to serve as alternative to silicon (Si)-based transistors, its application on nano-based stacks materials composed of 2D materials such as insulators, metals and semiconductors, and the challenges related to 2D materials manufacturing processes such as gate engineering, patterning, and doping.

Spin wave modes in magnetic waveguides with the width down to 320 nm have been studied by electrical propagating spin-wave spectroscopy and micromagnetic simulations for both longitudinal and transverse magnetic bias fields. For longitudinal bias fields, a 1.3 GHz wide spin-wave band was observed in agreement with analytical dispersion relations for uniform magnetization. However, the transverse bias field led to several distinct bands, corresponding to different quantized width modes, with both negative and positive slopes. Micromagnetic simulations showed that, in this geometry, the magnetization was nonuniform and tilted due to the strong shape anisotropy of the waveguides. Simulations of the quantized spin-wave modes in such nonuniformly magnetized waveguides resulted in spin wave dispersion relations in good agreement with the experiments. [ABSTRACT FROM AUTHOR]

Spin logic devices based on domain wall (DW) motion offer flexible architectures to store and carry logic information in a circuit. In this device concept, information is encoded in the magnetic state of a magnetic track shared by multiple magnetic tunnel junctions (MTJs) and is processed by DW motion. Here, we demonstrate that all-electrical control of such nanoscale DW-based logic devices can be realized using a novel MTJ stack. In addition to field-driven motion, which is isotropic, we show the directional motion of DWs driven by current, a key requirement for logic operation. Full electrical control of an AND logic gate using DW motion is demonstrated. Our devices are fabricated in imec’s 300-mm CMOS fab on full wafers, which clears the path for large-scale integration. This proof of concept, thus, offers potential solutions for high-performance and low-power DW-based devices for logic and neuromorphic applications. [ABSTRACT FROM AUTHOR]

2D materials offer a pathway for further scaling of CMOS technology. However, for this to become a reality, both n-MOS and p-MOS should be realized, ideally with the same (standard) material. In the specific case of MoS2 field effect transistors (FETs), ambipolar transport is seldom reported, primarily due to the phenomenon of Fermi level pinning (FLP). In this study we identify the possible sources of FLP in MoS2 FETs and resolve them individually. A novel contact transfer technique is used to transfer contacts on top of MoS2 flake devices that results in a significant increase in the hole branch of the transfer characteristics as compared to conventionally fabricated contacts. We hypothesize that the pinning not only comes from the contact-MoS2 interface, but also from the MoS2-substrate interface. We confirm this by shifting to an hBN substrate which leads to a 10 fold increase in the hole current compared to the SiO2 substrate. Furthermore, we analyse MoS2 FETs of different channel thickness on three different substrates, SiO2, hBN and Al2O3, by correlating the p-branch ION/IOFF to the position of oxide defect band in these substrates. FLP from the oxide is reduced in the case of Al2O3 which enables us to observe ambipolar transport in a bilayer MoS2 FET. These results highlight that MoS2 is indeed an ambipolar material, and the absence of ambipolar transport in MoS2 FETs is strongly correlated to its dielectric environment and processing conditions. [ABSTRACT FROM AUTHOR]

Two-dimensional semiconducting materials are considered as ideal candidates for ultimate device scaling. However, a systematic study on the performance and variability impact of scaling the different device dimensions is still lacking. Here we investigate the scaling behavior across 1300 devices fabricated on large-area grown MoS2 material with channel length down to 30 nm, contact length down to 13 nm and capacitive effective oxide thickness (CET) down to 1.9 nm. These devices show best-in-class performance with transconductance of 185 μS/μm and a minimum subthreshold swing (SS) of 86 mV/dec. We find that scaling the top-contact length has no impact on the contact resistance and electrostatics of three monolayers MoS2 transistors, because edge injection is dominant. Further, we identify that SS degradation occurs at short channel length and can be mitigated by reducing the CET and lowering the Schottky barrier height. Finally, using a power performance area (PPA) analysis, we present a roadmap of material improvements to make 2D devices competitive with silicon gate-all-around devices. [ABSTRACT FROM AUTHOR]

Spin-on-diffussant (SoD) processing as a doping technique in two-dimensional semiconductors shows a general process compatibility with materials such as MoS2 and WSe2. The characteristic Raman modes in chemical vapor deposition-grown MoS2 are retained after a phosphorus-based SoD processing at temperatures up to 1000 °C; the evolution of the characteristic Raman peaks with SoD processing indicates a reduction in the intrinsic electron concentration. Electrical measurements show a corresponding p-type shift in the MoS2 MOSFET transfer characteristics and indicate possible oxidation of MoS2 by the SoD processing. Both these effects correlate with XPS measurements which confirm the diffusion of phosphorus atoms into MoS2 and increased atomic percentage of Mo oxide after SoD processing. The p-type shifts in the electrical characteristics correspond to a maximum of 2.4 × 1012 cm–2 change in the intrinsic carrier concentration. Repeating the experiment on WSe2 flake devices leads to similar trends: an increased p-type and a decreased n-type conduction indicating p-type doping and a significant increase in the OFF-state leakage current. [ABSTRACT FROM AUTHOR]

Abstract Internal photoemission of electrons from uncapped monolayer graphene to insulating SiO 2 has been observed in samples prepared by water-intercalation based graphene transfer. The barrier height between the graphene Fermi level and the oxide conduction band bottom was reproducibly found to be 4.1–4.2 eV. Moreover, this value was weakly sensitive to the contacting metal work function (Al, Cu, Au). This barrier height corresponds to an effective work function of graphene close to 5.0 eV, which is nearly 0.5 eV higher than the usually reported vacuum value. Highlights • Internal photoemission of electrons has been detected from uncapped monolayer graphene. • Effective work function (EWF) of graphene has been determined to be 5.0 eV. • EWF of graphene at the interface with SiO 2 is 0.5 eV higher than the vacuum value. [ABSTRACT FROM AUTHOR]

2-D material FETs hold the promise of excellent gate control, but the impact of nonidealities on their performance remains poorly understood. This is because of the need, so far, to use computationally intensive nonequilibrium Green’s function (NEGF) simulations. Here, we therefore use a semiclassical model to investigate the role of nonidealities in the scaling of back-gated (BG) and top-gated (TG) monolayer MoS2 FETs. We verify the electrostatics and transport of the semiclassical model with density functional theory-based NEGF simulations and calibrate nonidealities, such as interface traps (${D}_{\textsf {it}}$) and Schottky contact barrier height ($\phi _{\textsf {SB}}$) to experimental monolayer and bilayer MoS2 FETs. We find that among the nonidealities, ${D}_{\textsf {it}}$ has the strongest subthreshold swing impact with 70 mV/dec obtainable in BG devices for a ${D}_{\textsf {it}}$ of $5\times {10}^{11}$ cm−2eV $^{-1}$ , an equivalent oxide thickness (EOT) of 1 nm, and a channel length (${L}_{\textsf {ch}}$) of 5 nm. For scaled EOT, $\phi _{\textsf {SB}}$ only strongly impacts ${I}_{ \mathrm{\scriptscriptstyle ON}}$ for the TG case, as the overlapping gate thins the Schottky barriers in the BG case. We show in TG devices that a spacer of only 5 nm results in a 1000-fold drop in ${I}_{ \mathrm{\scriptscriptstyle ON}}$ because of the nonidealities. We propose positive spacer oxide charge as a solution and show that a charge density of above 1013 cm−2 is required to fully recover the device performance. [ABSTRACT FROM AUTHOR]

With the rapid progress of spintronic devices, spin-logic concepts hold promises of energy-delay conscious computation for efficient logic gate operations. We report on the electrical characterization of domain walls in interconnected magnetic tunnel junctions. By means of spin-transfer torque effect, domains walls are produced at the common free layer and its propagation towards the output pillar sensed by tunneling magneto-resistance. Domain pinning conditions are studied quasi-statically showing a strong dependence on pillar size, ferromagnetic free layer width and inter-pillar distance. Addressing pinning conditions are detrimental for cascading and fan-out of domain walls across nodes, enabling the realization of domain-wall-based logic technology. [ABSTRACT FROM AUTHOR]

Spin Torque Majority Gate (STMG) is a logic concept that inherits the non-volatility and the compact size of MRAM devices. In the original STMG design, the operating range was restricted to very small size and anisotropy, due to the exchange-driven character of domain expansion. Here, we propose an improved STMG concept where the domain wall is driven with current. Thus, input switching and domain wall propagation are decoupled, leading to higher energy efficiency and allowing greater technological optimization. To ensure majority operation, pinning sites are introduced. We observe through micromagnetic simulations that the new structure works for all input combinations, regardless of the initial state. Contrary to the original concept, the working condition is only given by threshold and depinning currents. Moreover, cascading is now possible over long distances and fan-out is demonstrated. Therefore, this improved STMG concept is ready to build complete Boolean circuits in absence of external magnetic fields. [ABSTRACT FROM AUTHOR]

The microwave dielectric properties of (Ba0.1Pb0.9)(Zr0.52Ti0.48)O3 (BPZT) and ZnO thin films with thicknesses below 2~\mu \textm were investigated. No significant dielectric relaxation was observed for both BPZT and ZnO up to 30 GHz. The intrinsic dielectric constant of BPZT was as high as 980 at 30 GHz. The absence of strong dielectric dispersion and loss peaks in the studied frequency range can be linked to the small grain diameters in these ultrathin films. [ABSTRACT FROM AUTHOR]

Directional antennas revolutionized modern day telecommunication by enabling precise beaming of radio and microwave signals with minimal loss of energy. Similarly, directional optical nanoantennas are expected to pave the way toward on-chip wireless communication and information processing. Currently, on-chip integration of such antennas is hampered by their multielement design or the requirement of complicated excitation schemes. Here, we experimentally demonstrate electrical driving of in-plane tunneling nanoantennas to achieve broadband unidirectional emission of light. Far-field interference, as a result of the spectral overlap between the dipolar emission of the tunnel junction and the fundamental quadrupole-like resonance of the nanoantenna, gives rise to a directional radiation pattern. By tuning this overlap using the applied voltage, we record directivities as high as 5 dB. In addition to electrical tunability, we also demonstrate passive tunability of the directivity using the antenna geometry. These fully configurable electrically driven nanoantennas provide a simple way to direct optical energy on-chip using an extremely small device footprint. [ABSTRACT FROM AUTHOR]

We study the excitation of spin waves in scaled magnetic waveguides using the magnetoelastic effect. In uniformly magnetized systems, normal strains parallel or perpendicular to the magnetization direction do not lead to spin wave excitation since the magnetoelastic torque is zero. Using micromagnetic simulations, we show that the nonuniformity of the magnetization in submicron waveguides due to the effect of the demagnetizing field leads to the excitation of spin waves for oscillating normal strains both parallel and perpendicular to the magnetization. The excitation by biaxial normal in-plane strain was found to be much more efficient than that by uniaxial normal out-of-plane strain. For narrow waveguides with a width of 200 nm, the excitation efficiency of biaxial normal in-plane strain was comparable to that of shear strain. [ABSTRACT FROM AUTHOR]

Several applications of two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) in nanoelectronic devices require the deposition of ultrathin pinhole free high-κ dielectric films on 2D TMDs. However, deposition of nm-thin high-κ dielectric films on 2D TMDs remains challenging due to the inert TMD surface. Here, we demonstrate that the surface of a synthetic polycrystalline 2D MoS2 film is functionalized with SiO2 to enable the atomic layer deposition (ALD) of thin and continuous Al2O3 and HfO2 layers. The origins of nucleation, the growth mode, and layer coalescence process have been investigated by complementary physical characterization techniques, which can determine the chemical bonds, absolute amount, and surface coverage of the deposited material. SiO2 is prepared by oxidizing physical vapor deposited Si in air. The surface hydrophilicity of MoS2 significantly increases after SiO2functionalization owing to the presence of surface hydroxyl groups. SiO2 layers with a Si content of only 1.5 x 1015 atoms/cm² enable the deposition of continuous 2 nm thin Al2O3 and HfO2 layers on MoS2 at 300 °C. This fast layer closure can be achieved despite the sub-nm thickness and discontinuity of the SiO2 nucleation layer. On the basis of the experimental results, we propose a nucleation mechanism that explains this fast layer closure. Nucleation of Al2O3 and HfO2 occurs on the SiO2 islands, and fast layer closure is achieved by the lateral growth starting from the many nm-spaced SiO2 islands. Finally, the dielectric properties of Al2O3 on the functionalized MoS2 are confirmed in a top-gated capacitor that shows a leakage current of 3.8 x 10-6 A/cm² at a 3.4 nm equivalent oxide thickness. To conclude, fast nucleation and layer closure in ALD can be achieved even for a sub-nm thin, discontinuous nucleation layer. We propose that this insight can also be applied to other ALD processes, materials, or applications where thin and fully continuous layers are required. [ABSTRACT FROM AUTHOR]

In the recent decade, there is a growing interest in Hf 0.5 Zr 0.5 O 2 (HZO) thin films owing to their well-behaved ferroelectricity and high compatibility with semiconductor integrated circuit technology. The ferroelectric properties of HZO are highly pertinent to the wake-up effect, which has been reported to be associated with the monoclinic (m-), orthorhombic (o-), and tetragonal (t-) phases. However, it is very challenging to distinguish the o- and t- phases by conventional X-ray diffraction. In this study, the HZO thin films with and without the need for the wake-up process to enhance the ferroelectricity were prepared, and the precession electron diffraction (PED) phase mapping technique was utilized to identify the crystalline phases in the HZO layers. The PED characterization reveals the correlation between the phase transformation and the wake-up effect in HZO. The absence of the t-phase is responsible for the wake-up-free property in the ferroelectric HZO thin film. The wake-up-free and pronounced ferroelectricity of the nanoscale HZO thin film in this study may bring a practical impact on a variety of ferroelectric applications. [Display omitted] [ABSTRACT FROM AUTHOR]

FETs made on 2-D semiconductors, typically without degenerate doping at the contacts, have a significant Schottky junction (SJ) resistance, which complicates transistor analysis. This paper evaluates the effect of the contact resistance on the 2-D-material FET characteristics through four-terminal (4-T) resistance measurements on WSe2 FETs, which allow studying the channel and contacts characteristics separately. Apart from showing the nonnegligibility of contact resistance, this paper enables a finer understanding of commonly observed phenomena, such as transistor performance improvement with dielectric-encapsulation is observed to have a stronger effect on the contact than the channel; the resistance of the forward-biased SJ is observed to be not negligible, but comparable to that of the reverse-biased junction; at biases commonly referred to as “low-bias,” the WSe2 FET resistance could be dominated by the contacts; and pinchoff can be observed at relatively lower current levels, being related to the channel-contact resistance ratio rather than their magnitudes. In the devices where true channel pinchoff can be verified, a correlation emerges between current saturating behavior and asymmetry in the output characteristics with respect to the drain–source bias polarity, a feature that may serve as a guide toward interpreting standard FET output characteristics in 2-D materials. [ABSTRACT FROM PUBLISHER]

Perpendicular magnetic anisotropy (PMA) is an essential condition for CoFe thin films used in magnetic random access memories. Until recently, interfacial PMA was mainly known to occur in materials stacks with MgO\CoFe(B) interfaces or using an adjacent crystalline heavy metal film. Here, PMA is reported in a CoFeB\Ta bilayer deposited on amorphous high-κ dielectric (relative permittivity κ=20) HfO2, grown by atomic layer deposition (ALD). PMA with interfacial anisotropy energy Ki up to 0.49 mJ/m2 appears after annealing the stacks between 200°C and 350°C, as shown with vibrating sample magnetometry. Transmission electron microscopy shows that the decrease of PMA starting from 350°C coincides with the onset of interdiffusion in the materials. High-κ dielectrics are potential enablers for giant voltage control of magnetic anisotropy (VCMA). The absence of VCMA in these experiments is ascribed to a 0.6 nm thick magnetic dead layer between HfO2 and CoFeB. The results show PMA can be easily obtained on ALD high-κ dielectrics. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) transition metal dichalcogenides are potential low dissipative semiconductor materials for nanoelectronic devices. Such applications require the deposition of these materials in their crystalline form and with controlled number of monolayers on large area substrates, preferably using deposition temperatures compatible with temperature sensitive structures. This paper presents a low temperature plasma-enhanced atomic layer deposition (PEALD) process for 2D WS2 based on a ternary reaction cycle consisting of consecutive WF6, H2 plasma, and H2S reactions. Strongly textured, nanocrystalline WS2 is grown at 300 °C. The composition and crystallinity of these layers depends on the PEALD process conditions, as understood by a model for the redox chemistry of this process. The H2 plasma is essential for the deposition of WS2 as it enables the reduction of -W6+Fx surface species. Nevertheless, the impact of subsurface reduction reactions needs to be minimized to obtain WS2 with well-controlled composition (S/W ratio of 2). [ABSTRACT FROM AUTHOR]

Graphene is considered as potential candidate for future nano-interconnects. In this respect we study the Brønsted acid doping effect of single layer graphene (SLG) and few layer graphene (FLG) synthesized by chemical vapor deposition (CVD). A sheet resistance reduction of 50% is achieved by HNO 3 doping of SLG, and the resulting resistivity of 9.1 μΩ·cm is comparable to alternative metals to copper (e.g. Ru). On the other hand, synthetic FLG shows higher sheet resistance due to higher defect density. Mobility degradation at increased carrier concentration is a main limiting factor for sheet resistance reduction of CVD graphene. [ABSTRACT FROM AUTHOR]

In this work we are electrically characterizing multilayer graphene ribbons as potential Cu replacement towards future interconnect applications. We are comparing their performance with single-layer ribbons and we are reporting on sheet resistance, mobility and mean free path. We are additionally characterizing the contact properties for Pd contacts in top and edge configuration. Our results show high current carrying capacity for the multilayer ribbons and lower sheet resistance. Edge contacts to multilayer ribbons seem a promising approach for the decrease of the contact resistivity. Values of sheet resistance Rs ~ 280 Ω and contact resistivity Rc*W ~ 325 Ω·μm are measured for multilayer samples and edge contacts. Although the calculated ribbon mean free path is high for single-layer graphene (MFP SLG ~ 60 nm), it is comparable with the MFP of Cu for the multilayer samples (MFP FLG ~ 30 nm). Intercalation is a potential approach for improvement of the multilayer wire properties. [ABSTRACT FROM AUTHOR]

We report on the electrical characterization of synthetic, large-area MoS2 layers obtained by the sulfurization technique. The effects of dielectric encapsulation and localized defect states on the intrinsic transport properties are explored with the aid of temperature-dependent measurements. We study the effect of dielectric environment by transferring as-grown MoS2 films into different dielectrics such as SiO2, Al2O3, HfO2, and ZrO2 with increasing dielectric permittivity. Electrical data are collected on a statistically-relevant device ensemble and allow to assess device performances on a large scale assembly. Our devices show relative in-sensitiveness of mobility with respect to dielectric encapsulation. We conclude that the device behavior is strongly affected by several scattering mechanisms of different origin that can completely mask any effect related to dielectric mismatch. At low temperatures, conductivity of the devices is thermally activated, a clear footprint of the existence of a mobility edge separating extended states in the conduction band from impurity states in the band-gap. [ABSTRACT FROM AUTHOR]

In this work, we evaluate the material properties of graphene and assess the potential application of graphene to replace copper wires in Back-End-Of-Line (BEOL) interconnects. Based on circuit and system-level simulations, high restrictions are imposed to graphene with respect to contact resistance and mean free path. Experimentally we evaluate single and multi-layer graphene wires and we measure carrier mean free paths (MFPs) above ~ 110 nm. However, contact engineering will be the key issue for integration of graphene as interconnect. [ABSTRACT FROM AUTHOR]

The impact of the scaling of the channel length on the performances of metal-oxide-semiconductor field effect transistors, based on two-dimensional (2D) channel materials, is theoretically investigated, using density functional theory combined with the non-equilibrium Green's function method. It is found that the scaling of the channel length below 10nm leads to strong device performance degradations. Our simulations reveal that this degradation is essentially due to the tunneling current flowing between the source and the drain in these aggressively scaled devices. It is shown that this electron tunneling process is modulated by the effective mass of the 2D channel material, and sets the limit of the scaling in future transistor designs. [ABSTRACT FROM AUTHOR]

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET. [ABSTRACT FROM PUBLISHER]

Nanoscale morphology of vanadium dioxide (VO2) films can be controlled to realize smooth ultrathin (<10 nm) crystalline films or nanoparticles with atomic layer deposition, opening doors to practical VO2 metal-insulator transition (MIT) nanoelectronics. The precursor combination, the valence of V, and the density for as-deposited VO2 films, as well as the postdeposition crystallization annealing conditions determine whether a continuous thin film or nanoparticle morphology is obtained. It is demonstrated that the films and particles possess both a structural and an electronic transition. The resistivity of ultrathin films changes by more than two orders of magnitude across the MIT, demonstrating their high quality. [ABSTRACT FROM AUTHOR]

Crystalline vanadium dioxide (VO2) thin films were prepared by annealing amorphous VO2 films which were deposited by atomic layer deposition on a SiO2 substrate. A large influence of the oxygen partial pressure in the annealing ambient was observed by means of in-situ X-ray diffraction. In the range between 1 and 10Pa of oxygen the interesting VO2(R) phase crystallized near 450°C. Between 2 and 10Pa of oxygen, metastable VO2(B) was observed as an intermediate crystalline phase before it transformed to VO2(R). Anneals in inert gas did not show any crystallization, while oxygen partial pressures above 10Pa resulted in oxidation into the higher oxide phase V6O13. Film thickness did not have much effect on the crystallization behavior, but thinner films suffered more from agglomeration during the high-temperature crystallization on the SiO2 substrate. Nevertheless, continuous polycrystalline VO2(R) films were obtained with thicknesses down to 11nm. In the case where VO2(R) was formed, the semiconductor–metal transition was observed by three complementary techniques. This transition near 68°C was characterized by X-ray diffraction, showing the transformation of the crystal structure, by spectroscopic ellipsometry, mapping optical changes, and by sheet resistance measurements, showing resistance changes larger than 2 orders of magnitude between the low-temperature semiconducting state and the high-temperature metallic state. [ABSTRACT FROM AUTHOR]

Abstract: We report the large area growth of highly conductive carbon nanosheets (CNS) composed of few layer graphene on 200mm diameter Si substrates using conventional radio frequency plasma-enhanced chemical vapour deposition. Raman spectroscopy is used to characterise the evolution of the CNS nucleation and growth with time in conjunction with TEM revealing the nano-sized graphene-like nature of these films and the intimate contact to the substrate. An individual sheet can have edges as thin as 3 graphene layers. The influence of the growth support layer is also discussed as film growth is compared on titanium nitride (TiN) and directly on Si. Electrochemical cyclic voltammogram (CV) measurements reveal these layers to form an excellent electrical contact to the underlying substrate with excellent stability towards oxidation whilst having a large electrochemical surface area. The resistance of a 150nm film was measured to be as low as 20μohmcm. The high percentage of narrow few layer graphene edge sites exposed allows for faster electrochemical reaction rates compared to carbon nanotubes (CNTs) and other electrode materials (glassy carbon and Pt). [Copyright &y& Elsevier]

• Dual gated WS 2 MOSCAP devices were fabricated to measure both n/p-branch C-V response. • Frequency/temperature dependent CV curves were correlated with WS 2 MOSCAP simulation. • Interface trap density across the bandgap (D IT (E)) is extracted for 2ML WS 2. Dual gated 2ML WS 2 MOS Capacitors have been fabricated with capacitance values as high as 2.7uF/cm2 (with single sheet charge centroid assumption for the WS 2 channel). Frequency and temperature dependent C-V measurements were correlated with simulations to extract the interface trap density-energy (D IT (E)) profile. We observe an exponentially decaying defect distribution from the conduction band (E C) edge with a magnitude of 8 × 1013 cm−2 eV−1 and an inverse slope of 0.12 eV and a similar distribution with a peak magnitude of 1.2 × 1014 cm−2 eV−1 from the valence band (E V) edge with an inverse slope of 0.12 eV. [ABSTRACT FROM AUTHOR]

2D transition metal dichalcogenide based van der Waals materials are promising candidates to realize tunnel field effect transistors (TFETs) with a steep subthreshold swing (SS) for low‐power applications. Their atomically flat, self‐passivated layers offer potentially defect free interlayer tunneling. There are still several issues that need to be addressed to experimentally achieve a steep SS, e.g., the Schottky contacts, impact of thick layers, and device architecture with respect to gate configuration. This paper resolves these challenges by experimentally demonstrating MoS2/MoTe2 TFETs and their electrical characteristics, in conjunction with ab initio simulations and surface Kelvin probe microscopy. The Schottky barrier's effect at the contact regions are isolated by fabricating individual buried gates below the contacts. Devices with different top and bottom gate configurations are produced to understand the impact of gate placement on the heterostructure characteristics. Quantum transport simulations are performed on MoS2/MoTe2 multilayer stack to evaluate the impact of multiple layers on TFET performance, effect of gate placement, and the mechanism behind indirect tunneling over the heterojunction region. This work highlights the influence of the Schottky contacts, multiple layers and the role of different gate configurations on the band‐to‐band tunneling phenomenon in 2D heterojunction TFETs. [ABSTRACT FROM AUTHOR]