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As new applications impose jitter values in the range of a few tens of femtoseconds, the design of phase-locked loops faces daunting challenges. This paper derives basic relations between the tolerable jitter and the power consumption, predicting severe issues as jitters below 10 fs are sought. The results are also applied to the sampling clocks in analog-to-digital converters and suggest that clock generation may consume a greater power than the converter itself. [ABSTRACT FROM AUTHOR]

This paper presents a low power injection-locked oscillator (ILO)-type clock and data recovery (CDR) in 40 nm CMOS. An efficient “phase reset” scheme is proposed to periodically realign the clock phase to the rising edge of data. The frequency information is extracted by comparing the rising edge of the data and the clock after aligning the phase using a bang-bang phase detector (BBPD). Additionally, a low power injection-locked two-stage ring digitally controlled oscillator (ILDCO) is employed to provide four-phase quadrature clock and significantly reduce the power consumption. Based on the proposed architecture, the fabricated CDR consumes only 5.8 mW from a 0.9 V supply, while being able to extract the clock signal from 6.15 to 10.9 Gb/s input data with a measured jitter tolerance (JTOL) of 0.15 UIpp at the highest frequency, indicating that the CDR meets the OC-192 mask. Furthermore, the proposed CDR demonstrates a substantial improvement in the power efficiency of 0.58 pJ/bit. [ABSTRACT FROM AUTHOR]

The increase of clock frequency in digital circuits exacerbates the electromagnetic interference (EMI) between devices. Spread-spectrum techniques reduce the electromagnetic noise lowering harmonic peaks of the clock signal by means of frequency modulation. In System-on-Chips (SoCs) another requirement in many applications is the coexistence of both modulated and un-modulated clock domains. In these cases, suitable synchronization systems are used to allow data to cross the boundary between spread and un-spread clock domains. In this paper we present a spread-spectrum clock generator (SSCG) able to provide both spreaded and un-spreaded clocks. The spreaded clock has a specially designed modulation profile, allowing at the same time a seamless synchronization-free interface between spreaded and un-spreaded clock domains and a large EMI reduction. The paper presents the derivation of the new highly discontinuous modulation profile (that allows to achieve an EMI reduction up to 15.8dB) and implementation details of an all-digital SSCG able to provide the developed modulation waveform. A test chip has been fabricated in UMC 65nm CMOS technology, using a novel dual-output digitally controlled delay line. The circuit can generate both spread and un-spread clocks (double output mode) or the spread clock alone (single output mode). Area occupation is 0.102mm2, whereas power consumption is 48.5mW in double output mode and 34mW in single output mode. [ABSTRACT FROM AUTHOR]

Mismatches among frequency control elements in digitally-controlled oscillators can be a significant source of phase error in digital phase-locked loops (PLLs). This paper presents a multi-rate dynamic element matching technique and an adaptive mismatch-noise cancellation (MNC) technique that work together to address this problem. The two techniques operate in background during normal PLL operation, and the MNC technique has typical cold start convergence times of a few seconds. [ABSTRACT FROM AUTHOR]

This paper presents a linear current-reuse sampling phase detector for a single-loop type-I phase-locked loop (PLL) to simultaneously achieve a wide loop bandwidth and low control voltage ripple, resulting in low RMS jitter and reference spur, while minimizing the chip area by avoiding an explicit loop filter. Fabricated in 28-nm CMOS, the PLL prototype measures an integrated jitter of 440 fsRMS, and a spur level of −63.9 dBc at 3.296 GHz. It draws 3.3 mW at a 0.9-V supply and scores a jitter-power figure-of-merit (FoM) of −241.9 dB. With a 103-MHz reference input, a bandwidth of ~20 MHz aids suppressing significantly the ring VCO’s phase noise (PN), leading to an in-band PN of −116 dBc/Hz at 1-MHz offset. The die size is 0.003 mm2. [ABSTRACT FROM AUTHOR]

This paper proposes a sub-harmonically injection-locked all-digital PLL (SIL-ADPLL). The SIL-ADPLL includes five main circuit blocks: injection-locked digitally controlled oscillator with single-ended injection technique (SILDCO), injection-locked frequency divider (ILFD), timing-adjusted phase detector (TPD), multiplexed time-to-digital converter (MTDC), and the pulse generator (PG). The single-ended injection technique relaxes the pulse width constraint of the injection pulse and thus reduces the design complexity of PG. The proposed ILFD aided injection timing alignment technique can align the injection timing adaptively at output frequency higher than 20 GHz. The ILFD block is inserted between the SILDCO and the TPD without much penalty of power consumption. The proposed MTDC can quantize the output of TPD with only one TDC core to further save power consumption. The proposed PG can relax the trade-off between the phase noise suppression and the power consumption. Implemented in 65 nm CMOS process with a core area of 0.462 mm2, the SIL-ADPLL achieves 18- to 23-GHz frequency range, 57.4-fs rms jitter at 20 GHz, 13.7-mW power consumption, and −253.5-dB FoM. The measurement results also show robustness over environment variation. [ABSTRACT FROM AUTHOR]

This paper presents a PLL supporting diverse low-power clocking needs including wide input (6–200 MHz) and output (0.15–5 GHz) frequency ranges and SSC operation. Fabricated in 14nm FinFET CMOS, a low-power switched-cap loop filter is employed to enable high −3dB PLL bandwidth (>40% of $f_{\mathrm{ REF}}=19.2$ MHz), and the proposed reference current generator (IrefGen) provides accurate current with <4% tolerance without the need for external components or on-chip precision resistors. IrefGen decouples PLL loop dynamics from feedback divide ratio and provides immunity to systematic capacitor variation. Power gating of switched-cap loop filter’s bias circuits results in more than 10% PLL total power savings. The PLL achieves 1.6-ps integrated RMS jitter at 4 GHz using 100-MHz reference while consuming 2.6 mW from 0.95 V. The PLL performance satisfies the stringent PCIe Gen2/3 jitter specifications without resorting to inductors. [ABSTRACT FROM AUTHOR]

This paper describes a bias-current-free fractional-N hybrid phase-locked loop (HPLL) architecture that does not use a charge pump (CP) or a linear time-to-digital converter (TDC). A hybrid loop control with a digital integral path and an analog proportional-gain path offers technology scalability as well as linear phase detection under a low supply voltage. The CP-less analog control path consists of a flip-flop phase detector (PD) and passive loop filters including a programmable notch filter. Unlike the TDC, the flip-flop PD has negligible contribution to the in-band phase noise over different supply voltages. To mitigate ΔΣ quantization noise and PD nonlinearity effects, an FIR-filtered ΔΣ modulation is employed for fractional division. The proposed fractional-N HPLL implemented in 65-nm CMOS operates with a 0.65-V supply except a 0.9-V digital/voltage-controlled oscillator (D/VCO), consuming 1.85 mW at 1.2 GHz. The phase noise of –97 dBc/Hz at 1-MHz offset frequency and the reference spur of –76 dBc with the programmable notch filter are achieved. The measured in-band fractional spur levels vary from –37 dBc to –58 dBc. The experimental results show that the proposed architecture is promising for low-voltage clock generation and modulation systems. [ABSTRACT FROM AUTHOR]

This paper presents a quarter-rate forwarded clock (FC) receiver based on an injection-locked oscillator (ILO) which exploits a phenomenon in which phases of the output clock are shifted by the duty-cycle of an injection clock. Also, this paper describes the principle of this phase shifting phenomenon. To utilize the phase shifting phenomenon, a simple duty-cycle adjuster (DCA) is proposed. By using the DCA, the proposed FC receiver achieves 760 MHz of wide jitter tracking bandwidth (JTB) and 60 MHz JTB variation in spite of clock deskew. The proposed receiver achieves a 12 Gb/s data rate with 0.92 mW/Gb/s in a 1 V 65 nm CMOS process. [ABSTRACT FROM AUTHOR]

A 2.5–5.6 GHz low-phase-noise subharmonically injection-locked sub-sampling all-digital phase-locked loop with a dual-edge complementary switched injection technique is presented. While previously reported injection-locked phase-locked loops (ILPLLs) require additional circuitry for resolving a phase alignment mismatch between the PLL loop and injection path, the presented ILPLL exhibits a simplified architecture owing to the proposed injection technique and sub-sampling bang-bang phase detector (SSBBPD). Because the proposed injection technique exploits dual-edge injection, we analyze the performance impact of dual-edge injection when inaccurate injection timing occurs. This paper also offers an analysis of the injection technique based on the charge transfer and derives the realignment factor of the injection. With the proposed injection technique and the direct connection of the digitally controlled oscillator (DCO) clock to the SSBBPD, the timing mismatch between the PLL loop and injection path becomes insensitive to voltage and temperature drift. The proposed ILPLL prototype is fabricated in a 65-nm CMOS process and achieves a 168-fs integrated rms jitter over 1 kHz to 40 MHz at a 5-GHz output frequency with 156.25-MHz reference clock while consuming 15.4 mW with an active area of 0.06 mm2. [ABSTRACT FROM AUTHOR]

In this paper, we study networks of coupled oscillators applied to the distributed synthesis of clock signals for large systems-on-chip. The oscillators are implemented as interconnected all-digital phase-locked loops (ADPLLs), which are asynchronous control systems. We address the issue of modelling, synchronization and stability of both a single ADPLL and interconnected ADPLLs. We prove that the stability domain is universal for large Cartesian networks, and it related to the domain for a single ADPLL. We show that within the stability domain the network synchronises to the reference signal both in frequency and phase. A hardware verification of Cartesian networks is presented, and it is consistent with our theoretical findings. The proposed design may be useful for multiples engineering and physics applications, including clock generation, distributed computations, beamforming, and other applications, where the control over time synchronicity is crucially important for the system performance. [ABSTRACT FROM AUTHOR]

This paper presents a calibration-free and low-jitter phase-locked loop (PLL) with small performance degradation over PVT. We introduce an open-loop discrete-time phase noise cancellation (OPDTPNC) technique to achieve a wideband filtering and circuit inner-gain-tracking for PVT stabilization. The OPDTPNC is an effective phase realignment that enables a filtering bandwidth ~1/4 of the reference clock frequency. Besides, with the common structures and PVT tracking bias for sampler and corrector of the OPDTPNC, the prototype PLL maintains its low jitter under a wide range of PVT variations. Eventually, by cascading a Type-II PLL with the OPDTPNC, the proposed hybrid PLL attains the benefits of both Type-II PLL and injection-locked clock multiplier (ILCM). Fabricated in 28-nm CMOS with an active area of 0.023mm2 it consumes 4.1 mV from a 1 V supply with a reference spur of -63 dBc. The measured rms jitter of the 2.4 GHz PLL is 248 fs and 686 fs with and without OPDTPNC, respectively. When the temperature, supply and loop gain vary from 0 to 100°C, ±5%, and 6dB, respectively, the jitter performance only degrades less than 9%. [ABSTRACT FROM AUTHOR]

In this paper, a hybrid architecture of digital pulse width modulator (DPWM) with high resolution is proposed. Furthermore, to enhance linearity performance, the critical path is optimized by a novel synchronous phase-shifted circuit. A carry chain-based delay line is also utilized to improve time resolution. A 14-bit DPWM with the proposed architecture is implemented and tested by Altera Cyclone IV FPGA. The experiment results show that the DPWM achieves high linearity, where $R^{2}$ maintains over 0.9994. Besides, the output duty cycle covers a wide range from 0.9429% to 99.2% and the time resolution is about 41.3ps. [ABSTRACT FROM AUTHOR]

This paper presents an ultralow power asynchronous logic transmitter operating at 1 Gpps that achieves pulse synthesis using a double phase-locked loop (PLL) architecture for applications exploiting large-scale neuronal interfacing with CMOS probes. The 4 GHz center frequency OOK transmitter synthesizes 500 ps duration pulses from a 31.25 MHz crystal oscillator using a cascade of a master and a slave PLL with the latter locked to the former. Both PLLs are implemented with CMOS digital cells and ring oscillator-based VCO. A prototype fabricated in a 130 nm RFCMOS process operates at a measured 5 pJ/pulse energy budget for an active area of 0.04 mm2. To generate timing references and packets for high data rate recording devices, the synthesizer core feeds also a logic interface operating at 250 MHz with four 1.2–3.3 V external parallel channels. From reset time, the master–slave PLL combination achieves locking in a measured time of 450 ns, settling is resolved in \sim 4~\mu \texts , and the output pulses across the antenna load are generated with a 3.42 ps RMS jitter standard deviation. The obtained phase noise of a continuous OOK stream at 1 and 4 GHz, 1 MHz offset, is −103 and −93 dBc/Hz, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a loop gain optimization technique for integer-N digital phase-locked loops with a time-to-digital converter. Due to noise filtering properties, a phase-locked loop has an optimal loop gain which gives rise to the best jitter performance, taking into account external and internal noise sources. By using the loop gain optimization technique, the digital phase-locked loops can automatically attain this loop gain in background to minimize the jitter. Theoretical analysis is presented. The stability issue and the impact of loop latency are also discussed. Finally, the analysis is compared to behavioral simulations with good agreement. [ABSTRACT FROM AUTHOR]

In this paper, we propose and analyze a pulse-output digital-to-frequency converter (DFC) generating square waves, which uses a digital-to-time converter (DTC) to correct the spurious tones (spurs) in the output spectrum. We focus on high-level architectural potential, discuss the design features of a DTC suitable for the proposed system, and explore possibilities and limits of this approach in terms of cleanness of the output spectrum. The behavioral model simulations confirm the theoretical analysis presented. Besides an analytical description of the output spurs, we derive a closed-form estimate of the worst-case spur, which leads to a simple design equation. This is useful to determine the DTC requirements [number of bits and integral non-linearity (INL)], given a certain spurious-free dynamic range (SFDR) target. We show that the maximum spur strength (in dBc) depends exclusively on the ratio between the output frequency and the clock frequency and the DTC features (number of bits, INL, and other impairments) and increases with the ratio by 6 dB/octave. [ABSTRACT FROM AUTHOR]

This paper describes a low-power reference-less 5.4-Gb/s clock and data recovery (CDR) circuit with a fully digital quarter-rate linear phase detector (QLPD) having an extended pulse width output. By using a fully digital circuit and merging XOR function with charge pump, the power efficiency and linearity of the phase detector are improved. The proposed QLPD responds correctly up to 0.75 UI of phase difference at 5.4 Gb/s. The CDR was designed to conform to Embedded DisplayPort (eDP) standard of the Video Electronics Standards Association (VESA). The proposed CDR circuit has been fabricated using a 40-nm CMOS technology. The jitter tolerance (JTOL) margin was measured at 0.75 UI, which is 20% higher than the eDP specification of 0.624 UI at the 20-MHz jitter frequency. BER was measured as less than 10−12 with a 27−1 pseudo random bit sequence (PRBS) pattern. The CDR consumes 12.99 mW, including a bandgap reference circuit and power efficiency achieving 2.41 pJ/bit at 5.4 Gb/s. The area of the proposed CDR is 0.13 mm2. [ABSTRACT FROM AUTHOR]

This paper presents the Band-Reject Nested-PLL (BRN-PLL) scheme that simultaneously improves filtering of a noisy input signal and relaxes the requirements for the loop bandwidth. As the architecture employs a modified PLL as a divider of another PLL, a stability analysis is presented to demonstrate suitable operation. The BRN-PLL close-to-carrier output noise is dominated by the PFD/CP of the inner PLL and the far-from-carrier output noise is dominated by the LO of the outer PLL. The PFD/CP noise can be reduced by approximately 20 dB when the output is disconnected from the VCO during idle states, and a low noise floor is achieved using a passively biased double-switching pair LC VCO. Additionally, to maintain lower integrated phase noise, the proposed scheme uses a high-Q MEMS-based VCO to effectively smoothen the transition of the response between the two dominant noise sources. Absolute figures equal to -105 dBc/Hz at 1 kHz and -155 dBc/Hz at 10 MHz are measured from a 104 MHz clock-cleaner. [ABSTRACT FROM PUBLISHER]

This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71-mm^2. With input 10-Gb/s data of a 2^31-1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 \mus. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage. [ABSTRACT FROM PUBLISHER]

We present a linearized analysis of bang-bang phase-locked loops (PLLs) in the frequency domain that is complete and self-consistent. It enables the manual design of frequency synthesis PLLs for loop bandwidth, output phase noise and minimum jitter. Tradeoffs between various parameters of the loop become clear. The analysis is validated against measurements on four very different loops, and helps to answer long-standing questions on aspects of these circuits attributable a hard nonlinearity. A brief designer’s guide is included. [ABSTRACT FROM AUTHOR]

This paper discusses novel architectures and circuit techniques for DPLLs. These include: methods to have a wide temperature range in the digitally controlled oscillator (DCO) for ring-oscillator based DPLLs, re-circulating time to digital converter (TDC) architecture to support a large input phase error range, efficient, modular, divider architectures that provide 50% output duty cycle, while allowing dynamic programmability of the division ratio, and fractional DPLL approaches for spur cancellation and low power operation. The techniques described in the paper have been used to build DPLLs for serializer-deserializer (SerDes), processor clock generation, and wireless connectivity applications in 65 nm and 45 nm CMOS. These implementations are briefly discussed and representative silicon results are presented. [ABSTRACT FROM AUTHOR]

This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm^2 in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 psrms and the data eye opening is 0.613UI. [ABSTRACT FROM AUTHOR]

This paper analyses the stability of the synchronized state in Cartesian networks of identical all-digital phase-locked loops (ADPLLs) for clock distribution applications. Such networks consist in Cartesian grids of digitally-controlled oscillator nodes, where each node communicates only with its nearest neighbors. Under certain conditions, we show that the whole network may synchronize both in phase and frequency. A key aspect of this study lies in the fact that, in the absence of an absolute reference clock, the loop-filter in each ADPLL is operated on the irregular rising edges of the local oscillator and consequently, does not use the same operands depending on whether the local clock is leading or lagging. Under simple assumptions, these networks of so-called "self-sampled" all-digital phase-locked-loops (SS-ADPLLs) can be described as piecewise-linear systems, the stability of which is notoriously difficult to establish. The main contribution of this paper is a simple design rule that must be met by the coefficients of each loop-filter in order to achieve synchronization in a Cartesian network of arbitrary size. Transient simulations indicate that this necessary synchronization condition may also be sufficient for a specific (but important) class of SS-ADPLLs. A synthesis of the different approaches that have been conducted in the study of the synchronization of SS-ADPLLs is also done. [ABSTRACT FROM PUBLISHER]

The past several years have successfully brought all-digital techniques to the RF frequency synthesis, which could arguably be considered one of the last strong bastions of the traditionally-analog design approaches. With their high sensitivity and high dynamic range requirements, the RF circuits have long had a good excuse to avoid any possible source of digital switching activity. With the constant scaling of CMOS feature size and the merciless push for integration, the existence of almost free and powerful digital logic could not go unnoticed. Hence, the environment was ripe to transform the RF functions into digital realizations, as well as to apply digital assistance to help with the performance of RF circuits. This paper revisits the digitization journey of the traditional charge-pump PLL that has resulted in an all-digital frequency synthesizer with the best-in-class RF performance while occupying only a fraction of the silicon area and consuming a fraction of the power. The paper also offers a few novel techniques to further improve area, current consumption, testability, and reliability of frequency synthesizers. [ABSTRACT FROM PUBLISHER]

A phase-locked loop (PLL) using a single-ring-oscillator-based integrator with background frequency calibration is presented. By introducing the single-ring-oscillator-based integrator, the in-band phase noise and the power efficiency of the PLL are improved. With background frequency calibration, it allows this PLL to tolerate process, supply voltage, and temperature variations. Moreover, the reference spur will be improved by using timing orthogonal scheme. This PLL is fabricated in 40-nm CMOS process which occupies an active area of 0.0011mm2. Its power consumption is 1.22mW from a 1V supply voltage. The measured phase noise is −100dBc/Hz, −108dBc/Hz and -110dBc/Hz at the offset frequencies of 100kHz, 1MHz, and 10MHz, respectively. The integrated root-mean-square jitter is 1.5psrms, and this PLL achieves a figure-of-merit of −235.6dB. [ABSTRACT FROM AUTHOR]

A burst mode clock and data recovery (BMCDR) circuit for 10 Gbps passive optical network (10G-PON) is presented. The proposed BMCDR is reconfigurable between data gating mode and phase tracking mode to achieve instantaneously phase-locked with jitter suppression capability. Incorporating selectively gating VCO (SGVCO), the BMCDR operates at 1/5-rate and accomplishes 1:5 demultiplexing with a high energy efficiency of 1.24 pJ/bit. With a 4 MHz, 0.22UIpp jitter stressed input data at 10 Gbps, the recovered clock jitter at 2 GHz is 2.94 psrms. The prototype is fabricated using 55 nm CMOS technology. The core area is 0.03 mm^2 only. It dissipates 12.4 mW from 1 V supply. [ABSTRACT FROM AUTHOR]

This paper discusses a supply noise sensitivity problem of the gated ring oscillator (GRO) based time-to-digital converter (TDC) in all-digital phase-locked loops (ADPLLs) and presents a power supply rejection ratio (PSRR) enhancing method. A replica supply noise monitoring circuit is designed to track supply noise and enable feed-forward error cancellation for high PSRR TDC design. A prototype ADPLL with the proposed self-monitored TDC is implemented in 65 nm CMOS to evaluate the supply noise sensitivity of the TDC in the frequency domain. Intermodulation spur generation problem due to noise coupling is also addressed and demonstrated in hardware. The experimental results show that the proposed method effectively suppresses supply noise induced spurs at the output of the ADPLL, achieving the PSRR of 27 dB and 38 dB with 1 MHz supply noise and 5 MHz intermodulation noise respectively. [ABSTRACT FROM AUTHOR]

A multiplying delay-locked loop (MDLL)-based clock multiplier with a two-step phase aligning architecture and a dual-pulse charge-pump (CP) is proposed to reduce the reference spur level. The architecture has a phase-locked loop mode to align the coarse phase and an MDLL mode to obtain a delay-lock. With non-overlap dual phase detector pulses in the MDLL mode, the CP is directly calibrated in the runtime to minimize its phase offset. A discrete-time noise transfer function (NTF) is also derived to estimate the phase noise of multiplying-delay line from that of delay line. The NTF includes aliasing effect and shows better accuracy than the prior voltage controlled oscillator realignment-based approaches. This clock multiplier occupies an active area of 0.047-mm2 in 40-nm CMOS process. The clock multiplication ratio ( $N$ ) is an integer value from 8 to 27. With a low-cost 19.2-MHz TCXO reference, 153.6–518.4 MHz clocks were successfully generated, and a phase noise of −124 dBc/Hz at 100-kHz offset from a 518.4-MHz clock, rms jitter of 1.28 ps, and −65.5 dBc reference spur were measured. The power dissipation at 518.4 MHz was 2.6 mW from the 1.8 and 1.1 V supplies. [ABSTRACT FROM PUBLISHER]

In this paper, we show the relationship between the pull-in range of a linear phase-locked loop (PLL) and the current mismatch of the charge pump that controls the frequency of the oscillator in the PLL. We evaluate the pull-in range of the PLL based on a nonlinear behavioral model of the pull-in process with three types of phase detectors. We introduce the mismatch error to the charge pump current in the PLL and study the impact of this error on the pull-in range. We also apply the mismatch error to a nonlinear differential equation that describes the loop dynamics of the PLL and calculate the pull-in range under this mismatch condition. We validate the limitations of the pull-in range due to the current mismatch by a numerical simulation with MATLAB. [ABSTRACT FROM PUBLISHER]

Flying-Adder direct period synthesis is an emerging frequency synthesis technique. It is a mixed-signal technology that directly constructs the output clock period based on a multi-inputs reference. Owing to its open loop style and the usage of Time-Average-Frequency, this technique bears two important features: fine frequency resolution and instantaneous response. Although it has been used in commercial products for over a decade, the important issue associated with design/layout mismatch among its multi-inputs has not been studied in depth. In this paper, through a 55 nm Flying-Adder implementation, the cause of the mismatch is investigated. A mismatch model is created. Based on the model, the mismatch's impact is studied both in time and frequency domain. The experimental data from the chip is used to verify the observations from the analysis. Some useful insights are summarized in the end which will be useful in guiding future designs for commercial products. This study could also be helpful in developing a general theory for this problem. [ABSTRACT FROM PUBLISHER]

This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves -97∼dBc in-band phase noise, - 38∼dBc/Hz integrated noise, and 740 ns settling time. [ABSTRACT FROM AUTHOR]

Generation of low jitter, high frequency clock from a low frequency reference clock using classical analog phase-locked loops (PLLs) requires large loop filter capacitor and power hungry oscillator. Digital PLLs can help reduce area but their jitter performance is severely degraded by quantization error. Specifically, their deterministic jitter (DJ), which is proportional to the loop update rate becomes prohibitively large at low reference clock frequencies. We propose a scrambling TDC (STDC) to improve DJ performance and a cascaded architecture with digital multiplying delay locked loop as the first stage and hybrid analog/digital PLL as the second stage to achieve low random jitter in a power efficient manner. Fabricated in a 90 nm CMOS process, the prototype frequency synthesizer consumes 4.76 mW power from a 1.0 V supply and generates 160 MHz and 2.56 GHz output clocks from a 1.25 MHz crystal reference frequency. The long-term absolute jitter of the 160 MHz digital MDLL and 2.56 GHz digital PLL outputs are 2.4 $\rm{{ps}_{rms}}$ and 4.18 $\rm{{ps}_{rms}}$ , while the peak-to-peak jitter are 22.1 ps and 35.2 ps, respectively. The proposed frequency synthesizer occupies an active die area of 0.16mm2 and achieves power efficiency of 1.86 mW/GHz. [ABSTRACT FROM PUBLISHER]

Sine-shaped feedback DAC was proposed to be used in continuous-time \Sigma\Delta ADCs for its immunity to clock jitter. However, in a sine-shaped DAC, the carrier is used as an analog signal to mix with the data, consequently, all the carrier noise appears in the sine-shaped data. The effect of carrier noise was studied before, but the analysis was based on the assumption of white noise, which is not true in real PLLs. In this work, we present a simple, intuitive, and accurate model that can predict the effect of the clock noise on the sine-shaped DAC. The model is generic and can be applied for any noise profile. We tried to keep it as close as possible to the noise profile of a real clock source. The analysis is verified by simulation and measurement results. [ABSTRACT FROM AUTHOR]

This article describes the cross-correlation function as an alternative method to adapt loop gain in digital CDRs. Cross-correlation function inherent properties and their link with the cross-power spectral density help consolidating the adaptive loop gain technique, XCALG, for clock and data recovery systems that implement bang-bang phase detector. Considering the modulation of the loop gain due to jitter noise, previous works exploit the autocorrelation function at the output of the bang-bang phase detector as a proper indicator to track the system dynamics and perform loop gain adaptation. In contrast, we propose the XCALG as a new alternative to perform loop gain adaptation featuring better observability, less impact from jitter sources while keeping a safe phase margin. Theory behind the idea is enhanced, and the XCALG is demonstrated through behavioral system simulations. In addition, preliminary implementation costs of the cross-correlation function are discussed using a 65nm CMOS technology node. [ABSTRACT FROM AUTHOR]

An all-digital phase locked loop (ADPLL) with a proposed time-to-digital converter (TDC) which has no delay cell is designed by the 0.13-\mum CMOS process. The delay-cell-less TDC (DLTDC) that can suppress device noises and PVT mismatches is essential for wider bandwidth operations. Moreover, sub-gate TDC resolution can be achieved with the proposed DLTDC. A ring-VCO based digitally-controlled oscillator (DCO) which reduces 1/f noise is also proposed to enhance noise performance. The 2 MHz BW ADPLL which occupies 0.42 mm^2 consumes 12 mA and its measured jitter is 4 psrms at 2.4 GHz. [ABSTRACT FROM PUBLISHER]

All-digital phase-locked loops (ADPLL) are inherently multirate systems with time-varying behavior. In support of this statement linear time-variant (LTV) models of ADPLL are presented that capture spectral aliasing effects that are not captured by linear time-invariant (LTI) models. It is analytically shown that the latter are subset of the former. The high-speed ΣΔ modulator that improves the frequency resolution of the digitally-controlled oscillator (DCO) is included, too. It realizes fractional resampling and interpolation of the tuning data of the DCO. The noise transfer from all three operating clock domains of the ADPLL (reference, ΣΔ, and DCO) to its output phase is accurately predicted and design metrics are derived with regard to its folded close-in and far-out phase noise performance. The analytical results are validated via simulations using measured event-driven modeling techniques for a CMOS RF ADPLL. [ABSTRACT FROM PUBLISHER]

In a nonideal PLL circuit, leakage of the reference signal into the control line produces spurious tones. When the distorted PLL signal is used as a sampling clock to an analog-to-digital converter (ADC), it creates spurious sidebands in the sampled data as well. In spectrum sensing applications, the presence of spurious sidebands can lead to false detection of signals in otherwise empty channels. To remove the spurious sidebands, we first estimate the distortions to the sampled data and then compensate the data in the digital domain. To reduce hardware complexity and computation cost, we propose an algorithm that uses a Fourier Transform block (a typical component in spectrum sensing architectures) to estimate the sampling errors from the spurious sidebands. We also analyze the effects of the spurious sidebands on spectrum sensing. Computer simulations are included to show that the proposed solution can remove the spurious sidebands and improve the detection performance. [ABSTRACT FROM PUBLISHER]

Duty-cycled low-rate Internet-of-things (IoT) sensors are employed in diverse applications, requiring configurable and energy-efficient on-chip and on-demand clock synthesis. We present an all-digital frequency-locked loop (AD-FLL) capable of generating an accurate clock selectively in stand-alone operation or locked to a 32kHz reference. We report measurement results of two prototypes in 65nm and 28nm CMOS offering a configurable clock multiplication factor of up to 32 786, resulting in a wide tuning-range from a few MHz to 2.4GHz and 1.6GHz, respectively. The challenges of slow start-up and deterministic jitter are addressed by a fast hybrid-mode start-up procedure and by various jitter reduction modes. We also introduce the concept of Transient Clocking that leverages the capabilities of the proposed AD-FLL to make a system operational after cold-start or wake-up before the supply voltage has stabilized. We study two application examples that highlight the versatility of the concept in IoT applications and show its potential to amortize the time and energy cost of typical system start-up tasks, like state-restoration or wake-up event classification. [ABSTRACT FROM PUBLISHER]

The influence of coupling of oscillators in phase-locked loops (PLLs) was studied here. Particularly, numerical analyses based on nonlinear differential equations of the self- and mutual coupling systems were performed and compared with the results of the linear approximation model under synchronous conditions. The analysis revealed that coupling using the reference clock caused greater PLL instability than that caused by self-coupling for a given coupling strength. This shows that the phase error of mutual coupling exhibits the same behavior as that of reference-clock coupling in the single PLL under synchronous conditions, and the noise sensitivity of mutual coupling is twice that of the reference-clock coupling. In addition, the phase error of mutual coupling in the quasi-synchronous condition strongly depends on the relationship between the frequency difference of the two PLLs and the PLL bandwidth. We designed and fabricated the test circuits for theoretical verification using the 0.18- $\mu \text{m}$ standard CMOS process. From the measurements, adjustment of the timing difference between the two PLLs is effective in mitigating mutual coupling under synchronous conditions. Moreover, we implemented mutual injections between two oscillators in the test circuit and confirmed their effectiveness. The proposed methods will be useful for achieving the compact and effective cancellation of the mutual coupling between PLLs. [ABSTRACT FROM AUTHOR]

A low phase noise injection-locked reference clock multiplier that can suppress the delta-sigma (\Delta\Sigma) noise of \Delta\Sigma phase-locked loops (PLLs) is proposed. By adopting a two-phase PVT-calibrator that switches the calibration resolution, the clock multiplier can reduce the frequency-acquisition time, as well as tightly regulate the real-time degradation of the phase noise. To improve the performance of the calibration method utilizing two identical oscillators, the self-injection pulse generator that balances the loadings of two oscillators is proposed. In addition, this work presents a systematic design methodology that minimizes the degradation of the phase noise over the PVT variations, based on the phase noise analysis of injection-locking. The clock multiplier was designed with the prototype \Delta\Sigma PLL in the 65-nm CMOS process. It can provide five reference frequencies, i.e., 19.2, 28.8, 48, 57.6, and 96 MHz. The phase noise of the 96-MHz signal was -130.0 and -131.8 dBc/Hz at 100 kHz and 1 MHz offsets, respectively; the performance of low phase noise was confirmed over temperature variations. The total active area was 0.062 mm2, and the power consumption was 1.6–1.9 mW. By switching the reference frequency from 19.2 to 96 MHz, the phase noise of the prototype PLL at the 10-MHz offset from the 4.4-GHz signal was improved from -120.1 to -138.6 dBc/Hz. [ABSTRACT FROM AUTHOR]

We propose an enhancement to the digital phase detection mechanism in an all-digital phase-locked loop (ADPLL) by randomization of the frequency reference using carefully chosen dither sequences. This dithering renders the digital phase detector, realized as a time-to-digital converter (TDC), free from any phase domain spurious tones generated as a consequence of an ill-conditioned sampling of the feedback variable oscillator phase. In modern nanoscale technologies, TDC has a time quantization of 5 to 30 ps. This deadband can potentially result in spurious tones, whenever a near integer-N relationship arises between the oscillator frequency and the TDC sampling process. This work proposes injection of a spectrum-friendly short sequence dither into the reference clock signal to overcome the quantization introduced limit-cycles. This results in robust phase tracking performance and spurious-free operation of the ADPLL, which was verified in a 65-nm CMOS GSM/EDGE transmitter. [ABSTRACT FROM PUBLISHER]

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL’s phase detector (2.7–4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of −232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of −247dB, and normalized TR and area (FOMTA) of −262dB. [ABSTRACT FROM AUTHOR]

This work presents a producer-consumer link between two independent clock domains. The link allows for metastability-free, low-latency, high-throughput communication by slight adjustments to the clock frequencies of the producer and consumer domains steered by a controller circuit. Any such controller cannot deterministically avoid, detect, nor resolve metastability. Typically, this is addressed by synchronizers, incurring a larger dead time in the control loop. We follow the approach of Friedrichs et al. (TC 2018) who proposed metastability-containing circuits. The result is a simple control circuit that may become metastable, yet deterministically avoids buffer underrun or overflow. More specifically, the controller output may become metastable, but this may only affect oscillator speeds within specific bounds. In contrast, communication is guaranteed to remain metastability-free. We formally prove correctness of the producer-consumer link and a possible implementation that has only small overhead. With SPICE simulations of the proposed implementation we further substantiate our claims. The simulation uses 65nm process running at roughly 2GHz. [ABSTRACT FROM AUTHOR]