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This paper presents a CMOS image sensor (CIS) utilizing a noise-shaping successive-approximation register analog-to-digital converter (SAR ADC) incorporating the delta-readout scheme. While the noise-shaping SAR ADC with a proposed two-tap passive finite-impulse response (FIR) filter improves effective resolution, the delta-readout scheme reduces its power consumption. A prototype 1920 x 1440 pixel CIS was fabricated in a 90-nm CIS process. A single-channel readout SAR ADC occupying an area of 22.4 µm x 715 µm was implemented for reading out 16 columns of pixel array, consuming 437 µW. Owing to the proposed noise-shaping SAR ADC with oversampling ratio of 16, this paper achieves a noise reduction of 14 dB compared with the noise of a conventional SAR ADC. The delta-readout reduces the power consumption of the SAR ADC by 10% due to the high hit rate of the full high definition image format. The measured differential nonlinearity of the ADC is +0.77/-0.54 LSB and the integral nonlinearity is +0.81/-0.5 LSB. The prototype CIS consumes a total power of 64 mW and achieves a dynamic range of 66.5 dB and a figure of merit of 127 µV·nJ at a data rate of 138 Mpixels/s. [ABSTRACT FROM AUTHOR]

Efficient charge carrier transport in organic thin film transistors (OTFTs) often requires thin films with highly oriented feature. Although there are a number of methods to effectively form high-degree and large-scale alignment during the process of film formation, these methods usually resulted in nonuniform films. In order to obtain highly aligned uniform films, this paper provides a postalignment method after film formation. By applying electric field during solvent annealing, the polymer backbone can be reorganized along the direction of the electric field, leading to highly aligned polymer chains and significant improvement in charge mobility. In addition, after doping the polymer films with liquid crystal (LC), with the benefit of LC molecules' template, the degree of orientation of polymer molecular chains was further enhanced, resulting in further improvement of the charge mobility up to 9.42 cm² ·V-1·s-1. This paper exhibits the possibility of improving charge transport after film formation to obtain high-performance solution-processable OTFT for low-cost and large-scale organic electronics. [ABSTRACT FROM AUTHOR]

In this paper, we propose a tunable terahertz (THz) radiation source that utilizes a free electron beam to generate THz diffraction radiation coupled with the guided modes in a cylindrical corrugated waveguide. Detailed theoretical analyses and computer simulations are conducted, and the results demonstrate the characteristics of the tunable radiation frequency. In particular, the coherent diffraction radiation excited by a prebunched electron beam is discussed both theoretically and numerically with regard to the enhancement of the radiation power and efficiency. This paper may offer attractive prospects for the development of compact and tunable radiation sources in the THz frequency regime. [ABSTRACT FROM AUTHOR]

In this paper, reliability issues of In2O5Sn (indium-tin oxide: a transparent material) transparent gate recessed channel (TGRC)-MOSFET has been analyzed by considering the effect of interface trap charges (both positive and negative) present at the Si/SiO2 interface. Following device, characteristics are studied in terms of static, linearity, and intermodulation figure of merits. It is found that with the amalgamation of the transparent gate indium tin oxide on conventional recesses channel (CRC) MOSFET, it exhibits improved immunity against interface trap charges in comparison to CRC-MOSFET. In addition, the influence of ambient temperature (150-300 K) along with trap charges on TGRC-MOSFET has also been explored with an aim to analyze at which temperature of the device is more stable in the presence of interface defects (trap charges). Results obtained reveal that TGRC shows improved device performance at low temperature with trap charges being less influenced. Thus, this paper demonstrates that TGRC MOSFET can act as a promising candidate for low-power linear analog applications, where low temperature is required. [ABSTRACT FROM AUTHOR]

This paper demonstrates the use of doublegate accumulation mode (AM) and junctionless (JL) transistors for dynamic memory applications at 85 °C. The doping dependent assessments of AM and JL devices include an analysis of storage volume, carrier lifetime, and depth of potential well to determine characteristics of Dynamic Random Access Memory (DRAM). This paper shows significant impact of carrier lifetime for channel doping (Nd) ≤ 1018 cm-3 on Retention Time (RT), while the depth of potential well is more critical at higher doping (>1018 cm-3). RT of ~2.5 s at 85 °C and ~4.5 s at 27 °C is achieved for gate length (Lg) of 400 nm with Nd = 1017 cm-3 which reduces to ~90ms at 85 °C for Lg = 25 nm. This paper discusses the storage volume (Lg x film thickness for a fixed volume with width of 1 µm) optimization to attain maximum retention. Insights and guidelines, as a function of doping and device dimensions, are outlined for dynamic memory applications. [ABSTRACT FROM AUTHOR]

Graphene provides a new opportunity for thermoelectric study based on its unique heat transfer behavior controllable by a gate voltage. In this paper, an effective thermal conductivity model of graphene for thermoelectric cooling is proposed. The model is based on a double-voltage-control mechanism. According to the law of Fourier heat conduction, an effective thermal conductivity model of the proposed thermoelectric cooling device is derived taking a tunable external voltage into account. Then, a gate voltage is used which can change graphene's thermoelectric characteristics. To verify the correctness and effectiveness of the proposed model, a circuit simulation model using HSPICE is built based on the thermoelectric duality. The simulation results from HSPICE and the calculated results from the mathematic model show good agreements with each other. This paper provides a novel precisely controlling method for thermoelectric cooling. [ABSTRACT FROM AUTHOR]

This paper aims to investigate a porous silicon (PS)-based edge termination for planar type ac switch. TRIAC device prototypes, specifically dedicated to evaluate blocking performances, are fabricated by integrating electrochemical etching in device processing. A mixed porous morphology containingmicro-, meso-, and macropores is obtained in a p-Type through-wafer-diffused via after anodization. The fabricated prototypes show PS-dependent blocking capabilities. The possible impacts of the anodization conditions and the physical features of PS on the electrical characteristics are discussed in detail. Low leakage currents (<10 µA) have been demonstrated up to several hundred voltages for both bias polarities. The forward blocking voltage decreases with increasing PS thickness, while an opposite trend is observed for the reverse blocking voltage. This paper confirms the interest of PS as a potential insulating material for power device manufacture. [ABSTRACT FROM AUTHOR]

Metal--insulator--metal (MIM) diodeswith ultrathin insulators are highly promising for a variety of applications, such as vertical integration technology. However, MIM diodes with thin enough structures have not been achieved in previous studies on diodes using Schottky emission or tunneling conduction asymmetry. In this paper, we demonstrate an MIM diode with an ultrathin, 5-nm ZrO2/Al2O3/ZrO2 insulator, using the work-function difference between the top and bottom electrodes. The rectifying properties of the diode were enhanced by employing RuO2 as an electrode, due to its high work function and the catalytic effect on oxygen decomposition, contributing to the suppression of trap-assisted tunneling. This paper presents an important development in understanding MIM structures with respect to the electrical and chemical properties. [ABSTRACT FROM AUTHOR]

Although oxide thin-film transistors (TFTs) have drawn great interests in flexible displays, a key obstacle is the requirement of high-temperature annealing to realized mobility >10 cm²/V · s. In this paper, a fully room-temperature strategy, involving the deposition of ~10 nm In-Ga-Zn-O (IGZO) channel layer and ~4 nmAl2O3 passivation layer, is introduced. The as-prepared flexible TFT on polymide substrate exhibits a saturation mobility of 15.3 cm²/V · s, Vth of 3.08 V, and on/off current ratio of 2.3 x 107. Thickness-dependent analysis indicates that the interface between Al2O3 and IGZO is composed of negative O-rich layer, which impel the energy band bending inside the IGZO layers and release of electrons from traps. This paper opens up a route to achieve fully room-temperature fabrication of high-performance flexible TFT. [ABSTRACT FROM AUTHOR]

This paper describes the separation between the area and the perimeter current density components of 4H-SiC vertical p+-i-n diode with a circular Al+ implanted emitter of different diameters in the range 150-1000 µmand for temperatures of measurement in the range 30-290 °C. It is shown that before the diode series resistances become dominant, the forward current is given by the sum of an area plus a perimeter component, both of exponential trend with ideality factor 2; while toward high voltages, an area componentwith exponential trend and ideality factor 1 adds to the previous components. Moreover, this paper shows that forward area and perimeter current density components can be used for a straightforward identification of the parameters controlling the current transport, provided that they can be fit by the p-n junction equations in the frame of the abrupt junction approximation. Finally, this paper shows that the area reverse current density can be used for the identification of the electrically active defects in the drift layer. [ABSTRACT FROM AUTHOR]

There have been a lot of ambiguities related to physics of quasi-saturation (QS) in laterally diffused MOS (LDMOS) devices in the published literature. For example, models that explain QS in input characteristics do not explain the same in output characteristics and vice versa. In addition to this, none of the earlier models explain early onset of QS at higher temperatures nor the models were validated using counter arguments. Attributed to this, a need for unified theory explaining physics of QS is justified in this paper. Furthermore, this paper for the first time, while addressing missing links between the observations reported in the past, develops a unified theory to explain physics of QS behavior. The theory presented here is independent of device architecture and covers all voltage-current–temperature trends. While considering velocity saturation and space charge modulation, we have discovered key role of high field mobility degradation of majority carriers and electric field screening, which is found to be the root cause of QS in LDMOS devices. The theory presented is further validated with numerous counter arguments. Finally, based on the new physical insight developed, we have proposed different approaches to mitigate QS effect. A detailed device design guideline to mitigate QS and its correlation with analog/RF performance, electo static discharge, hot-carrier reliability, self-heating, and safe operating area concern is presented in Part II of this paper. [ABSTRACT FROM PUBLISHER]

Transconductance efficiency ( gm/{I}D ) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of gm/{I}D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultrathin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the gm/{I}D -based design methodologies usage in DG FDSOI transistors sizing. [ABSTRACT FROM AUTHOR]

This paper demonstrates the influence of nonuniform doping on the electrostatics of symmetric double-gate junctionless transistor using empirical modeling scheme. To present the clear insight into the device electrostatics of nonuniform doped channel, the peak of the doping concentration has been varied from Si/SiO2 interface of front gate to the back gate. The parameters explored in this paper are surface potential, electric field, drain current, threshold voltage, subthreshold slope, and drain-induced barrier lowering for different straggle factors and channel lengths. By properly optimizing the straggle value and peak of the doping concentration, device performance can be tuned accordingly. [ABSTRACT FROM AUTHOR]

In this paper, we present an experimental analysis of the degradation induced by positive bias temperature instability stress in GaN-based power high electron mobility transistors with p-type gate, controlled by a Schottky metal/p-GaN junction. In particular, the role of the aluminum content (Al%) in the AlGaN barrier layer on the threshold voltage degradation is investigated by means of constant voltage stress measurements. This has been performed for different process conditions with varying Al content. Main results in this paper demonstrate that when a relatively large positive bias is applied on the gate, two competing trapping mechanisms take place in the AlGaN barrier layer or at the p-GaN/AlGaN interface causing V\text {TH} instability. First, an aluminum independent hole trapping mechanism, caused by elastic tunneling from p-GaN valence band (2-D hole gas), leads to a relatively short-time and recoverable negative V\text {TH} shift. In the second step, defect creation occurs. These additional defects are filled with electrons and cause a permanent or slowly recoverable positive V\text {TH} degradation. The amount of defect creation was dependent on the Al% in the barrier. [ABSTRACT FROM PUBLISHER]

With the development of novel device applications, e.g., in the field of Internet of Things or point-of-care personalized diagnostic systems, came an increased demand for MESFETs for fast and low-power consumption integrated circuits and active-matrix displays. In this paper, we present fabrication and characterization of transparent Ru–Si–O/In–Ga–Zn–O MESFETs on flexible substrates. The use of transparent conducting oxide, namely, Ru–Si–O, as Schottky gate electrode, allows for processing the devices at room temperature, enabling the utilization of such low-temperature substrates as polyethylene terephthalate foil and paper. It was shown that tuning the device geometry allows realization of transistors providing on-current up to 2 mA, while the highest on-to-off current ratio equals 2\times 10^\mathrm 5 , with off-current below 1 nA, carrier mobility in the channel exceeds 9 cm ^\mathrm 2\cdot \textV^\mathrm -1\cdot \texts^\mathrm -1 , and subthreshold swing is below 250 mV $\cdot $ decade ^{\mathrm { {-1}}} . [ABSTRACT FROM PUBLISHER]

This index covers all technical items - papers, correspondence, reviews, etc. - that appeared in this periodical during the year, and items from previous years that were commented upon or corrected in this year. Departments and other items may also be covered if they have been judged to have archival value. The Author Index contains the primary entry for each item, listed under the first author's name. The primary entry includes the co-authors' names, the title of the paper or other item, and its location, specified by the publication abbreviation, year, month, and inclusive pagination. The Subject Index contains entries describing the item under all appropriate subject headings, plus the first author's name, the publication abbreviation, month, and year, and inclusive pages. Note that the item title is found only under the primary entry in the Author Index. [ABSTRACT FROM AUTHOR]

A self-assembly and electrostatic (SAE) carrier technology is developed for high-precision and high-throughput chip-to-wafer 3-D integration. In this paper, water surface tension-driven chip assembly is combined with electrostatic adhesion to keep high alignment accuracies obtained by the capillary self-assembly process. The self-assembled chips can be firmly fixed on an SAE carrier wafer by electrostatic adhesion, and then, the chips can be readily detached from the carrier by discharging and transferred to another carrier with a temporary adhesive. This paper describes the impact of chip clamping forces and electrical reliability of the SAE carrier on chips to be 3-D stacked in chip-to-wafer configuration. Through-Si via formation is demonstrated by using a via-last 3-D integration process based on the SAE carrier. The demonstration shows that the SAE carrier maintains higher chip alignment accuracies than does conventional carrier without electrostatic adhesion. [ABSTRACT FROM AUTHOR]

In this paper, a physics-based compact model for calculating the semiconductor charges and gate capacitance of III-V nanowire (NW) MOS transistors is presented. The model calculates the subband energies and the semiconductor charges by considering the wave function penetration into the gate insulator, effective mass discontinuity at the semiconductor-oxide interface, 2-D confinement in the NW, and Fermi-Dirac statistics. The semiconductor charge expression proposed in this paper is completely explicit in terms of applied gate voltage, therefore, making it highly suitable for large circuit simulations. The model is also compared with the results from self-consistent Schrödinger-Poisson solver for different NW sizes and materials and found to be accurate over a wide range of gate voltages. [ABSTRACT FROM AUTHOR]

With the emergence of a multichip Light-emitting diodes (LEDs) device based on different chip arrays, a new modeling for a multichip LED device with different array becomes urgent. This paper presents a compact thermal model (CTM) for the multichip LED device with different chip array for nonuniform thermal properties. Based on a general 3-D CTM, LED chips can be arranged in various array forms according to the multichip LED construction design. By linking the thermal matrix to junction temperature prediction, the proposed CTM provides accurate predictions of temperature distribution of the multichip LED device, compared to the practical physical model and infrared radiation measurement. The modeling technique has been successfully demonstrated and verified. Based on the proposed method, this paper presents the multichip LED device with a staggered array to optimize the LED positions so that heat concentration of the LED array can be reduced. [ABSTRACT FROM AUTHOR]

Parasitic capacitance in nanoscale FETs is becoming a dominant component of the total device capacitance which degrades device and circuit performance. This problem is exacerbated with the introduction of multigate FETs such as FinFET and gate-all-around FETs. In this paper, we introduce the corner spacer design for gate-all-around nanowire FET to significantly decrease parasitic capacitance with negligible degradation in ON-current. We show that the parasitic capacitance of a well-engineered corner spacer in a nanowire FET can be reduced by over 80% compared to the device with full nitride spacers. Ring oscillator stage delay and energy consumption of the corner spacer design are lower than the full spacer by over 50% each. This paper shows the possibility of engineering the spacers as a performance booster to continue scaling. [ABSTRACT FROM AUTHOR]

This paper presents using ultrasonic spray pyrolysis deposition method to grow MgO nanorod arrays on the top surface and the sidewall of the GaN-based ultraviolet light-emitting diodes. It is found that when the thickness of the MgO film is over 60 nm, the self-assembled MgO nanorod arrays are obtained. Transmission electron microscopy, scanning electron microscopy, X-ray diffraction, X-ray photoelectron spectroscopy, refractive index, extinction coefficient, and photoluminescence spectrum are used to analyze the structural, chemical, and optical characteristics of the MgO nanorod arrays. The LED chip with the MgO nanorod arrays shows slightly degraded electrical characteristics for it requires a higher forward voltage to provide 0.35-A forward current and higher series resistance. However, the LED chip with the MgO nanorod arrays has great improvement in electroluminescence and efficiency. Compared to the LED chip with a standard SiO2 passivation layer, the LED chip with the MgO nanorod arrays shows improvement of 14.1% in light output power (LOP), 12% in external quantum efficiency and wall plug efficiency. The uniformity of the LED performance like forward voltage, LOP, and wall-plug efficiency is investigated in this paper. [ABSTRACT FROM AUTHOR]

With lots of interest in negative capacitance field-effect transistors for ultralow-power complementary metal-oxide-semiconductor technology, negative capacitance thin-film transistors (NCTFTs) have also received much attention. Although previous studies on NCTFTs were done, the NC effect in organic-based TFTs was not studied yet. In this paper, P(VDF-TrFE) ferroelectric-gated P3HT semiconductor channel TFTs are experimentally demonstrated with solution-based fabrication process. Especially, this paper shed light on the NC effect in the organic based TFTs. The step-up current-voltage characteristics are repeatedly and reliably observed in diverse TFTs, and then, with the results, transconductance (gm) amplification implemented by the negative capacitance was delved. Moreover, with the aid of ferroelectric polarization switching, super steep-switching characteristic of the organic-based TFT was experimentally confirmed. These experimental results and discussion would be helpful in understanding NC effects in TFTs. [ABSTRACT FROM AUTHOR]

In contrast to the conventional planar p-i-n photodiode and a metal-semiconductor-metal photodetector, the 3-D dual-gate photosensitive thin-film transistor (TFT) architectures presented here attain excellent photoresponse characteristics. Operating the device in the subthreshold regime further boosts the photoconductive gain as a result of light-induced decrease in the threshold voltage. This paper presents design considerations along with a performance comparison between 3-D photosensitive TFTs that have π- and FIN-shaped channels and conventional TFT with a planar channel. Our paper shows that the π-shaped structure tends to have a higher sensitivity while the FIN-shaped counterpart is more responsive with wider dynamic range. For both structures, a measured photoconductive gain of 104~106% is obtained with spectral responsivity ranging from near UV to near IR, and the photoresponse time in the range of tens of milliseconds. The 3-D dual-gate photosensitive TFT architecture appears to be very promising for large-area, low-level UV, visible, and IR detection applications. [ABSTRACT FROM AUTHOR]

The physical mechanisms involved in the trapping and de-trapping processes associated with surface donor traps in gallium nitride (GaN) transistors are discussed in this paper. The paper challenges the conventional transient techniques adopted for extrapolating the trap energy level via experiments and TCAD simulations. Transient TCAD simulations were employed to reproduce the time-dependent electrical behavior of a metal-on-insulator field-effect transistor and explain the influence of the electric field and energy barrier on the transient time associated with the trapping and de-trapping mechanisms of surface traps. The comparison between three test structures and the relative variation of the trapping and de-trapping times with the bias and trap parameters leads to the suggestion of a proposed test structure and bias configuration to accurately extrapolate the energy level of surface traps in GaN transistors. [ABSTRACT FROM AUTHOR]

One shortcoming of capacitive micromachined ultrasonic transducers (CMUTs) for commercial use is the weak output power relative to traditional ultrasonic transducers. Recently, we reported an annular CMUT cell with an improved transmit efficiency over a conventional circular cell in air. Extending this paper, we designed and fabricated a nine-element concentric CMUT array to enhance the transmit power and offer depth focusing. The proposed 200-kHz array has an aperture diameter of 2.13 cm and a fill factor of 81%. A pillar-free etching process was developed to create the deep large-area cavities of the proposed wafer-bonded CMUT. The fabricated device was characterized for the static and dynamic performance using a profilometer and a laser Doppler vibrometer, respectively. The average maximum plate dynamic displacements of the CMUT driven by 20-Vpp ac excitation voltage at dc biases of 100 and 150 V were measured to be 1.28 and 1.97 μm, respectively. Accordingly, the surface output power densities were calculated to be 0.40 and 0.96 KW/m2. We investigated the crosstalk between neighboring cells and the plate-cracking phenomenon, and provided relative suggestions for improvement. This paper demonstrates the feasibility of the concentric annular-cell CMUT array design for air-coupled applications. [ABSTRACT FROM PUBLISHER]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

In this paper, a p-channel vertical 4H-silicon carbide (SiC) MOSFET (SiC p-MOSFET) has been fabricated successfully for the first time as a potential candidate for the complementary inverter application. The static characteristics and the robustness, including short circuit and avalanche capabilities of the p-MOSFET, are experimentally tested. Moreover, the comparison between the p-MOSFET and similar rating n-MOSFET is carried out. The short-circuit capability is 15% higher than that of the n-channel MOSFET. Furthermore, this paper also provides the physical insights into the failure mechanism during the short-circuit transient of the p- and n-MOSFET. Meanwhile, an electro-thermal analytical model is proposed to explain the thermal distribution during this transient. Last, the avalanche withstand time of the fabricated SiC p-MOSFET is experimentally demonstrated to be 27% higher than that of the n-channel one. It is concluded that the SiC p-MOSFET could be a competitive power switch applicable for high-frequency complementary inverters. [ABSTRACT FROM PUBLISHER]

Conventionally, integrated drain-extended MOS (DeMOS) like high-voltage devices are designed while keeping only performance targets for a given application in mind. In this paper, for the first time, performance and reliability codesign approach using 3-D TCAD has been presented for various superjunction (SJ) type DeMOS devices. In this context, how to effectively utilize the SJ concept in a DeMOS device for System on Chip applications, which often has stringent switching and RF performance targets, is explored in detail in this paper. Moreover, design and reliability tradeoffs for switching and RF applications are discussed, while considering two unique sets, one with fixed breakdown voltage and other with fixed ON-resistance. Finally, hot carrier generation, safe operating area concerns, and electrostatic discharge physics are explored and compared using 3-D TCAD simulations. [ABSTRACT FROM PUBLISHER]

In this paper, an innovative process flow developed to improve the thermal resistance of power ICs was presented. In this field, one of the major device failure mechanisms is related to the high temperatures reached during the working cycles due to the extremely critical electrical current densities. Therefore, heat transfer and dissipation are crucial aspects that need continuous improvements. Usual approaches to face this issue deal with package heat sinks design, solder selection, and wafer thinning. In this paper, a novel technological approach was settled, in which heat sinks microstructures were successfully integrated at wafer level stage on standard p-i-n diodes. To this aim, the bulk Si on the backside was partially replaced with Cu, a material characterized by a higher thermal conductivity material. Moreover, the well microstructures filled by Cu provide the advantage of wafer self-support, without requiring dedicated and more expensive thinning and handling technologies. An extensive characterization of the final devices was also carried out to evaluate the process and the thermal and electrical improvements. Finally, a failure analysis on selected devices was performed to identify any critical issue with the standard packaging process. [ABSTRACT FROM PUBLISHER]

The metal–semiconductor interface is fundamental to any semiconductor device and the success of advanced technology nodes critically depends upon the minimization of the contact resistance at the interface. In this paper, we calculate the electronic structure of a metal–semiconductor interface (TiGe/Ge contact) within the framework of first-principles density functional theory simulations. We report the modulation of the Schottky barrier height with respect to the different phases of TiGe metal and different crystallographic orientations of Ge substrate. We further compute the I – V characteristics of the TiGe/Ge contact with nonequilibrium Green’s function formalism, using a two-terminal device configuration. The calculated transmission spectrum allows us to extract the contact resistance at the metal–semiconductor interface. Furthermore, the onset of Ohmic contact for p-doped TiGe/Ge interface is identified by studying the I – V characteristics as a function of increasing active carrier concentration. We find that a doping concentration of 1e21 is sufficient to transform the Schottky contact into Ohmic and thereby achieve a least possible contact resistance at the interfaces. Our paper thus provides useful physical insights into the nanoscale details of the TiGe/Ge interfaces and can guide further process development to minimize the contact resistance. [ABSTRACT FROM PUBLISHER]

A low-leakage electrostatic discharge power clamp with adjustable triggering voltage ( Vt1) is proposed in this paper. By enabling the static detection path using the transient one, the proposed clamp achieves a wide range of adjustable Vt1 while maintaining low standby leakage current ( I\text {leak}) , which overcomes the flaw of traditional static clamps. Besides, the adjustable Vt1 with low I\text {leak} is attractive for nanoscale applications. Moreover, the proposed clamp achieves enhanced false-triggering immunity over traditional transient clamps. The proposed clamp is successfully verified in a 65-nm CMOS process. Aside from silicon verifications, detailed comparisons with prior arts and practical application concerns are also addressed in this paper. [ABSTRACT FROM PUBLISHER]

Wafer-scale, CMOS compatible graphene transfer has been established for device fabrication and can be integrated into a conventional CMOS process flow back end of the line. In Part I of this paper, statistical analysis of graphene FET (GFET) devices fabricated on wafer scale is presented. Device yield is approximately 75% (for 4500 devices) measured in terms of the quality of the top gate, oxide layer, and graphene channel. Statistical evaluation of the device yield reveals that device failure occurs primarily during the graphene transfer step. In Part II of this paper, device statistics are further examined to reveal the primary mechanism behind device failure. The analysis from Part II suggests that significant improvements to device yield, variability, and performance can be achieved through mitigation of compressive strain introduced in the graphene layer during the graphene transfer process. The combined analyses from Parts I and II present an overview of mechanisms influencing GFET behavior as well as device yield. These mechanisms include residues on the graphene surface, tears, cracks, contact resistance at the graphene/metal interface, gate leakage as well as the effects of postprocessing. [ABSTRACT FROM PUBLISHER]

This paper investigates the impacts of typical semiconductor material properties—electron affinity, bandgap, and dielectric constant, on the electrical performance of a p-type core–shell heterojunction nanowire FET by numerical simulations. At the heterojunction, a valence band offset of 200 meV forms a sufficient energy barrier confining the holes in the quantum well, resulting in the optimal OFF-state current. A higher dielectric constant of the shell region is found to be able to decrease the leakage current of the device. The optimum conditions from the parameter analysis are demonstrated by a realistic and achievable material combination of Si/SiGe for the core–shell configuration. This paper provides physical insights into the materialwise impacts for designing the proposed transistor showing the reduced OFF-current and a better subthreshold swing for low-power applications. [ABSTRACT FROM PUBLISHER]

As the transparent contact in radial p-n junction core-shell nanowire array solar cells can be either planar or conformal, the characteristics of these two types of device structure would be very different since conformal contact gives rise to severe band bending. Although radial p-n junction GaAs core-shell nanowire array solar cell with conformal transparent contact has been briefly inferred to have an inferior performance compared to the same nanowire array solar cell with planar transparent contact, the characteristics of these two types of radial p-n junction core-shell nanowire array solar cells are not known. Furthermore, it is unknown how the performance of these two types of solar cell compares with each other when the nanowire design parameters are optimized according to device physics of these two types of solar cell. In this paper, it is shown that radial p-n junction GaAs core-shell nanowire array solar cells with planar transparent contact are prone to carrier avalanche breakdown, and hence have a limited range of doping density. On the other hand, carrier diffusion in radial p-n junction GaAs core-shell nanowire array solar cells with conformal transparent contact is poor and hence requires a high doping to the core in order to increase the output voltage. All in all, this paper reveals that either type of transparent contact structure yields essentially the same energy conversion efficiency as long as the radial p-n junction GaAs core-shell nanowires are designed to suit the device physics of the type of transparent contact. [ABSTRACT FROM PUBLISHER]

The effect of temperature and parasitic photocurrent on event-based dynamic vision sensors (DVS) is important because of their application in uncontrolled robotic, automotive, and surveillance applications. This paper considers the temperature dependence of DVS threshold temporal contrast (TC), dark current, and background activity caused by junction leakage. New theory shows that if bias currents have a constant ratio, then ideally the DVS threshold TC is temperature independent, but the presence of temperature dependent junction leakage currents causes nonideal behavior at elevated temperature. Both measured photodiode dark current and leakage induced event activity follow Arhenius activation. This paper also defines a new metric for parasitic photocurrent quantum efficiency and measures the sensitivity of DVS pixels to parasitic photocurrent. [ABSTRACT FROM PUBLISHER]

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

Gate dielectric damage caused by both internal and external stresses is becoming worse because of aggressive complementary metal–oxide–semiconductor (CMOS) scaling. However, conventional technologies for damage reduction using thermal annealing during fabrication have some limitations. As a result, there is a growing demand for technologies that will cure CMOS damage as a new paradigm for improving long-term reliability. This review paper reexamines self-recovery technologies, which are fully compatible with CMOS fabrication. Although self-heating has long been considered an unwanted operating side effect, it can also be favorably utilized to cure damage. Generated Joule heat arising from device operation can uniformly anneal the gate dielectric and effectively recover damage in various devices, such as conventional logic, memory, and aerospace CMOS devices, as well as thin-film transistors for displays. [ABSTRACT FROM AUTHOR]

This paper reviews what changed in the reliability of NAND Flash memory arrays after the paradigm shift in technology evolution determined by the transition from 2-D to 3-D integration schemes. Starting from a quick glance at the fundamentals of raw array reliability, the reasons for its worsening with the evolution of 2-D technologies will be discussed, focusing on the physical phenomena which contributed more to that outcome. By exploring the dependence of the magnitude of these phenomena on cell and array parameters, the abrupt improvements achieved from the 3-D transition in terms of raw array reliability will then be explained, highlighting also that these improvements were turned into new opportunities for the technology. Finally, the physical issues specific to 3-D arrays will be addressed, providing a glimpse of the challenges that the NAND Flash technology will have to face from the standpoint of array reliability in the near future. [ABSTRACT FROM AUTHOR]

This paper presents a modeling approach to simulate the impact of total ionizing dose (TID) degradation on low-power analog and mixed-signal circuits. The modeling approach has been performed on 180-nm n-type metal–oxide–semiconductor field-effect transistors (n-MOSFETs). The effects of the finger number, channel geometry, and biasing voltages have been tested during irradiation experiments. All Berkeley short-channel insulated gate field-effect transistor model (BSIM) parameters relevant to the transistor properties affected by TID have been modified in an algorithmic flow to correctly estimate the sub-threshold leakage current for a given dose level. The maximum error of the model developed is below 8%. A case study considering a five-stage ring oscillator is simulated with the generated model to show that the power consumption of the circuit increases and the oscillation frequency decreases around by 14%. [ABSTRACT FROM AUTHOR]

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier charge density within few discrete subbands. Combining a parabolic approximation of the Poisson equation, the first-order perturbation theory for the Schrödinger subband energy eigen-values and the Fermi–Dirac statistics for the confined carrier density lead to an explicit solution of the dc characteristic in ultrathin JL devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirm its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on JL nanowire devices. [ABSTRACT FROM AUTHOR]

In this paper, alternative operational mode (AOM) of Si-based blocked impurity band (BIB) detectors is thoroughly investigated. The basic structure of the detector evolves from the prototype of the ion-implanted BIB detector, which is potentially compatible with CMOS processes. Benefiting from lower dark current, the detectivity of ion-implanted devices studied in this work is comparable with the Si BIB detectors ever reported. For ion implantation devices, a peak blackbody detectivity of ${5} \times {10}^{{12}}$ cm $\cdot $ Hz1/2/W (background temperature T = 40 K) occurs at 2 V under AOM. These merits make the ion-implanted device a powerful candidate for a wide range of applications from infrared to terahertz band. By analyzing the carrier distribution and the band structure in different functional regions of the device at the measured temperature, depletion junction formed in the region of active layer near active layer/cathode interface side is deduced when the device is operated under AOM. The theory is successfully used to interpret experimental data, including the detectivity comparable to the epitaxial device, significantly reduced dark current. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, a physics-based bias-dependent model of single-event transients (SETs) in double-gate (DG) MOSFET suitable for circuit simulation is presented. The existing approaches that use double exponential and dual double-exponential current sources to emulate these transient currents in the circuit simulators depend on the parameters extracted from TCAD device simulations. In order to capture the essential physics behind these current transients in the circuit simulations, there is a need for a physics-based bias-dependent SET current model that considers the electrostatics in the chosen device. The proposed SET current model is developed from the solution of 2-D Poisson’s equation with proper boundary conditions of DG MOSFET. It takes into account the dependence of the transient potential and drain current on linear energy transfer (LET), strike positions, drain and gate biases, device dimensions, and channel doping. The results from the model are validated with the simulation results from TCAD. The SET current model is integrated in Cadence circuit simulator and observed through simulations the voltage perturbation at the output of the CMOS inverter due to heavy ion strike on nMOS transistor in OFF state for different LETs and loads. The proposed model captures the current plateau region effect in CMOS inverter. [ABSTRACT FROM AUTHOR]

Silicon nanowire (SiNW) field-effect transistors (SiNWFETs) are of great potential as a high-sensitivity charge sensor. The signal-to-noise ratio (SNR) of an SiNWFET sensor is ultimately limited by the intrinsic device noise generated by carrier trapping/detrapping processes at the gate oxide/silicon interface. This carrier trapping/detrapping-induced noise can be significantly reduced by replacing the noisy oxide/silicon interface with a Schottky junction gate (SJG) on the top of the SiNW. In this paper, we present a tri-SJG SiNWFET (Tri-SJGFET) with the SJG formed on both the top surface and the two sidewalls of the SiNW so as to enhance the gate control over the SiNW channel. Both experiment and simulation confirm that the additional sidewall gates in a narrow Tri-SJGFET indeed can confine the conduction path within the bulk of the SiNW channel away from the interfaces and significantly improve the immunity to the traps at the bottom buried oxide/silicon interface. Therefore, the optimal low-frequency noise performance can be achieved without the need for any substrate bias. This new gating structure holds promises for further development of robust SiNWFET-based charge sensors with low noise and low operation voltage. [ABSTRACT FROM AUTHOR]

In this paper, a nontoxic and environmentally friendly water-driven (WD) route to prepare InZnO thin films with various molar ratio of In and Zn has been reported. The formation mechanisms and physical properties of InZnO thin films as a function of element molar ratio are investigated by various characterization techniques. By comparing the performance of InZnO/SiO2 thin-film transistors (TFTs) at different element molar ratio, the results indicate that the molar ratio of 2:1 (In:Zn) is the optimal choice. Based on the optimal molar ratio, fully WD InZnO/HfOx TFT is fabricated and the excellent electrical properties are obtained at a low operating voltage of 5 V, including a higher field-effect mobility of 9.1 cm $^{{2}}\text{V}^{-{1}}\text{s}^{-{1}}$ , a larger ON-/OFF-state current ratio of ${1.5} \times {10}^{{7}}$ , a smaller subthreshold swing of 0.09 V/dec, and a smaller threshold voltage shift of 0.44 V after 5400-s bias stressing, separately. Finally, to further validate the feasibility of InZnO TFTs in complex logic circuits, an inverter is assembled based on the InZnO/HfOx TFT, exhibiting a high gain of 8.8. More importantly, the excellent properties of InZnO/HfOx TFT are achieved at a low-voltage stage, which stands for the great application prospects of WD TFTs in low-cost and excellent performance electronic devices. [ABSTRACT FROM AUTHOR]

This paper presents the first analytical model for the ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) in vertical power FinFETs. The model allows to extract the channel mobility and series resistance and to separate the current conduction through the bulk fin channel and the accumulation-mode metal–oxide–semiconductor (MOS) channel. The model was validated by experiments and simulations. The extracted series resistance was verified by measuring a diode fabricated in the same wafer with the FinFETs. At the same time, simulations using the extracted channel mobility and series resistance agreed well with the experiments. The model was then used to analyze a 1200 V GaN vertical power FinFET. The main ${R}_{ \mathrm{\scriptscriptstyle ON}}$ component was identified to be from the drift layer and the substrate, while the gate-modulated channel resistance only accounts for ~13% of the total device ${R}_{ \mathrm{\scriptscriptstyle ON}}$. Our model enables parameter extraction from the dc characteristics of a single device, and therefore, provides a fast and easy way to understand, analyze, and design vertical power FinFETs. Our model can also be adjusted to allow for fast and accurate parameter extraction in other power transistors with a vertical gate-modulated channel, such as trench MOSFETs. [ABSTRACT FROM AUTHOR]

This paper deals with optimum design and development of a thermionic electron gun to meet specified beam requirements within defined electric and geometric constraints for a Ka-band traveling wave tube (TWT) for space applications. The electron gun design is based on the Pierce method and carried out according to the iterative process indicated by Vaughan. The design of a periodic permanent magnet (PPM) beam focusing system for the stability of the beam is also required. A sensitivity analysis, by varying electric parameters and geometric parameters, is presented and taken into account as a fundamental role to the aim of optimizing the design of the Pierce gun. A cathode current value of 550 mA at a cathode voltage value of 20 KV with a beam diameter value of less than 0.55 mm, as a result of the analysis, is imposed as a goal design parameter, to obtain a TWT output power value more than 500 W. The simulated results show very good agreement with the beam tester experimental results. The body current measured value, in excellent agreement with the simulated one, shows the effectiveness of the design procedure. Data from the experimental beam tester demonstrate 98% beam transmission to the collector. [ABSTRACT FROM AUTHOR]

For the photovoltaic effect (PE), the surface potential is suggested to be an adverse factor, and researchers usually try to increase the thickness of the conductive layer or the number of strip electrodes to avoid it. However, the potential can still not be eliminated. More importantly, the huge cost has to be paid, and the photovoltaic performances are largely reduced. While the drawback of potential in PE may become excellent merit in lateral PE (LPE) due to their different working mechanisms. Moreover, the decreasing thickness of the conductive layer may be inversely used as an efficient method to modulate the LPE performances. In this paper, the indium tin oxide (ITO) conductive layer thickness-dependent LPE responses are well studied in the copper indium gallium selenide (CIGS) heterostructure. The LPE response is significantly improved with ITO thickness decreasing from 150 to 10 nm, and the thickness-dependent enhancement is strongly dependent on the illumination intensity, especially in high illumination intensities, a nonmonotonic thickness dependence is obtained. In addition, it is found that the heterostructure exhibits an ultrafast response speed of ~14.5 $\mu$ s/~15.0 $\mu$ s, and what is more, the response time nearly remains constant without depending on the ITO thickness. [ABSTRACT FROM AUTHOR]

This paper presents functional high-temperature analog circuits in silicon carbide bipolar technology. The circuits will collectively form the analog signal conditioning block for a wireless telemetry system in an extreme environment (above 400°C). The signal conditioning block is composed of a low dc gain operational amplifier, a negative voltage charge pump (CP), an RC oscillator, and a voltage regulator. The circuits are tested up to 450°C. The measured open-loop gain for the amplifier at 450°C is 30 dB. The regulator provides approximately 9-V output at 450°C for a fixed load current of up to 18 mA and an applied reference of 4.5 V. The negative voltage CP requires an oscillating signal at its input, which is provided by the RC cross-coupled oscillator. The CP provides about −5 V at 450°C. [ABSTRACT FROM AUTHOR]

In this paper, a new dual-pocket (DP), dielectric modulated (DM) heterostructured tunnel field-effect transistor (DM-HTFET)-based biosensor has been reported. First, the efficacy of the DP-hetero-TFET (HTFET) has been analyzed by comparing it with other existing TFET structures. Next, a comprehensive assessment of sensitivity between single-pocket (SP) and DP-DM-HTFET biosensors for pocket thickness (${T}_{\text {pocket}}$), pocket length (${L}_{\text {pocket}}$), pocket doping (${N}_{\text {pocket}}$), work function of the gate metal, molar fraction of Ge, gate oxide layer, and gate oxide layer thickness (${T}_{\text {ox}}$) was done. Hence, a nonuniform arrangement of biomolecules inside the cavity simulation has been done using ATLAS device simulation software to validate the working ability of the proposed sensor. Significant improvement in the sensitivity due to threshold voltage (ON-current) i.e., 26.78% (78.5%), 60.8% (40.4%), 56% (${2.2} \times {10}^{{2}}$ %), and 40.6% (80.68%) has been observed for the DP-DM-HTFET over SP with the variation of ${T}_{\text {pocket}}$ , ${L}_{\text {pocket}}$ , ${N}_{\text {pocket}}$ , and ${T}_{\text {ox}}$ , respectively. DP-DM-HTFET-based current mirror circuit has also been demonstrated at the end. Sensitivity evaluation discloses that the DP-DM-HTFET can be a promising candidate for CMOS-based label-free biosensing applications. [ABSTRACT FROM AUTHOR]