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In this paper, unclamped inductive switching (UIS) performance of the novel silicon–oxide–nitride–oxide–silicon (SONOS) gate power MOSFET (SG-MOSFET) is analyzed. The avalanche energy absorption of the SG-MOSFET at UIS is 5.2 times that of the conventional power MOSFET. Analysis shows that the improvement is due to the heavily doped p-body used in the device. Moreover, the influence of the structural parameters on the UIS performance of the device is experimentally characterized. Measurement results show that the UIS performance is not sensitive to the \p^+ contact width and slightly degrades with a larger gate length. Furthermore, the results show that it is promising to further improve the UIS performance of the device by using a more efficient charge trapping material in the gate dielectric to allow further increase in the p-body doping concentration. [ABSTRACT FROM PUBLISHER]

Resistive switching memory (RRAM) devices generally rely on the formation/dissolution of conductive filaments through insulating materials, such as metal oxides and chalcogenide glasses. Understanding the mechanisms for filament formation and disruption in resistive switching materials is a critical step toward the development of reliable and controllable RRAM for future-generation storage. In particular, the capability to control the filament resistance and the reset current through the compliance current during filament formation may provide a key signature to clarify the switching mechanism. This paper provides a physically based explanation for the universal resistance switching in bipolar RRAM devices. A numerical model of filament growth based on thermally activated ion migration accounts for the resistance switching characteristics. The same physical picture is extended to numerically model the reset transition. The impact of migration parameters and experimental setup on the set/reset characteristics is discussed through numerical simulations. [ABSTRACT FROM AUTHOR]

One of the most important degradation modes in CMOS technologies, the bias temperature instability (BTI) has been known since the 1960s. Already in early interpretations, charge trapping in the oxide was considered an important aspect of the degradation. In their 1977 paper, Jeppson and Svensson suggested a hydrogen-diffusion controlled mechanism for the creation of interface states. Their reaction–diffusion model subsequently became the dominant explanation of the phenomenon. While Jeppson and Svensson gave a preliminary study of the recovery of the degradation, this issue received only limited attention for many years. In the last decade, however, a large number of detailed recovery studies have been published, showing clearly that the reaction–diffusion mechanism is inconsistent with the data. As a consequence, the research focus shifted back toward charge trapping. Currently available advanced charge-trapping theories based on switching oxide traps are now able to explain the bulk of the experimental data. We give a review of our perspective on some selected developments in this area. [ABSTRACT FROM PUBLISHER]

This paper presents an evaluation of laterally double-diffused MOS transistors in synchronous dc–dc buck converters using a physical-based mixed device and circuit simulation. It is observed that impact ionization of the low-side transistor can be very high after the dead-time drain overshoot voltage point. In addition, heavy ion irradiation degrades power MOSFET performance and may lead to a potential circuit malfunction due to a significant increase in transient current if heavy ions strike the dc–dc buck converter at a critical time during switching. [ABSTRACT FROM PUBLISHER]

In this paper, the unclamped inductive switching (UIS) behavior of an inverted L-shaped source trench power MOSFET is numerically analyzed and experimentally characterized. The measured avalanche energy absorption at UIS of the new trench power MOSFET is 2.1 times that of the conventional trench power MOSFET. This is explained by numerical simulation, which shows that the voltage drop across the emitter/base junction in the parasitic bipolar junction transistor of the new structure is smaller than that of the conventional structure. The influence of structural and device size variation of the new trench power MOSFET on UIS performance is also investigated. Results show that the avalanche current density at UIS is a strong function of the \p^+-region width and the device size. Furthermore, the effect becomes very significant as the device size becomes very small. [ABSTRACT FROM PUBLISHER]

In this paper, the effect of various device design engineerings such as channel engineering, i.e., graded channel (GC), gate stack (GS) engineering (high-\kappa), and dual-material gate (DMG) on double-gate MOSFET (DG MOSFET) have been analyzed using ATLAS device simulator. Furthermore, the combinations of these technologies i.e., GC, along with GS engineering, i.e., GCGSDG, and GS together with DMG, i.e., GS dual-material DG (GSDMDG), have been taken into consideration. The simulation results demonstrate that, out of the several design engineerings, the GCGSDG is the most suitable for high-speed switching applications. However, the GSDMDG provides superior performance as an amplifier. [ABSTRACT FROM PUBLISHER]

The need for reliable models that take into account the nonlinear kinetics of dopants is nowadays of paramount importance, particularly with the physical dimensions of electron devices shrinking to the deep nanoscale range and the development of emerging nanoionic systems such as the memristor. In this paper, we present a novel nonlinear dopant drift model that resolves the boundary issues existing in previously reported models that can be easily adjusted to match the dynamics of distinct memristive elements. With the aid of this model, we examine switching mechanisms, current–voltage characteristics, and the collective ion transport in two terminal memristive devices, providing new insights on memristive behavior. [ABSTRACT FROM PUBLISHER]

This paper presents a nanotechnology-based high-power-density and low-power-loss on-chip power inductor for dc–dc switching power converters. This power inductor utilizes a composite of bundled multiwalled (concentric) carbon nanotubes (BMWCNTs) and Fe (iron) in order to achieve high performance in a small size. Titanium (Ti) is then added as a coating material on the BMWCNT-based power inductor. The BMWCNT-based power inductor with a single layer and three turns occupies an area of \200\ \mu\m \times \200\ \mu\m. It exhibits an inductance of 206 nH, a quality factor of 427 at 20 MHz, and a dc rated current of 100 mA. The power inductor size and the performance characteristics are competitive with state-of-the-art power inductors. The design, analysis, modeling, and simulation results of the BMWCNT-based power inductor are presented and compared with state-of-the-art conventional power inductors from the literature. [ABSTRACT FROM AUTHOR]

Bias temperature instability (BTI) is a serious reliability concern for MOS transistors. This paper covers theoretical analysis, Monte Carlo simulation, and experimental investigation of the charge trapping component of BTI. An analytical model for both stress and recovery phases of BTI is presented. Furthermore, the model properly describes device behavior under periodic switching, also called AC-BTI or cyclostationary operation. The model is based on microscopic device physics parameters, which are shown to cause statistical variation in transistor BTI behavior. It is shown that a universal logarithmic law describes the time dependence of charge trapping in both stress and recovery phases, and that the time dependence may be separated from the temperature and bias point dependence. Analytical equations for the statistical parameters are provided. The model is compared with experimental data and Monte Carlo simulation results. [ABSTRACT FROM AUTHOR]

This paper presents, for the first time, the study of the application of a lateral diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in a common-gate configuration to radio-frequency (RF) transmit/receive (T/R) switching circuits. A single-pole double-throw (SPDT) 900-MHz T/R switch is implemented using 0.25-\mu\m LDMOSFET foundry technology. Measured results show that our switching circuit can achieve a low insertion loss of 0.82 dB and a high power handling capability of 27 dBm. This result is promising in integrating power management integrated circuits, RF power amplifiers, and switching circuits in a single chip, based on LDMOSFET technology, to realize an RF transmit front-end system-on-chip solution. [ABSTRACT FROM AUTHOR]

The effects of vanadium doping on resistive switching (RS) characteristics and mechanisms of RF-sputtered SrZrO3 (SZO)-based thin films are investigated in this paper. The physical and electrical properties of SZO-based thin films are modulated by vanadium doping due to the Zr4+ ion replaced by V5+, further affecting the RS parameters of SZO-based thin films. The conduction mechanisms of SZO-based thin films are dominated by ohmic conduction (hoping conduction) and Frenkel--Poole emission for the low resistance state (LRS) and the high resistance state (HRS), respectively. The turn-on process might be attributed to the formation of conducting filaments consisting of oxygen vacancies with the effective barrier height (φB,eff) in the range of 0.10-0.13 eV, whereas the turn-off process might result from thermally assisted oxidation of oxygen vacancies by the Joule heating effect. Furthermore, the introduction of the high valence cation (V5+) in a Zr4+ site of SZO crystalline structure can suppress the formation of oxygen vacancies due to the charge neutrality restriction. Such suppression leads to the changes in the forming voltage, turn-on voltage, HRS resistance, dielectric constant, and φB,eff with vanadium doping concentration up to 0.2 mol%, which is within the solid solubility limit based on our measured lattice constants and Vegard's law. [ABSTRACT FROM AUTHOR]

The use of spin-transfer torque (STT) devices for memory design has been a subject of research since the discovery of the STT on MgO-based magnetic tunnel junctions (MTJs). Recently, MTJ-based computing architectures such as logic-in-memory have been proposed and claim superior energy-delay performance over static CMOS. In this paper, we conduct exhaustive energy-performance analysis of an STT-MTJ-based logic-in-memory (LIM-MTJ) 1-bit full adder and compare it with its corresponding CMOS counterpart. Our results show that the LIM-MTJ circuit has no advantage in energy-performance over its equivalent CMOS designs. We also show that the MTJ-based logic circuit requiring frequent MTJ switching during the operation is hardly power efficient. [ABSTRACT FROM AUTHOR]

Suspended gate field-effect transistors (SG-FETs) with switching gates are interesting as digital logic switches because of their high Ion/Ioff current ratio and their infinite sub-threshold slope. However, the limits of scalability of the SG-FETs are still unclear. This paper investigates two effects that could limit scaling: the dielectric charging and the dielectric roughness. To do so, a surface-potential-based model for suspended gate transistors with a mechanically switching gate is presented and validated using experimental data. Devices fabricated in a standard complimentary metal-oxide-semiconductor process are used for the model assessment. The model reproduces the effect of a fixed charge and the effect of a nonideal contact of the gate after pull-in. We show that, at the device dimensions required to follow the International Technology Roadmap for Semiconductors, these effects will be critical. [ABSTRACT FROM AUTHOR]

In this paper, a nonlinear model of microwave power AlGaAs/InGaAs pseudomorphic high-electron mobility transistors (pHEMTs) for switch circuit applications is presented. The symmetrical property that allows for the interchange of the drain and the source is emphasized in the characteristic equations, preserving differentiable features to any orders for the entire bias range. Moreover, the subthreshold voltage, the gate leakage current, and the charge conservation for pHEMT device modeling are included for completeness. The model is validated by being used for a single-pole-single-throw switching circuit in a commercial simulation environment, and the harmonic and two-tone intermodulation distortion predictions (at both ON and OFF states) are examined. The measurement data show quite good agreement with the simulation results, demonstrating the effectiveness of the proposed model. [ABSTRACT FROM AUTHOR]

A high-isolation high-linearity GaAs pseudomorphic high-electron mobility transistor single-pole-double-throw micro-wave switch was developed using a tunable field-plate (FP) bias voltage technology. In this paper, a piece of FP metal was deposited between 0.15-μm-long gate and drain terminals. An extra FP-induced depletion region was generated to suppress the harmonics of switching associated with OFF-state operation. When switching into the ON-state, the FP switch is associated with an insertion loss similar to that of the standard switch below 6 GHz. However, the isolation performance can be enhanced by 10 dB using an FP technology, which reduces the OFF-state capacitance that is produced by the extra FP-induced depletion region. The FP provides an additional mechanism to suppress the power of the second-and third-order harmonics in the OFF-state with slight ON-state insertion-loss degradation. [ABSTRACT FROM AUTHOR]

This paper addresses the numerical modeling of re- set programming in NiO-based resistive-switching memory. In our model, we simulate electrical conduction and heating in the conductive filament (CF), which controls the resistance of the low resistive (or set) state, accounting for CF thermal-activated dissolution. Employing CF electrical and thermal parameters, which were previously characterized on our NiO-based samples, our calculations are shown to match experimental reset and retention characteristics. Simulations show that reset transition is self-accelerated as a consequence of a positive feedback between the thermal dissolution of the CF and local Joule heating in the CF bottleneck, which can account for the abrupt resistance transition. in experimental data. Finally, the model is used to investigate the reduction of the reset current, which is needed for device application. [ABSTRACT FROM AUTHOR]

A novel solid-electrolyte nonvolatile switch that we previously developed for programmable large-scale-integration circuits turns on or off when a conducting Cu budge is formed or dissolved in the solid electrolyte. Cu+ ion migration and an electrochemical reaction are involved in the switching process. For logic applications, we need to adjust its turn-on voltage (VON), which was too small to maintain the conductance state during logic operations. In this paper, we clarified that VON is mainly affected by the rate of Cu+ ion migration in the solid electrolyte. Considering the relationship between the migration rate and VON, we replaced the former electrolyte, Cu2-αS, with Ta2O5, which enabled us to appropriately adjust VON with a smaller Cu+ ion diffusion coefficient. [ABSTRACT FROM AUTHOR]

The SiC trenched-and-implanted vertical junction field-effect transistor (TI-VJFET) is an excellent device for power switching applications, but its on-resistance needs to be further reduced to suppress ON-state power loss. In this paper, we used small cell pitch size and high channel/drift layer doping concentration to achieve low on-resistance. Advanced fabrication processes, such as Bosch process trench etching, self-aligned Ni silicide, and self-aligned gate overlay were implemented to support such an aggressive design. Normally on 4H-SiC TI-VJFETs of various channel-opening dimensions have been designed and fabricated based on a 12 μm, 1.8 x 1016 cm3 doped drift layer. Record high performance TI-VJFETs have been achieved and will be reported. Other SiC VJFET structures under active research are reviewed and compared to TI-VJFET. Without the need for epi-regrowth or stringent lithography alignment, TI-VJFET has the advantage of a less demanding fabrication process. In addition, its high current density, adjustable channel width and low gate resistance make TI-VJFET an excellent device for fast power switching applications. [ABSTRACT FROM AUTHOR]

This paper presents advanced 4H-SiC high-voltage Schottky rectifiers with improved performance when compared to conventional 4H-SiC Schottky rectifiers. Two types of 4H-SiC junction barrier Schottky (JBS) rectifiers have been explored. These rectifiers offer Schottky-like ON-state and fast switching characteristics, while their OFF-state characteristics have a low leakage current similar to that of the PiN junction rectifier. Planar 4H-SiC JBS rectifiers, with more than 1-kV blocking capability and orders of magnitude lower reverse leakage current than that of conventional SiC Schottky rectifiers, have been demonstrated. In addition, a novel device structure, called lateral channel JBS rectifier, was designed and experimentally demonstrated in 4H-SiC with up to 1.5-kV blocking capability and pinlike reverse characteristics. [ABSTRACT FROM AUTHOR]

Ten-kilovolt SiC MOSFETs are currently under development by a number of organizations in the United States, with the aim of enabling their applications in high-voltage high-frequency power conversions. The aim of this paper is to obtain the key device characteristics of SiC MOSFETs so that their realistic application prospect can be provided. In particular, the emphasis is on obtaining their losses in various operation conditions from the extensive characterization study and a proposed behavioral SPICE model. Using the validated MOSFET SPICE model, a 20-kHz 370-W dc/dc boost converter based on a 10-kV 4H-SiC DMOSFET and diodes is designed and experimentally demonstrated. In the steady state of the boost converter, the total power loss in the 15.45-mmé SiC MOSFET is 23.6 W for the input power of 428 W. The characterization study of the experimental SiC MOSFET and the experiment of the SiC MOSFET-based boost converter indicate that the turn-on losses of SiC MOSFETs are the dominant factors in determining their maximum operation frequency in hard-switched circuits with conventional thermal management. Replacing a 10-kV SiC PiN diode with a 10.kV SiC JBS diode as a boost diode and using a small external gate resistor, the turn-on loss of the SiC MOSFET can be reduced, and the 10-kV 5-A SiC MOSFET-based boost converter is predicted to be capable of a 20-kHz operation with a 5-kV dc output voltage and a 1.25-kW output power by the PSpice simulation with the MOSFET model. The low losses and fast switching speed of 10-kV SiC MOSFETs shown in the characterization study and the preliminary demonstration of the boost converter make them attractive in high-frequency high-voltage power-conversion applications. [ABSTRACT FROM AUTHOR]

Technology scaling has entered a new era, where chip performance is constrained by power dissipation. Power limits vary with the application domain; however, they dictate the choices of technology and architecture and necessitate implementation techniques that tradeoff performance for power savings. This paper examines technology options in the power-limited-scaling regime and reviews sensitivity-based analysis that can be used for the optimal selection of optimal architectures and circuit implementations to achieve the best performance under power constraints. These tradeoffs are examined in the context of power minimization at the technology, circuit, logic, and architecture levels, both at the design and run times. [ABSTRACT FROM AUTHOR]

In this paper, novel channel and source/drain profile engineering schemes are proposed for sub-50-nm bulk CMOS applications. This device, referred to as the silicon-on-depletion layer FET (SODEL FET), has the depletion layer beneath the channel region, which works as an insulator like a buried oxide in a silicon-on-insulator MOSFET. Thanks to this channel structure, junction capacitance (Cj) has been reduced in SODEL FET, i.e., Cj (area) was ∼ 0.73 fF/ μm2 both in SODEL nFET and pFET at Vbias 0.0 V. The body effect coefficient γ is also reduced to less than 0.02 V1/2. Nevertheless, current drives of 886 μA/ μm (Ioff = 15 nA/μm) in nFET and -320 μA/ μm (Ioff= 10 nA/μm) in pFET have been achieved in 70-nm gate length SODEL CMOS with |Vdd| = 1.2 V. New circuit design schemes are also proposed for high-performance and low-power CMOS applications using the combination of SODEL FETs and bulk FETs on the same chip for 90-nm-node generation and beyond. [ABSTRACT FROM AUTHOR]

For the switching performance of low-voltage (LV) power MOSFETs, the gate-drain charge density (Qgd) is an important parameter. The so-called figure-of-merit, which is defined as the product of the specific on-resistance (Rds,on) and Qgd is commonly used for quantifying the switching performance for a specified off-state breakdown voltage (BVds). In this paper, we analyzed the switching behavior in power trench MOSFETs by using experiments and simulations, focusing on the charge density Qgd . The results of this analysis can be used for further optimization of these devices. The results show that the Qgd can be split into three charge contributions: accumulation, depletion, and inversion charge. It is shown that the inversion charge is located mainly underneath the trench bottom. The accumulation and depletion charge contribute each about 45% in conventional LV trench MOSFETs and can be reduced by using a thick bottom oxide in a shallow trench gate just extending in the drift region. Further, we derived an analytical model for calculating the Qgd, that takes into account the geometry dependence. [ABSTRACT FROM AUTHOR]

An avalanche generation phenomenon has a large influence on turn-off switching loss and reverse-biased safe operating area of high-voltage insulated gate bipolar transistors (IGBTs). The purpose of this paper is to clarify the correlation between the avalanche multiplication phenomenon and the turn-off characteristics. We introduce a turn-off switching analytical model of IGBTs that considers the avalanche multiplication effect. It is concluded that the criterion of dynamic avalanche depends on the gate resistance. In the case of 4.5-kV IGBTs, the gate resistance of more than 200 &Ohm; · cm² is needed to suppress the dynamic avalanche generation under a clumped inductive load circuit. On the contrary, the turn-off switching loss increases in the case that the gate resistance RG is increased to more than approximately 100 &Ohm; · cm². Theses results show that to realize low turn-off switching loss, it is necessary to ensure that the gate resistance is below a constant value, such as 100 &Ohm; · cm². However, at high current density, such as 80 A/cm², the dynamic avalanche will generate under such small gate resistance condition. Therefore, it is important to develop IGBTs without destruction even under the condition of dynamic avalanche generation. [ABSTRACT FROM AUTHOR]