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Low 1/f noise, low-dropout (LDO) regulators are becoming critical for the supply regulation of deep-submicron analog baseband and RF system-on-chip designs. A low-noise, high accuracy LDO regulator (LN-LDO) utilizing a chopper stabilized error amplifier is presented. In order to achieve fast response during load transients, a current-mode feedback amplifier (CFA) is designed as a second stage driving the regulation FET. In order to reduce clock feed-through and 1/f noise accumulation at the chopping frequency, a first-order digital [SIGMA][DELTA] noise-shaper is used for chopping clock spectral spreading. With up to 1 MHz noise-shaped modulation clock, the LN-LDO achieves a noise spectral density of 32 nV/ [square root of Hz] and a PSR of 38 dB at 100 kHz. The proposed LDO is shown to reduce the phase noise of an integrated 32 MHz temperature compensated crystal oscillator (TCXO) at 10 kHz offset by 15 dB. Due to reduced 1/f noise requirements, the error amplifier silicon area is reduced by 75%, and the overall regulator area is reduced by 50% with respect to an equivalent noise static regulator. The current-mode feedback second stage buffer reduces regulator settling time by 60% in comparison to an equivalent power consumption voltage mode buffer, achieving 0.6 [micro]s settling time for a 25-mA load step. The LN-LDO is designed and fabricated on a 0.25 [micro]m CMOS process with five layers of metal, occupying 0.88 [mm.sup.2]. Index Terms--Chopper stabilization, current feedback amplifier, low-dropout regulators, power supply rejection.

Systematic design of low-dropout-regulator (LDO) regulated low-phase-noise LC-tank voltage controlled oscillators (VCOs) is presented. Low-frequency sensitivity profile of power supply induced phase noise of a typical cross-coupled LC-tank VCO is investigated. The relationship between frequency pushing and power supply-induced phase noise is derived. Systematic codesign of VCO sensitivity to low-frequency supply noise with respect to an LDO output noise and power supply rejection profile is introduced. To demonstrate the design approach experimentally, two 2.4-GHz LC-tank VCOs with pMOS and nMOS switching devices powered by PFET LDOs are designed and fabricated on an 0.18-ftm, 7-layer metal CMOS process. By using an integrated LDO, it is shown that the VCO phase-noise sensitivity to low frequency improves by 55 dB at 100-kHz offset. Index Terms--DC-DC power conversion, voltage regulators, phase noise, power supply rejection (PSR), voltage-controlled oscillators (VCOs).

The design and analysis of a fully integrated multistage interleaved synchronous buck dc-dc converter with on-chip filter inductor and capacitor is presented. The dc-dc converter is designed and fabricated in 0.18 [micro]m SiGe RFBiCMOS process technology and generates 1.5 V-2.0 V programmable output voltage supporting a maximum output current of 200 mA. High switching frequency of 45 MHz, multiphase interleaved operation, and fast hysteretic controller reduce the filter inductor and capacitor sizes by two orders of magnitude compared to state-of-the-art converters and enable a fully integrated converter. The fully integrated interleaved converter does not require off-chip decoupling and filtering and enables direct battery connection for integrated applications. This design is the first reported fully integrated multistage interleaved, zero voltage switching synchronous buck converter with monolithic output filters. The fully integrated buck regulator achieves 64% efficiency while providing an output current of 200 mA. Index Terms--Fully integrated switched-mode (SM) dc-dc converter, interleaved synchronous buck converter, zero voltage switching (ZVS).

[SIGMA][DELTA] frequency discriminators ([SIGMA][DELTA]AFDs) convert instantaneous frequency deviations of a carrier signal to digital. They are used for decoding narrowband phase or frequency modulated signals in communication receivers, self calibration of RF frequency synthesizers and in digital phase locked loops. In this paper, the impact of reference (sampling) clock phase noise on a [SIGMA][DELTA]AFD's spurious-free dynamic range (SFDR) is derived. It is shown that for [SIGMA][DELTA]FDs with jittered sampling clock, in addition to FM sidebands, a high baseband tonal content is generated degrading overall SFDR. The reference clock phase noise impact is derived mathematically, and two commonly used [SIGMA][DELTA]FDs circuits are designed and implemented to verify the results experimentally. Experimental results are shown to match the theoretical prediction of SFDR within 3 dB. Index Terms--Clock Jitter, frequency discriminators, [SIGMA][DELTA]modulators.

Current feedback amplifiers (CFAs) provide fast response and high slew rate with Class-AB operation. Fast response, low-dropout regulators (LDRs) are critical for supply regulation of deep-submicron analog baseband and RF system-on-chip designs. An LDR with an CFA-based second stage driving the regulation field-effect transistor is presented. The low dropout (LDO) achieves an output noise spectral density of 67.7 nV/[square root of Hz], and PSR of 38 dB, both at 100 kHz. In comparison to an equivalent power consumption voltage feedback buffer LDO, the proposed CFA-based LDO settles 60% faster, achieving 0.6-[micro]s settling time for a 25-mA load step. The LDO with CFA buffer is designed and fabricated on a 0.25-[micro]m CMOS process with five layers of metal, occupying 0.23-[mm.sup.2] silicon area. Index Terms--Current feedback amplifier (CFA), low-dropout regulators (LDRs), power supply rejection.

Two integrated polar supply-modulated class E and F power amplifiers (PAs) in 0.18-[micro]m SiGe BiCMOS process are presented. The amplifiers are used to transmit GSM-EDGE signals with an envelope dynamic range of 11 dB and a frequency range of 880-915 MHz. The amplifiers use switch-mode dc--dc buck converters for supply modulation, where sigma--delta ([SUMMATION][DELTA]M), delta ([DELTA]M), and pulsewidth modulation are used to modulate the PA amplitude signal. A framework has been developed for comparing the three switching techniques for EDGE implementation. The measurement results show that [DELTA]M gives the highest efficiency and lowest adjacent channel power, providing class E and F PA efficiencies of 33% and 31%, respectively, at maximum EDGE output power. The corresponding class E and F finearized amplifiers' output spectra at 400-kHz offset are -54 and -57 dBc, respectively. Index Terms--EDGE, polar modulation, power amplifiers (PAs), switching amplifiers. Digital Object Identifier 10.1109/TMTT.2007.895407

Pulsewidth modulation (PWM) and sigma-delta modulation (SDM) have been used in several high linearity, high accuracy power delivery applications such as dc-dc power converters, audio, and radio frequency power amplifiers and data converters. While PWM can generate high linearity signals with high efficiency, it suffers from discrete tonal output spectrums. SDM, on the other hand, can generate high linearity output spectrums with shaped quantization noise spectrums and lower efficiencies due to oversampling requirements. In this paper we present a particular class of carrier frequency modulated PWM (CFMPWM), which spreads the tonal content of regular PWM uniformly in frequency and reduces the baseband noise with respect to SDM by up to 15 dB. The new modulation scheme preserves the high efficiency properties of PWM. An approximate method to estimate the spectrum of CFMPWM signals with both deterministic and random modulation is also presented. Simulation results and experimental data are reported to analyze the spectral spreading properties of the proposed CFMPWM scheme. Index Terms--Carrier frequency modulated pulsewidth modulation (CFMPWM), electromagnetic interference (EMI), pulse density modulation (PDM), sigma--delta modulation (SDM).

A bandpass (BP) sigma-delta modulator ([SIGMA][DELTA]M)-based direct digital frequency synthesizer (DDS) architecture is presented. The DDS output is passed through a single-bit, second-order BP[SIGMA][DELTA]M, shaping quantization noise out of the signal band. The single-bit BP[SIGMA][DELTA]M is then injection locked to an LC-tank oscillator, which provides a tracking BP filter response within its locking range, suppressing the BP[SIGMA][DELTA]M out of band quantization noise. The instantaneous digital frequency control word input of the DDS is used to tune the noise shaper center frequency, achieving up to 20% tuning range around the fundamental. The BP[SIGMA][DELTA]M-based synthesizer is fabricated in a 0.25-[micro]m digital CMOS process with four layers of metal. With a second-order BP noise shaper and a 44-MHz LC tank oscillator, an SFDR of 73 dB at a 2-MHz bandwidth and phase noise lower than--105 dBc/Hz at a 10-kHz offset is achieved. Index Terms--Direct digital frequency synthesizer (DDS), injection locking, oscillator, phase noise, sigma-delta modulator ([SIGMA][DELTA]M).

Frequency synthesizers are fundamental building blocks in radio frequency, communications, and analog signal processing for generating high accuracy oscillatory signals. In general, the frequency synthesizer is the most sensitive block in the system since many of the signal processing elements such as clock, filters, and up/down converters depend on the synthesizer generating a clean sinusoidal signal at the given frequency. For radiation environments, the response and the sensitivity of the phase-lock loop (PLL) and the synthesizer block is very critical. This paper examines the effect of single events (SEE) radiation on the PLL locking and steady state response. The PLL circuits operating at 2.4 GHZ were designed and fabricated using a 0.13 ~m CMOS process This paper presents the experimental and simulations results on the SEE radiation effects on the PLL. Index Terms--Hold-in range, lock-in range, phase locked loop (PLL), radiation effects, single event effect (SEE), VCO.

Wideband low-noise [SIGMA][DELTA] fractional-N synthesizers pose several design challenges due to the nonlinear time-varying nature of synthesizer building blocks such as phase frequency detectors (PFDs), charge pump, and frequency dividers. Loop nonlinearities can increase close-in phase noise and enhance spurious tones due to intermodulation of high-frequency quantization noise and tonal content; therefore, an accurate simulation model is critical for successful implementation of loop parameters and bandwidth widening techniques. In this paper a closed-loop nonlinear simulation model for fractional-N synthesizers is presented. Inherent nonuniform sampling of the PFD is modeled through an event-driven dual-iteration-based technique. The proposed technique generates a vector of piecewise linear time--voltage pairs, defining the voltage-controlled oscillator (VCO) control voltage. This method also lends itself to modeling of cyclostationary thermal and flicker noise generated by time-varying charge-pump current pulses. A flexible third-order [SIGMA][DELTA] modulated RF synthesizer core with integrated loop filter and LC-tank VCO is designed and fabricated in 0.13-[micro]m CMOS process in order to validate the technique experimentally. The proposed modeling technique was able to predict in-band spur power levels with 1.8-dB accuracy, and spur frequency offsets with lower than 400-Hz accuracy with several programmable nonidealities enabled. Index Terms--Fractional.N frequency synthesizers, phase-locked loops (PLLs), phase noise, quantization noise, sigma--delta modulation, spurs.

A mixed-signal adaptive ripple canceller for reducing switching noise and spurious emissions in switching regulators is presented. The proposed mixed-signal ripple suppression technique tracks and cancels the switching noise by utilizing two schemes: A primary mixed-signal adaptive ripple canceller that provides large signal ripple cancellation up to 20 dB, and an auxiliary linear amplifier-based ripple canceller that minimizes the residual ripple content, achieving a combined ripple rejection of 24 dB. Proposed approach operates without the need for external components, reducing overall printed circuit board area without loss of efficiency. The adaptive ripple canceller is designed and fabricated in a 250 nm CMOS process with four levels of metal. The ripple-canceller is integrated with an on-chip buck regulator to characterize its rejection effectiveness. The ripple canceller can also be utilized as a stand-alone ripple cleaner module with an external commercial-off-the-shelf (COTS) switching regulator. The proposed ripple canceller can track and cancel power supply ripple up to 1 MHz with 24 dB rejection and reduces ripple content up to fourth harmonic by at least 20 dB while supporting dc loads up to 1 A and ripple currents up to 350 mApk-pk. The proposed approach achieves 30% lower quiescent current than using a linear low-dropout regulator without the need for any external components. [ABSTRACT FROM AUTHOR]

High power supply rejection (PSR) with a wide rejection frequency band is becoming a critical requirement in linear low-dropout regulators (LDOs) used in complex systems-on-chip (SOCs). Typical LDOs achieve higher PSR within their loop-bandwidth; however, their supply rejection performance degrades with reduced loop-gain outside their loop-bandwidth. Typical LDOs with external filtering capacitors may also have spectral peaking in their PSR response, causing excess system-level supply noise. This work presents an LDO design approach, which achieves a PSR of higher than 68 dB up to 2 MHz frequency and over a wide range of loads up to 250 mA. The wide PSR bandwidth is achieved using a current-mode feedforward ripple canceller (CFFRC) amplifier which provides up to 25 dB of PSR improvement. The feedforward path gain is inherently matched to the forward gain of the LDO, not requiring calibration. The LDO has a fast load transient response with a recovery time of 6.1 $\mu \text {s}$ and has a quiescent current of 5.6 $\mu \text {A}$. For a full load transition, the LDO achieves settling with overshoot and undershoot voltages below 27.6 and 36.36 mV, respectively. The LDO is designed and fabricated in a 180 nm bipolar/CMOS/DMOS (BCD) technology. The CFFRC amplifier helps to achieve low quiescent power due to its inherent current mode nature, eliminating the need for supply ripple summing amplifiers and adaptive biasing. [ABSTRACT FROM AUTHOR]

A wideband hybrid Envelope tracking (ET) modulator utilizing a hysteretic-controlled three-level switching converter (3L-SWC) and a slew-rate enhanced linear amplifier (LA) are presented. In addition to smaller ripple and lower losses of 3L-SWCs, employing the proposed hysteresis control loop results in a higher speed loop and wider bandwidth converter, enabling over 80 MHz of switching frequency. A concurrent sensor circuit monitors and regulates the flying capacitor voltage $V_{\mathrm{ CF}}$ and eliminates the conventionally required calibration loop to control it. The hysteretic-controlled 3L-SWC provides a high percentage of power amplifier (PA) supply load current with lower ripple, reducing the LA high-frequency current and ripple cancellation current, improving the overall system efficiency. A slew-rate enhancement (SRE) circuit is employed in the LA, resulting in slew rate of over 307 V/ $\mu \text{s}$ and bandwidth of over 275 MHz for the LA. The SRE circuit provides a parallel auxiliary current path directly to the gate of the class-AB output stage transistors, speeding-up the charging or discharging of output without modifying the operating point of the remaining LA, while maintaining the quiescent current of the class-AB stage. The supply modulator is fabricated in a 65-nm CMOS process. The measurement results show the tracking of long-term evolution (LTE)-40-MHz envelope with 93% peak efficiency at 1-W output power, while the SRE is disabled. Enabling the SRE, it can track LTE-80-MHz envelope with peak efficiency of 91%. [ABSTRACT FROM AUTHOR]

A fully integrated, point-of-load, low-noise, isolated dc–dc converter for supply regulation of high dynamic range analog and mixed-signal isolated sensor signal-chains is presented. The isolated dc–dc converter utilizes an integrated planar air-core micro-transformer as a coupled-resonator and an isolation barrier, and enables direct connection of low-voltage mixed-signal circuits to higher supply rails for current and voltage sensing. The transformer is driven at its resonant frequency of 100 MHz to achieve maximum power transfer. A mixed-signal perturb-and-observe-based frequency search algorithm is developed to improve maximum power transfer efficiency by 60% across the isolation barrier compared to fixed driving frequency method. The switching ripple at output is reduced by 11 dB utilizing spread spectrum clocking in the driver, and 21 dB using a low-dropout regulator. Conducted and radiated EMI distribution on the IC is measured by a set of proposed ring oscillator-based noise sensors with −68-dBm noise sensitivity. The proposed isolated converter achieves the highest level of integration compared to state-of-the-art integrated isolated converters, and provides 50-V on-chip junction isolation using standard CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents an output external capacitor-less, fully integrated, fast settling NMOS low-dropout (LDO) regulator with adaptively biased error amplifier (EA) for system-on-chip core applications. The adaptive biasing technique increases both loop bandwidth and slew-rate of the LDO by 100% at full load condition without changing no-load quiescent current. Direct feedback to gate-to-source voltage of the NMOS regulation FET provides fast load transient response. The proposed LDO employs a cross-coupled common-gate input based EA, with transconductance boosting, achieving twice unity-gain bandwidth in comparison to a typical folded-cascode common-source input stage. Low output impedance of NMOS regulation stage and low input impedance of the EA reduce load dependent stability issue. The proposed regulator is designed and fabricated in a 0.18- $\mu \text{m}$ CMOS technology with die-area of 0.21 mm2. The LDO generates a regulated output voltage of 1.4–1.6 V from an input voltage of 1.6–1.8 V, consumes 133 $\mu \text{A}$ quiescent current, and supports 0 pF to 50 pF load capacitance. Measured results show 166 mV undershoot with 19 ns settling time for a load step from 9 mA to 40 mA in 350 ps edge-time for zero-load capacitance. After using adaptive biasing, the settling time is reduced by 37% and 36% for 0 pF and 50 pF load, respectively. [ABSTRACT FROM AUTHOR]

Supply regulation using low quiescent current linear regulators helps in extending the battery life of power aware applications with very long standby time. A 1.24 $\mu \text{A}$ quiescent current NMOS low dropout (LDO) that uses a hybrid bias current generator (HBCG) which boosts the bias current dynamically and adaptively to improve the transient response is presented in this paper. A bias-current scalable error amplifier with an on-demand pull-up/pull-down buffer drives the NMOS pass device. The error amplifier is powered with an integrated dynamic frequency charge pump to ensure low dropout voltage. A low-power relaxation oscillator (LPRO) generates the charge pump clocks. A novel switched-capacitor pole tracking (SCPT) compensation scheme is proposed to ensure stability up to maximum load current of 150 mA with a low-ESR 1 $\mu \text{F}$ output capacitor. Designed in a 0.25 $\mu \text{m}$ CMOS process, the LDO has an output voltage range of 1–3 V, a dropout voltage of 240 mV, and a core area of 0.11 mm2. [ABSTRACT FROM AUTHOR]

A radiation-tolerant digital multiphase current-mode hysteretic point-of-load regulator fabricated on a commercial 180-nm CMOS process is presented. Experiments and simulations are used to demonstrate its single-event immunity and its total-dose tolerance over 100 krad(Si). Key electrical performance parameters are: 5-V input, 0.8–3.3 V output, 10-A load current, 93% peak efficiency, four-phase hysteretic quasi-current-mode buck converter with ±1.5% frequency synchronization, ±3.6% current sharing error, and 1% ripple. [ABSTRACT FROM AUTHOR]

An integrated reconfigurable CMOS quasi-circulator operating at 2.4 GHz is presented. A passive structure delivers transmit power amplifier (PA) output signal to the differential low-noise amplifier (LNA) input as a common-mode signal and simultaneously delivers received signal as a differential-mode signal at the LNA input. The leakage of the PA output signal at the LNA input is reduced in two steps. First, the use of a reconfigurable impedance matching circuit, instead of a fixed 50- $\Omega $ resistance reduces the leakage by compensating the antenna impedance mismatch, and improves transmitter–receiver isolation. Second, a reconfigurable summing stage adds amplitude and phase adjusted PA output signal to LNA output to cancel the residual PA output leakage. Measurement results show that the receiver achieves a reduction of 90 dB for a single tone and more than 50 dB for a QPSK modulated 40-MHz bandwidth transmit signal. The receiver gain is more than 10 dB and the noise figure in the receiver path is 4.5 dB. The reconfigurable quasi-circulator along with the receiver LNA is designed and fabricated on a 130-nm CMOS technology. The cancellation circuitry occupies 0.27 mm2 and consumes 30-mW quiescent power, while the total active area of the chip is 1 mm2, and it consumes 65-mW power. [ABSTRACT FROM PUBLISHER]

A four-phase, quasi-current-mode hysteretic buck converter with digital frequency synchronization, online comparator offset-calibration and, digital current-sharing control is presented. The switching frequency of the hysteretic converter is digitally synchronized to the input clock reference with less than ±1.5% error in the switching frequency range of 3–9.5 MHz. The online offset calibration cancels the input-referred offset of the hysteretic comparator and enables ±1.1% voltage regulation accuracy. Maximum current-sharing error of ±3.6% is achieved by a duty-cycle-calibrated delay line-based pulsewidth modulation generator, without affecting the phase synchronization timing sequence. In light-load conditions, individual converter phases can be disabled, and the final stage power converter output stage is segmented for high efficiency. The dc–dc converter achieves 93% peak efficiency for Vi= 2 V and Vo= 1.6 V. [ABSTRACT FROM AUTHOR]

A linear-switch mode hybrid envelope tracking (ET) supply modulator utilizing adaptive biasing and gain enhanced current mirror operational transconductance amplifier (OTA) with class AB output stage in parallel with a switching regulator is presented. In comparison to a conventional OTA design with similar quiescent current consumption, proposed approach improves positive and negative slew rate from 50 to 93.4 V/ \mu \texts and −87 to −152.5 V/ \mu \texts , respectively, dc gain from 45 to 67 dB while consuming same amount of quiescent current. The proposed hybrid supply modulator achieves 83% peak efficiency, power-added efficiency (PAE) of 42.3% at 26.2 dBm for a 10-MHz 7.24-dB peak-to-average power ratio (PAPR) long-term evolution (LTE) signal and improves PAE by 8% at 6 dB back off from 26.2-dBm power amplifier (PA) output power with respect to fixed supply. With a 10-MHz 7.24-dB PAPR quadrature-phase shift keying LTE signal the ET PA system achieves adjacent channel leakage ratio (ACLR) of −37.7 dBc and error vector magnitude (EVM) of 4.5% at 26.2-dBm PA output power, while with a 10-MHz 8.15-dB PAPR 64QAM LTE signal the ET PA system achieves ACLR of −35.6 dBc and EVM of 6% at 26-dBm PA output power without digital predistortion. The proposed supply modulator core circuit occupies 1.1-mm2 die area, and is fabricated in a 0.18- \mu \textm CMOS technology. [ABSTRACT FROM AUTHOR]

A fully integrated digital low-dropout regulator (DLDO) with a fast transient response, providing a regulated supply for system-on-chip (SoC) power management applications is proposed. Wideband operation and fast transient response are achieved through a transient enhanced proportional-integral controller, without compromising the stability of the DLDO at steady-state operation. The transient enhancement stage boosts loop-gain dynamically during load transients. In the gain boosting mode, the DLDO closed-loop bandwidth is increased, resulting in reduced undershoot/overshoot and fast settling. When the output voltage recovers to the desired level, the boost mode operation is disabled. For a load change with a 4-mA/ns slew rate between 10 and 50 mA, utilizing transient enhancement mode reduced the measured undershoot and overshoot by 35% and 17%, respectively. The characterization results show that the transient enhancement mode can reduce the settling time from 500 to 250 ns for a 10–50-mA load current change. The proposed DLDO operates with an input voltage ranging from 0.84 to 1.24 V, and output voltage ranging from 0.6 to 1 V. The maximum output current of the DLDO is 50 mA and the DLDO achieves a peak current efficiency of 99.2%, with DLDO figure of merit (FOM2) of 63.25 ps. The DLDO prototype chip is fabricated on a 0.13- \mu \textm CMOS technology and occupies a 0.0631-mm2 die area. [ABSTRACT FROM PUBLISHER]

Low-noise linear regulators are critical for power supply regulation of noise-sensitive circuits, such as ADCs, phase-locked loops, and other mixed-signal/RF system-on-a-chip designs. A low-noise low-dropout (LN-LDO) regulator using switched-RC bandgap reference and a multiloop, unconditionally stable error amplifier for output capacitorless operation is presented in this paper. A sample-and-hold switched-RC filter is developed to reduce the noise of the bandgap reference and drain-side modulated current-mode chopping technique is proposed to reduce the flicker (1/f) noise of the error amplifier. A switched capacitor notch filter is utilized to filter out the residual chopping ripple of the error amplifier. Thermal noise of the current reference circuit which is significant at such low noise levels is also reduced by using a low-area penalty passive RC filter. These techniques reduce the total integrated output noise of the LDO in the 10 Hz to 100 kHz band from $95.3\;\mu {{\rm{V}}_{{\rm{RMS}}}}$ down to $14.8\;\mu {{\rm{V}}_{{\rm{RMS}}}} . The LDO delivers a maximum load current of 100 mA with a dropout voltage of 230 mV and a quiescent current consumption of 40\;\mu \rmA . It achieves a power supply rejection of 50 dB at 10 kHz for a programmable output voltage range of 1–3.3 V. Fabricated in a 0.25\;\mu \rmm CMOS process, the LDO core occupies an area of 0.18 mm2. [ABSTRACT FROM AUTHOR]

Efficient current, voltage, and power sensing are critical blocks for power management, switching regulators, maximum power point tracking (MPPT) circuit, and motor control. This paper presents a standard CMOS and low-power current-to-digital converter (IDC) that senses the current flowing at high-voltage nodes. The proposed sensor uses a CMOS-switched capacitor circuit to sense a dc–dc converter output current and gives digital output without an analog-to-digital converter (ADC), or the need for high-voltage technologies. Compared to the resistor-based current-sensing methods that require current-to-voltage circuit, gain block, and an ADC converter, the proposed sensor is a low-power integrated circuit that achieves high resolution, lower complexity, and lower power consumption. The IDC circuit is fabricated on a 5 V, 0.7 μm, and three metal CMOS technology and occupied less than 10% area (1 mm2 area) compared to other sensors. It consumes 18 mW that is less than 40% power consumed by other sensors, and its current measurement error is below 0.4%. The proposed IDC circuit has been characterized as standalone and with a boost dc–dc regulator and MPPT for photovoltaic systems. [ABSTRACT FROM AUTHOR]

Digital low-dropout (DLDO) regulators are gaining attention due to their design scalability for distributed multiple voltage domain applications required in state-of-the-art system-on-chips. Due to the discrete nature of the output current and the discrete-time control loop, the steady-state response of the DLDO has inherent output voltage ripple. A hybrid DLDO (HD-LDO) with fast response and stable operation across a wide load range while reducing the output voltage ripple is proposed. In the HD-LDO, a DLDO and a low current analog ripple cancellation amplifier (RCA) work in parallel. The output dc of the RCA is sensed by a 2-bit analog-to-digital converter, and the digitized linear stage current is fed into the DLDO as an error signal. During load transients, a gear-shift controller enables fast transient response using dynamic load estimation. The DLDO suppresses the output dc of the RCA within its current resolution. With this arrangement, a majority of the dc load current is provided by the DLDO and the RCA supplies ripple cancellation current. The HD-LDO is designed and fabricated in a 180-nm CMOS technology, and occupies 0.697 mm2 of the die area. The HD-LDO operates with an input voltage range of 1.43-2.0 V and an output voltage range of 1.0-1.57 V. At 100-mA load current, the HD-LDO achieves a current peak efficiency of 99.11% and a settling time of 15 clock periods with a 0.5-MHz clock for a current switching between 10 and 90 mA. The RCA suppresses fundamental, second, and third harmonics of the switching frequency by 13.7, 13.3, and 14.1 dB, respectively. [ABSTRACT FROM AUTHOR]

Testing and calibration constitute a major part of the overall manufacturing cost of microelectromechanical system (MEMS) devices. A physical-stimulus-free built-in-self-test (BIST) integrated circuit (IC) design characterizing the sensitivity of capacitive MEMS accelerometers is presented. The BIST circuitry can extract the amplitude and phase response of the acceleration sensor’s mechanics under electrical excitation within 0.55% of error with respect to its mechanical sensitivity under physical stimulus. Sensitivity characterization is performed using a low computational complexity multi-variate linear regression model. The BIST circuitry maximizes the use of existing analog and mixed signal readout signal chain and the host processor core, without the need for computationally expensive fast Fourier transform (FFT)-based approaches. The BIST IC is designed and fabricated using the 0.18- \mu \textm CMOS technology. The sensor analog front-end and BIST circuitry is integrated with a three axis, low- g capacitive MEMS accelerometer in a single hermetically sealed package. The BIST circuitry occupies 0.3 mm ^{ { {2}}} with a total readout IC area of 1 mm ^{ { {2}}}$ , and consumes 8.9 mW during self-test operation. [ABSTRACT FROM PUBLISHER]

Failure due to aging mechanisms is an important concern for RF circuits. In-field aging results in continuous degradation of circuit performances before they cause catastrophic failures. In this regard, the lifetime of RF/analog circuits, which is defined as the point where at least one specification fails, is determined not only by aging at the device level but also by the slack in the specifications, process variations, and the stress conditions on each of the devices. In this paper, we present a methodology for analyzing, monitoring, and recovering performance degradation in cross-coupled \textLC oscillators caused by aging mechanisms in MOSFET devices. At design time, we identify reliability hot spots and concentrate our efforts on improving these components. We also identify the circuit variable that is easy to measure but highly correlated to the performance of the primary circuit and codesign the monitoring and reconfiguration mechanism along with the primary circuit. Experimental results with a fabricated oscillator chip show that the phase noise of the oscillator degraded by 1.5 dB over ten days (240 h) of accelerated stress conditions, and this loss can be recovered by the proposed mitigation scheme. [ABSTRACT FROM PUBLISHER]

Failure due to aging mechanisms in CMOS devices is an important concern of RF circuits. Lifetime of analog/RF circuits is defined as the point where at least one specification will fail due to aging effects. In this brief, we present a methodology for analyzing the performance degradation of RF circuits caused by aging mechanisms in MOSFET devices and inductors at design time (presilicon). We identify reliability hotspots and concentrate on these circuit components to enhance the lifetime with low area and no performance impact. [ABSTRACT FROM PUBLISHER]

Several state-of-the-art monitoring and control systems, such as dc motor controllers, power line monitoring and protection systems, instrumentation systems, and battery monitors, require direct digitization of high-voltage (HV) input signals. Analog-to-digital converters (ADCs) that can digitize HV signals require high linearity and low-voltage coefficient capacitors. A built-in self-calibration and digital-trim algorithm correcting static mismatches in capacitive digital-to-analog converter (DAC) used in successive approximation register analog-to-digital converters (SAR ADCs) is proposed. The algorithm uses a dynamic error correction (DEC) capacitor to cancel the static errors occurring in each capacitor of the array as the first step upon power-up and eliminates the need for an extra calibration DAC. Self-trimming is performed digitally during normal ADC operation. The algorithm is implemented on a 14-bit HV input range SAR ADC with integrated DEC capacitors. The IC is fabricated in 0.6- \mu m HV-compliant CMOS process, accepting up to 24V_{\rm pp} differential input signal. The proposed approach achieves 73.32-dB signal-to-noise and distortion ratio, which is an improvement of 12.03 dB after self-calibration at 400-kS/s sampling rate, consuming 90 mW from a ±15 V supply. The calibration circuitry occupies 28% of the capacitor DAC and consumes <15 mW during operation. Measurement results show that this algorithm reduces integral nonlinearity from as high as 7 LSBs down to 1 LSB, and it works even in the presence of larger mismatches exceeding 260 LSBs. Similarly, it reduces differential nonlinearity errors from 10 LSBs down to 1 LSB. The ADC occupies an active area of 9.76 mm ^{2}$ . [ABSTRACT FROM AUTHOR]

An all-digital sliding-mode (ADSM) controlled dc-dc converter, utilizing single-bit oversampled frequency domain digitizers in its feedback path is proposed. Sliding-mode control provides several benefits over the traditional PID control in terms of fast transient response, robustness to parameter and component variations, and low sensitivity to loop disturbances. However, analog implementations of sliding-mode control require several amplifiers in the controller and suffer from process, voltage, and temperature variations. In the proposed approach, the sliding-mode controller (SMC) is implemented digitally; utilizing a first order single-bit ΣΔ frequency to digital converter (ΣΔFDC)-based feedback and reference digitizing ADCs, running at 32-MHz sampling rate. The ADSM regulator achieves 1% settling time in less than 5 μs for a load variation of 600 mA. The SMC uses a high-bandwidth hysteretic differentiator and an integrator to perform the sliding control law in digital domain. The proposed approach overcomes the steady-state error (or dc offset), and band limits the switching frequency, which are the two common problems associated with SMCs. The IC is designed and fabricated on a 0.35-μm CMOS process occupying an active area of 2.72 mm2. [ABSTRACT FROM AUTHOR]

A novel backgate modulation technique alleviating limitations associated with supply-regulated polar transmitters is proposed. The backgate of a partially depleted silicon-on-insulator metal–semiconductor field-effect transistor with a breakdown voltage of 15 V is used to modulate the gain and output power of an RF power amplifier (PA). The high-impedance backgate provides high-efficiency and wide-dynamic-range modulation of PA gain. Measured results at 1.8 GHz demonstrate 16% power-added efficiency improvement at 6-dB backed-off output power, compared with the same RF PA without backgate modulation. [ABSTRACT FROM AUTHOR]

This paper presents a digitally controlled programmable point-of-load regulator for next-generation power systems. A novel digital control scheme was designed to minimize single-event effect (SEE)-induced transient effects. By effectively programming the loop transmission, the POL can trade off transient response time with SET robustness. The IC works with 1 to 5.5 V input voltage, 1–4.5V regulated output voltage, high efficiency (peak efficiency at 94%) and power of up to 5 W. The design was fabricated in the AMI i2t100 0.7 \mum complimentary, metal-oxide semiconductor (CMOS) process and characterized with the Jet Propulsion Laboratory (JPL) pulsed laser system. [ABSTRACT FROM PUBLISHER]

A 10 b opamp-sharing pipeline analog-to-digital (A/D) using current-reuse operational transconductance amplifiers (OTA) with dual nMOS differential inputs is presented. The current-reuse OTA topology facilitates opamp-sharing between all of the consecutive pipeline stages, minimizing power consumption and die area. Analog transistors in the OTA are always biased in saturation ensuring no loss of settling time due to OTA power turn-on delays. The A/D is fabricated in a 0.18-\mum CMOS process and occupies an active die area of 0.7 mm^2. At 50 MS/s, maximum SNDR of 58 dB (ENOB=\ 9.3 b) is achieved with 9.2 mW analog power consumption on a 1.8 V supply. [ABSTRACT FROM AUTHOR]

A dual-channel directional digital hearing aid front end using microelectromechanical-systems microphones, and an adaptive-power analog processing signal chain are presented. The analog front end consists of a double differential amplifier-based capacitance-to-voltage conversion circuit, 40-dB variable gain amplifier (VGA) and a power-scalable continuous time sigma delta analog-to-digital converter (ADC), with 68-dB signal-to-noise ratio dissipating 67 \muW from a 1.2-V supply. The MEMS microphones are fabricated using a standard surface micromachining technology. The VGA and power-scalable ADC are fabricated on a 0.25-\mum complementary metal–oxide semciconductor TSMC process. [ABSTRACT FROM PUBLISHER]

A low-power transceiver for medical implant communication service is presented. The device consists of three subsystems, which perform wake-up signal reception, data-link binary frequency-shift keying (BFSK) reception, and transmission, respectively. A common antenna interface is reused in the three subsystems, reducing circuit complexity and number of external components. Super-regenerative architecture is used for wake-up reception, and gm-boosted common-gate stages are used to optimize receiver (RX) performance with low power consumption. The transmitter employs an all-digital frequency-locked loop to directly drive a class AB power amplifier. The transmitter can alternatively use an injection-locked power oscillator for lower bit rates and power consumption. The integrated circuit is designed and fabricated on a 0.18-\mu\m CMOS process. The wake-up RX achieves a -80-dBm sensitivity for a 50-kb/s signal and a 280-\mu\W dissipation. The BFSK RX achieves a -97-dBm sensitivity for a 75-kb/s signal and a 2-mW power consumption. Finally, the transmitter achieves an output power of -5 dBm for a power consumption of 2.9 mW. [ABSTRACT FROM AUTHOR]

Several wireless biomedical transceivers, including medical implants communication systems (MICSs), require ultra-low-power low-complexity frequency synthesizers. This paper presents an all-digital frequency-locked loop (ADFLL)-based frequency synthesizer with a built-in frequency-shift keying modulator for MICS and industrial–scientific–medical band applications. Unlike all-digital phase-locked loops that rely on a power-hungry time to digital converter, the proposed ADFLL employs a high-resolution single-bit \Sigma \Delta frequency discriminator in the feedback path and a noise-cancelling \Sigma \Delta phase-accumulator-based frequency controller in the reference path, achieving fractional resolution with low power consumption. The loop compensation is implemented digitally using an infinite impulse response filter followed by a digital-intensive current-steering DAC driving a ring-oscillator-based voltage-controlled oscillator. The ADFLL achieves 9.5-Hz frequency resolution, spanning the ISM 400–410-MHz band. A worst case near-integer spur of -\62 dBc and a phase noise of -\83 dBc/Hz at 300-kHz offset are measured. The ADFLL is fabricated on a \0.18-\mu\ m CMOS process, occupying a \ 0.14-mm^2 die area, with a quiescent current consumption of \700~\mu\ A. [ABSTRACT FROM AUTHOR]

A radiation hardened by a design delay-locked loop (DLL) architecture for quadrature phase clock generation in a 133 MHz DDR memory designed on a foundry 0.13 \mum fabrication process is presented. The DLL employs an all-digital architecture, including a hardened digital integrator using error-correction logic. The area and power overhead due to the hardening are 32% and 37%, respectively. Simulation results demonstrate that the all-digital DLL is hardened against single-event transients with no timing impact due to hardening. Layout techniques to make the DLL hardened to multiple bit upsets are also presented. [ABSTRACT FROM AUTHOR]

A reconfigurable 12-b pipeline analog-to-digital converter (ADC) implemented by enabling or disabling MDAC OTAs in parallel is presented. Power scaling is achieved without varying the dc bias conditions of critical analog nodes, reducing design complexity, and allowing an existing design to be rapidly reconfigured for new specifications. The ADC can be designed for optimal power consumption over the entire sampling rate range due to the linear power scaling provided by the parallel OTA approach. The proposed ADC operates over a sampling rate range of 20 MS/s to 40 MS/s with > 62 dB SNDR. The analog power varies linearly from 36 mW at 20 MS/s to 72 mW at 40 MS/s. The ADC was fabricated in 0.18- \mu\m CMOS process and occupies a die area of 1.9 \mm^2. [ABSTRACT FROM PUBLISHER]

A 6 GHz Type-I fractional-N PLL with noise-cancelling DAC and discrete-time sample and hold loop-filter is presented. The 1 MHz bandwidth PLL utilizes an inherently linear PFD and noise-cancelling charge-pump DAC circuit to reduce quantization noise by more than 25 dB. The worst case near-integer in-band spur is measured at -61 dBc and the integrated RMS phase error is -42 dBc. The measured in-band phase noise at 300 kHz offset from the 6.12 GHz carrier is -102 dBc/Hz and out-of-band phase noise at 3 MHz offset is -130 dBc/Hz. The PLL loop settling time for an accuracy of 0.01 ppm and a frequency step of 60 MHz is less than 11 μs. The synthesizer is fabricated in a 0.18 μm CMOS technology with 6 metal layers and consumes 26 mA from a 1.8 V power supply. [ABSTRACT FROM AUTHOR]