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A new adiabatic circuit technique called adiabatic differential cascode voltage switch with complementary pass-transistor logic tree (ADCPL) is presented. ADCPL is a dual-rail logic with relatively low gate complexity. It operates from a two-phase nonoverlapping supply clock. Power reduction is achieved by recovering the energy in the recover phase of the supply clock. Energy dissipation comparison with other logic circuits is performed. Simulation shows that for a pipelined ADCPL carry lookahead adder, a power reduction of 50%-70% can be achieved over the static complimentary metal oxide semiconductor case within a practical operation frequency range. The results also show that the lower the operating frequency, the larger the energy savings for an ADCPL circuit. Index Terms--Adiabatic circuit, differential cascode voltage logic, low-power circuit, low-power digital system.

There has been growing interest in single-inductor multiple-output (SIMO) dc-dc converters due to its reduced cost and smaller form factor in comparison with using multiple single-output converters. An application for such a SIMO-based switching converter is to drive multiple LED strings in a multichannel LED display. This paper proposes a quasi-hysteretic finite-state-machine-based digitally controlled single-inductor dual-output buck switching LED driver operating in discontinuous conduction mode (DCM) and extends it to drive multiple outputs. Based on the time-multiplexing control scheme in DCM, a theoretical upper limit of the total number of outputs in a SIMO buck switching LED driver for various backlight LED current values can be derived analytically. The advantages of the proposed SIMO LED driver include reducing the controller design complexity by eliminating loop compensation, driving more LED strings without limited by the maximum LED current rating, performing digital dimming with no additional switches required, and optimization of local bus voltage to compensate for variability of LED forward voltage VF in each individual LED string with smaller power loss. Loosely binned LEDs with larger VF variation can, therefore, be used for reduced LED costs. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) are promising candidates for transistors and interconnects for nanoelectronic circuits. Although CNTs intrinsically have excellent electrical conductivity, the large contact resistance at the interface between CNT and metal hinders its practical application. Here, we show that electrical contact to the CNT is substantially improved using a graphitic interfacial layer catalyzed by a Ni layer. The p-type semiconducting CNT with graphitic contact exhibits high on-state conductance at room temperature and a steep subthreshold swing in a back-gate configuration. We also show contact improvement to the semiconducting CNTs with different capping metals. To study the role of the graphitic interfacial layer in the contact stack, the capping metal and Ni catalyst were selectively removed and replaced with new metal pads deposited by evaporation and without further annealing. Good electrical contact to the semiconducting CNTs was still preserved after the new metal replacement, indicating that the contact improvement is attributed to the presence of the graphitic interfacial layer. [ABSTRACT FROM PUBLISHER]

There has been a strong demand for developing an ultradense and low-power nonvolatile memory technology. In this paper, we present a carbon-based resistive random access memory device with a carbon nanotube (CNT) electrode. An amorphous carbon layer is sandwiched between the fast-diffusing top metal electrode and the bottom CNT electrode, exhibiting a bipolar switching behavior. The use of the CNT electrode can substantially reduce the size of the active device area. We also demonstrate a carbon-based complementary resistive switch (CRS) consisting of two back-to-back connected memory cells, providing a route to reduce the sneak current in the cross-point memory. The bit information of the CRS cell is stored in a high-resistance state, thus reducing the power consumption of the CRS memory cell. This paper provides valuable early data on the effect of electrode size scaling down to nanometer size. [ABSTRACT FROM PUBLISHER]

Kinetic inductance is an important property of carbon nanotubes (CNTs) in high-frequency applications. However, disagreements exist in whether the kinetic inductance of CNTs is present in the diffusive transport regime. In this paper, we fabricated the horizontally aligned multiwalled nanotube (MWNT) arrays on silicon substrates and investigated the inductance properties of the MWNT arrays with different lengths using direct current and radio frequency characterizations. The experimental results show that the electron transport in the CNT arrays is diffusive and that the value of the kinetic inductance is proportional to the length of the CNT arrays. We have experimentally validated that the kinetic inductance theory is applicable to CNTs in the diffusive transport regime. This paper could quell the existing disagreements about the kinetic inductance and provide insights to the potential applications of CNTs as interconnects and on-chip inductors. [ABSTRACT FROM AUTHOR]

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications. [ABSTRACT FROM AUTHOR]

Gas identification represents a big challenge for pattern recognition systems due to several particular problems such as nonselectivity and drift. The purpose of this paper is twofold: 1) to compare the accuracy of a range of advanced and classical pattern recognition algorithms for gas identification for the in. house sensor array signals and 2) to propose a gas identification ensemble machine (GIEM), which combines various gas identification algorithms, to obtain a unified decision with improved accuracy. An integrated sensor array has been designed with the aim of identifying combustion gases. The classification accuracy of different density models is compared with several neural network architectures. On the gas sensors data used in this paper, Gaussian mixture models achieved the best performance with higher than 94% accuracy. A committee machine is implemented by assembling the outputs of these gas identification algorithms through advanced voting machines using a weighting and classification confidence function. Experiments on real sensors' data proved the effectiveness of the system with an improved accuracy over the individual classifiers. An average performance of 97% was achieved using the proposed committee machine. [ABSTRACT FROM AUTHOR]

The effects of under bump metallurgy (UBM) microstructures on the intermetallic compound (IMC) growth of electroplated and stencil printed eutectic Sn-Pb solder bumps were investigated. The process parameters and their effects on UBM surface morphology and UBM shear strength were studied. For the electroplating process, the plating current density was the dominant factor to control the Cu UBM microstructure. For the stencil printing process, the zincation process has the most significant effect on the Ni UBM surface roughness and Ni grain sizes. In both processes, the good adhesion of UBM to aluminum can be obtained under suitable UBM processing conditions. Samples with different UBM microstructures were prepared using the two processes. The resulting samples were thermal aged at 85 °C, 120 °C, and 150 °C. It was observed that the Cu UBM surface roughness had larger effect on the IMC growth and solder ball shear strength than the Ni UBM surface roughness. The thickness of Cu3Sn and Cu6Sn5 IMC depended strongly on the UBM microstructure. However, for Ni/Au UBM, no significant dependence was observed. More likely, the thickness of Au-Ni-Sn IMC near the IMC/solder interface was controlled by the amount of gold and the gold diffusion rate in the solder. Shear tests were performed after thermal aging tests and thermal/humidity tests. Different failure modes of different sample groups were analyzed. Electroless Ni UBM has been developed because it is a mask-less, low-cost process compared to electroplated Cu UBM. This study demonstrated that the process control was much easier for Ni UBM due to its lower reactivity with Sn material. These properties made Ni UBM a promising candidate for the lead-free solder applications. [ABSTRACT FROM AUTHOR]

The significance of interfacial delamination as a crucial failure mechanism in electronic packaging has been documented in many papers. A number of failure criteria have been used to solve the problems with a pre-crack at the interface. However, in real electronic packages, the size and location of the cracks or/and delamination cannot be predicted. It is not easy to use the traditional fracture criteria to deal with more complicated 3D delamination problems. The epoxy molding compound (EMC)/copper leadframe interface was selected in this study. A series of button shear tests were conducted to evaluate the interfacial adhesion between the EMC and copper. In each test, the failure load acting on the EMC of the button shear sample was measured at different shear angles and a finite element model was used to evaluate the stresses at the EMC/copper interface. In this paper, an energy-based failure criterion is proposed using both the interfacial distortional and hydrostatic strain energy densities as two failure parameters. Stresses were extracted from the numerical simulation in order to calculate the interfacial distortional strain energy density, Ud, and the interfacial hydrostatic strain energy density, Uh, related, respectively, to the shear and tensile modes. Ud and Uh were averaged within a selected region of the finite element model where it exhibits high interfacial strain energy density values. [ABSTRACT FROM AUTHOR]

In this paper, a three-dimensional CMOS technology is proposed and implemented using stacked Fin-CMOS (SF-CMOS) architecture. The technology is based on a double layer silicon-on-insulator wafer formed by two oxygen implants to create two single-crystal silicon films with an oxide isolation layer in between. The proposed approach achieves a 50% area reduction and significant shortening of the wiring distance between active devices through vertical connection when compared with conventional planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET structure. SF-CMOS devices and simple circuits were fabricated and characterized. [ABSTRACT FROM AUTHOR]

A planar double-gate SOI MOSFET (DG-SOI) with thin channel and thick source/drain (S/D) was successfully fabricated. Using both experimental data and simulation results, the S/D asymmetric effect induced by gate misalignment was studied. For a misaligned DG-SOI, there is gate nonoverlapped region on one side and extra gate overlapped region on the other side. The nonoverlapped region introduces extra series resistance and weakly controlled channel, while the extra overlapped region introduces additional overlap capacitance and gate leakage current. We compared two cases: bottom gate shift to source side (DG-S) and bottom gate shift to drain side (DG-D). At the same gate misalignment value, DG-S resulted in a larger drain-induced barrier lowering effect and smaller overlap capacitance at drain side than DG-D. Because of reduced drain-side capacitance, the speed of three-stage ring oscillator of DG-S, with 20% gate misalignment length (Lmis) is over gate length (Lg), or Lmis/Lg = 20%, was faster than that of two-gate aligned DG-SOI. [ABSTRACT FROM AUTHOR]

The effects of nonrectangular fin cross section of double-gate FinFETs are studied. For a given top-fin width, which is defined by the photolithography step, the short-channel effect immunity is degraded by the inclination of the sidewalls. The nonrectangular fin geometry also leads to nonuniform current flow and current crowding in the vertical direction. Together with the nonuniform series resistance along the height of the fin, a non-linear dependence of on-current with fin heights (which have been regarded as the Ws in planar MOSFET) is observed. The impacts of nonvertical sidewall have been characterized according to the inclination angle in this work. Under different inclination angles as dictated by the processing technology, the device performances at various fin heights are characterized. A new design constraint that limits the choice of fin height for a given technology is also discussed. [ABSTRACT FROM AUTHOR]

Provides information on a study which fabricated thin-film transistors using the nickel-seeded metal-induced lateral crystallization (MILC) technique. Overview of the nickel-seeded MILC; Device fabrication process; Experimental results and discussion; Design guideline to reduce the grain boundary effect.

Provides information on a study which fabricated thin-film transistors using the nickel-seeded metal-induced lateral crystallization (MILC) in which an amorphous silicon is crystallized to form a large grain polysilicon film. Description of the MILC process; Mobility models of solid phase crystallization and MILC devices; Experimental results and discussion.

Proposes a three-dimensional (3-D) complementary metal oxide semiconductor (CMOS) integrated circuit based on the conventional CMOS silicon-on-insulator technology. Discussion on the 3-D thin film transistor CMOS technology and design issues; Description on the fabrication process; Device characteristics; Inverter characteristics and circuit performance.

In this paper we present an efficient structural approach for diagnosing board interconnects using boundary-scan. Whereas existing diagnosis approaches assume only wired-AND or wired-OR bridging fault model, we consider a more complex bridging short fault model in a CMOS circuit environment. The diagnostic test set is generated on the basis of graph theoretic technique and the adjacency fault model is adopted. By using the structural information of the wiring layout, the test length can be reduced. Both one-step and two-step diagnosis algorithms are given. They guarantee the complete diagnosis of multiple interconnect faults with no aliasing or confounding. The algorithms have been evaluated by simulation on several benchmark layouts and randomly generated layouts. Simulation results show that more than 50% reduction in the number of tests can be achieved for two-step diagnosis when the fault rate is very small, such as in a matured product line. This can significantly save the diagnosis cost for boundary-scan testing. [ABSTRACT FROM AUTHOR]

Proposes a physically-based noise model which predicts that the excess low-frequency noise shows a Lorentzian-like spectrum. Information on silicon-on-insulator (SOI); Noise sources in an SOI metal-oxide-silicon field-effect transistor; Results and discussions; Conclusions.

In this article, a generic VLSI architecture which is both programmable and scalable is proposed for block-matching motion estimation algorithms. Various motion estimation algorithms can be implemented using the proposed architecture by organizing the individual search positions (checking points) into checking vectors. A checking vector is processed in parallel by fully exploiting its data dependency. The optimal choice for the size of checking vector is discussed based on the design tradeoffs among processing speed, silicon area, and I/O bandwidth. Appropriate designs are recommended for various video applications. © 1998 John Wiley & Sons, Inc. Int J Imaging Syst Technol, 9, 257–273, 1998 [ABSTRACT FROM AUTHOR]

The electromigration (EM) properties of pure Cu and Cu/carbon nanotube (CNT) composites were studied using the Blech test structure. Pure Cu and Cu/CNT composite segments were subjected to a current density of 1.2 × 106 A/cm2. The average void growth rate of Cu/CNT composite sample was measured to be around four times lower than that of the pure copper sample. The average critical current-density-length threshold products of the pure Cu and Cu/CNT composites were estimated to be 1800 and 5400 A/cm, respectively. The slower EM rate of the CU/CNT composite stripes is attributed to the presence of CNT, which acts as trapping centers and causes a decrease in the diffusion of EM-induced migrating atoms. [ABSTRACT FROM AUTHOR]

In this letter, the radio-frequency (RF) transmission properties of single-walled carbon nanotubes (CNTs) have been characterized up to the frequency of 12 GHz in a carbon nanotube field-effect transistor (CNFET) configuration using a two-port S-parameter method for the first time. The RF characteristics of the CNTs were measured from the drain to the source of the CNFET. A resistance, inductance, and capacitance model has been proposed, and the element values have been extracted. Without the effect of the parasitics, the RF signal transmission in the CNTs presents no degeneration even at 12 GHz. The capacitive contact between CNTs and metal electrodes is reported. [ABSTRACT FROM AUTHOR]

A local silicon-gate carbon nanotube field effect transistor (CNFET) configuration has been proposed and implemented for integration purpose. By combining the advantages of in situ carbon nanotube growth technology and the silicon-on-insulator technology, we have realized the CNFETs with individual device operation, low parasitic capacitance, high yield fabrication, and better compatibility to the complementary-metal-oxide-semiconductor (CMOS) process. The CNFETs show up-to-date electrical performance. The scaling effect of gate oxide is also explored. This configuration makes CNFET a step closer to the CMOS integrated circuit application. [ABSTRACT FROM AUTHOR]

Carbon nanotube (CNT) has a potential to be used as nanoscale transmission lines and as high-performance passive components in nanoelectronics. In this letter, we discuss single-walled carbon nanotubes (SWNTs) that were grown using a chemical-vapor deposition technique. Both the dc and ac two-terminal resistances were measured and analyzed. The transmission properties of the SWNTs were shown by comparing the S parameters of a device with CNTs with those of a device without a CNT. The radio-frequency characterization of the CNTs was carried out using the network analyzer to frequency of 20 GHz. [ABSTRACT FROM AUTHOR]

Silicon oxynitride rectangular optical waveguides have been fabricated by plasma-enhanced chemical vapor deposition and dry etching. The propagation loss and polarization dependent loss in as-grown samples show a substantial reduction after the samples have been annealed. Birefringence measurements before and after annealing on waveguides of different widths suggest that the waveguide modal birefringence is strongly affected by both waveguide geometry and stress in the material. Hence, the modal birefringence can be minimized by designing the appropriate waveguide geometry to compensate for any stress effects. [ABSTRACT FROM AUTHOR]

A stacked three-dimensional Fin-CMOS (SF-CMOS) technology has been proposed and implemented. The technology is based on a double-layer SOI wafer formed by performing two oxygen implants to form two single-crystal silicon films with isolation layer in between. The proposed approach achieves a 50 % area reduction and significant shortening of wiring distance between the active devices when compared with existing planar CMOS technology. The SF-CMOS technology also inherits the scalability and two-dimensional processing compatibility of the FinFET architecture. [ABSTRACT FROM AUTHOR]

An optical switch structure which combines a planar lightwave circuit and liquid crystal is proposed and experimentally demonstrated. The switching is realized by inducing total internal reflection through controlling the refractive index of the liquid crystal. The principle and the design of the integrated optical switch are described. Experimental results suggest that anchoring of the liquid crystal molecules on nonplanar structures is very crucial in affecting the switching performance. [ABSTRACT FROM AUTHOR]

An air-spacer technology with raised source/drain (S/D) for ultrathin-body (UTB) silicon-on-insultor MOSFETs is developed. The results show that the poly raised S/D can effectively reduce the series resistance and the air spacer can effectively reduce the fringing capacitance. The air spacer is particularly useful when combined with high-κ gate dielectric. The improved device characteristics are demonstrated experimentally and by extensive two-dimensional device simulation. [ABSTRACT FROM AUTHOR]

Benzocyclobutene (BCB), a low-k, photosensitive, easily patterned material is used as the interfacing layer that isolates the passive components from the lossy, low-resistivity silicon. Its performance is further improved by reducing the conductive loss with an electroplated and highly-conductive metal, namely, copper. Standard 50-Ω microstrip lines and a microstrip-transmission-line-based microwave filter, exhibiting insertion losses of 0.8 dB and 1.1 dB at 10 GHz, respectively, are demonstrated. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 40: 9–11, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.11271 [ABSTRACT FROM AUTHOR]

We have demonstrated the fabrication of horizontally aligned carbon nanotube (CNT) bundles on Si substrate for interconnect line application. By controlling the catalyst thickness, we fabricated multi-walled CNT and few-walled CNT bundles with different diameters. We measured the resistances of the CNTs as a function of the length and the diameter. The dependence of the contact resistance between the CNT and the metal on the CNT diameter was extracted from the resistance plots. We investigated and experimentally validated the relationship between the diameter and the mean free path of the CNT.