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In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

Effective interface engineering techniques in III-nitride heterojunction power devices, aiming at yielding high VTH stability in insulated-gate devices and suppressed current collapse in high-voltage switching operation, are of critical significance to enhance device performance and reliability. In this work, we present an interface enhancement technology featuring in situ low-damage NH3/Ar/N2 pre-gate plasma treatment prior to the ALD-Al2O3 deposition for high-performance III-nitride MIS-HEMTs. It is manifest that this technology can effectively remove the native oxide while forming a monocrystal-like nitridation interfacial-layer (NIL) on the III-nitride surface. The Al2O3(NIL)/GaN/AlGaN/GaN MIS-heterostructures with high-quality interface exhibit well-behaved electrical characteristics, including a small subthreshold swing of ∼64 mV/dec, a small hysteresis of ∼0.09 V, tiny f/T dispersions in the C- V characteristics, and low interface trap density of ∼1 × 1012-6 × 1012 cm−2eV−1. Cross-sectional TEM micrograph of the Al2O3/III-nitride gate stack with a monocrystal-like nitridation interfacial-layer (NIL). [ABSTRACT FROM AUTHOR]

In this work, we manifest that the epitaxial structure for p-GaN gate high-electron-mobility transistor is a versatile platform to develop electronics for operating in an extremely wide temperature range (X-WTR) from 2 to 675 K, with comprehensive X-WTR studies on device operation and circuit behaviors. The key enabler for the high-temperature operation is the wide bandgap that substantially suppresses the thermal excitation of the intrinsic carrier. However, for the low-temperature side, the two-dimensional electron and hole gas (2DEG and 2DHG) channels at the heterojunctions are formed by the temperature-insensitive polarization fields, which free the carriers from freezing out. The monolithically integrated GaN n-FET, p-FET, and the resultant complementary circuits are, therefore, shown to operate in X-WTR. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

A 650-V/84-mΩ normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally-off gate control, and a 650-V normally-on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QG×RON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs. [ABSTRACT FROM AUTHOR]

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this article, we demonstrate a GaN-based gate driver with an overcurrent (OC) protection circuit and an undervoltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, the OC protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power devices. The OC protection is implemented with a separated sensing branch and blanking time controller, and the response time to an OC event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V, and its threshold voltage is especially tailored for the GaN integrated circuits. [ABSTRACT FROM AUTHOR]

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad. [ABSTRACT FROM AUTHOR]

Enhancement-mode (E-mode) p-channel gallium nitride (GaN) field-effect transistors (p-FETs) are essential components for GaN-based complementary logic circuits. For the ease of integration with n-FETs, they could be fabricated on the commercial p-GaN gate high-electron-mobility-transistor (HEMT) platform, on which the two-dimensional electron gas at the AlGaN/GaN hetero-interface is completely depleted in as-grown epi-structures. However, under the gated region where p-GaN is recessed and depleted at thermal equilibrium, a parasitic electron channel (PEC) could appear at the AlGaN/GaN interface. This Letter reports experimental investigations on the PEC with specifically designed structures, confirming that the PEC does exist but imposes limited impacts on electrical characteristics of p-FETs. When connected with an external contact, the PEC could act as a back gate to modulate the overlaying p-channel. If isolated from external contacts, which is the case of p-FETs under normal operations, electrons in the PEC would redistribute under the active region of p-FETs in the horizontal direction (i.e., parallel to the surface) under different biases but are mostly confined near the AlGaN/GaN interface in the vertical direction (i.e., perpendicular to the surface). [ABSTRACT FROM AUTHOR]

We report GaN high-electron-mobility transistors (HEMTs) with a thick (7.7 µm) GaN buffer on a Czochralski low resistivity Si (LRS) substrate. The GaN HEMTs exhibit high performance for both radio-frequency (RF) amplification and power conversion. The thick GaN buffer was grown by means of vacancy engineering, delivering a low dislocation density of ∼1.6 × 108 cm−2, contributing to suppressed RF signal coupling to the lossy Si substrate and a high vertical voltage blocking capability. For RF performance, GaN HEMTs with a 650 nm gate exhibit an fT/fMAX value of 25.1/32.3 GHz and a maximum output power POUT of 2.2 W/mm at 4 GHz with a drain voltage VDS of 20 V, which is comparable with the performance of RF GaN HEMTs on a high-resistivity silicon substrate without the existence of the field plate. For power performance, the vertical breakdown voltage of the wafer is 1160 V, and the three-terminal lateral breakdown voltage is 885 V in a GaN HEMT with a gate-to-drain distance of 8 µm. The thick GaN layer on the LRS substrate scheme thus provides a compelling platform for monolithic integration of high-performance RF devices and high-voltage power devices. [ABSTRACT FROM AUTHOR]

Recently, a GaN reverse-conducting high-electron-mobility transistor (RC-HEMT) has been demonstrated. The RC-HEMT features built-in distributive Schottky contacts, which provide a low-loss freewheeling path. The RC-HEMT offers the same functionality as an HEMT/Schottky barrier diode (SBD) pair, but consumes much less chip area, thus its ${R}_{ \mathrm{\scriptscriptstyle ON}}$ (ON-resistance $\times $ total device width) is significantly reduced. Theoretically, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT can approach that of an HEMT. In practice, due to certain geometry limitations, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of an RC-HEMT lies between an HEMT/SBD pair and a single HEMT. This work investigates the factors that influence ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT using both experimental measurements and numerical simulations. It is found that ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is strongly affected by the geometry of the source and channel regions, where HEMT sections and SBD sections are interdigitally distributed. With coarse patterning of these regions, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is close to the HEMT/SBD pair. Through proper geometry scaling, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of RC-HEMT is reduced and approaches that of HEMT. [ABSTRACT FROM AUTHOR]

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoHLED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The detrapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance Ron and/or threshold voltage Vth of the HEMT. The results show that the recovery processes of both dynamic Ron and threshold voltage Vth of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs. [ABSTRACT FROM AUTHOR]

The short circuit (SC) behavior of a newly developed GaN-HEMT/SiC-JFET cascode device is investigated in this work. The reverse leakage current through the drain-side PN junction (IR) of the SiC JFET under SC conditions is measured simultaneously during the SC event. IR of the SiC JFET increases to 6.4 A at the end of a 5-μs nondestructive SC pulse. The increase of IR during the SC pulse induces a turning point in the SC current waveform and a dramatic negative threshold voltage shift (>30 V) in the SiC JEFT, resulting in high transient drain-to-source voltage in the GaN HEMT. The underlying mechanism is associated with the increase of local potential in the P-type layer of the SiC JFET with inevitable spread resistance (RSPD). It is suggested that reducing RSPD can improve SC capability and high IR should be considered in SC failure mechanism analysis and the design of external gate resistance of the SiC JFET. [ABSTRACT FROM AUTHOR]

Short circuit (SC) capability of 650-V Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under single and repetitive tests is characterized in this article. The investigated devices exhibit strong capability under a single SC test, but weak capability under repetitive SC tests with a bus voltage of 400 V and a gate drive voltage of 6 V. The failure mechanism under repetitive SC tests is revealed through electrothermal simulation and microscale failure spot analysis. Thermal fatigue cracks are formed due to the high temperature spike and local temperature fluctuations in the narrow GaN channel and buffer layers, leading to weak repetitive SC capability. The unique heat confinement effect in the GaN layer plays an important role in the formation of high temperature spike and fatigue cracks. The withstand time in a single SC test is several hundred microseconds due to fast drain current drop that results from high temperature and, to a lesser degree, the dynamic threshold voltage shift during the SC transient. The device failure in a single-event SC test is related to heat diffusion to a wider region. Some guidelines are proposed for handling and improving the repetitive SC capability. [ABSTRACT FROM AUTHOR]

The threshold voltage (VTH) of an enhancement-mode Schottky-type p-GaN gate high-electron-mobility transistor (HEMT) is found to have a special dependence on the drain bias. The device commonly requires higher gate voltage to switch on the transistor from a high-drain-voltage off-state than what is expected from the static device characteristics. The reason behind the dynamic VTH has been proved to be the floating p-GaN layer, where charges could be stored and further influence VTH under different drain bias. In this article, a SPICE-compatible equivalent circuit model is presented according to the structure of Schottky-type p-GaN gate HEMTs. It features a floating node to imitate the charge storage process within the gate stack. Compared to conventional models, the proposed model could accurately predict the dynamic VTH characteristics and switching behaviors of power electronics circuits, where Schottky-type p-GaN gate HEMTs are deployed as power transistors. The phenomena related to the dynamic VTH, including the disappearance of Miller plateau, the overestimated false-turn-on problem, and the higher reverse conduction loss are evaluated with a half-bridge circuit and the merits of the proposed model are verified. [ABSTRACT FROM AUTHOR]

An AlGaN-recess-free, ultrathin-barrier (UTB) AlGaN (<6 nm)/GaN heterostructure is presented for the fabrication and integration of AlGaN/GaN enhancement/depletion-mode (E/D-mode) heterojunction field-effect transistors (HFETs), and metal–insulator-semiconductor HFETs (MIS-HFETs). The 2D electron gas in the access region of the UTB-AlGaN/GaN (MIS)HFETs can effectively be recovered by a low-pressure chemical-vapor-deposited SiNx passivation layer (LPCVD-SiNx), which is capable of introducing about 2.75 × 1013 cm−2 positive fixed charges at the LPCVD-SiNx/(Al)GaN interface. LPCVD-SiNx can also serve as a good gate insulator for D-mode MIS-HFETs. Using the self-terminating etching of LPCVD-SiNx on III-nitride as well as a low-damage remote plasma pretreatment, high uniformity E-mode HFETs and low-hysteresis E-mode MIS-HFETs have been fabricated using the GaN-on-Si platform. E/D-mode MIS-HFET inverters with a large logic swing have also been demonstrated on this platform. The UTB-AlGaN/GaN heterostructure is an attractive technology platform for the on-chip integration of power and RF devices with power-driven circuits for GaN-based smart power integrated circuits. [ABSTRACT FROM AUTHOR]

GaN power transistors are attracting increasing attention for next-generation power switching applications. However, GaN power transistors should not be regarded as a direct replacement for silicon power metal–oxide–semiconductor field-effect transistors, since the unique properties of GaN power transistors require special treatment. In this work we review a unique and critical property of GaN power transistors, the dynamic threshold voltage (Vth). GaN power transistors feature a p-GaN gate structure, while the gate metal contacts the p-GaN layer through a Schottky junction. This unique p-GaN gate structure is distinctively different from the silicon metal–oxide–semiconductor gate structure in that the p-GaN layer is actually a floating region without direct electrical contact to the external electrodes of the device. The floating p-GaN layer enables a charge storage process during the switching operation of a p-GaN gate high-electron-mobility transistor. Through carefully designed experiments, the strong correlation between charge storage and the dynamic Vth shift has been revealed; this also serves as an approach to accurately predict the dynamic Vth during switching operation. The influence of the dynamic Vth on power switching applications is discussed. For example, with a positive dynamic Vth shift, the reverse conduction voltage of a GaN power transistor is significantly increased, adding to the power loss. This positive Vth shift also demands a sufficiently high gate drive voltage to ensure that the GaN power transistor can be fully turned on, which reduces the safety margin for the gate reliability of the device. To design a GaN based power switching circuit, accurate simulation of the device/circuit characteristics is necessary. Circuit simulations that do not consider the dynamic Vth lead to a large deviation from the measurement circuit characteristics. We demonstrate that by incorporating the dynamic Vth into the circuit model this deviation can be effectively eliminated. [ABSTRACT FROM AUTHOR]

A 1200-V/100-mΩ silicon carbide (SiC) junction field-effect-transistor (JFET)/ gallium nitride (GaN) high-electron-mobility-transistor (HEMT) hybrid power switch is demonstrated, which features a flip-chip copackaged cascode configuration incorporating a vertical SiC JFET and a lateral GaN-HEMT. The high-voltage SiC-JFET provides the high-voltage blocking capability while the low-voltage GaN-HEMT enables the normally-off gate control with superior switching characteristics. Compared to conventional SiC-JFET/Si-mosfet cascode devices, the SiC-JFET/GaN-HEMT cascode device exhibits fast switching speed, which has been validated by systematic characterizations including static/dynamic device-level measurements and board-level hard-switching tests. Meanwhile, the device is free from several notorious issues of high-voltage GaN power transistors such as dynamic on-state resistance degradation and threshold voltage shift. Such a wide-bandgap semiconductor-based hybrid switch is suitable to be deployed in high-power and high-efficiency power conversion systems. [ABSTRACT FROM AUTHOR]

Herein, gallium nitride (GaN) samples implanted with magnesium (Mg) and fluorine (F) ions are investigated by photoluminescence (PL) measurements. In low‐temperature PL measurements, the characteristic green luminescence (GL) band attributable to nitrogen vacancies (VN) is observed in Mg‐ion‐implanted GaN. As VN are likely to act as donors, suppressing their formation is essential to realizing p‐type conductivity. The energy required for a F impurity to replace VN in GaN and eventually form F on a N site decreases when the Fermi level approaches the valence band maximum, and therefore F is employed as a subsequent implantation element to compensate for VN. The GL band peak disappears upon implanting Mg and F ions at a high temperature and adjusting the F concentration to an appropriate value. This result suggests that VN generated by Mg ion implantation can be suppressed using an element with a lower formation energy than that of VN. [ABSTRACT FROM AUTHOR]

Low-loss reverse-conducting normally- OFF double-channel AlGaN/GaN power transistor with the built-in Schottky barrier diode (SBD) has been systematically studied. This device features the MOS-gate section and SBD-anode section paralleled to an interdigital layout along the gate width direction. A common access region that conducts current at both forward and reverse ON-states is employed, which is beneficial to reduce the conduction loss. With a MOS-HEMT/SBD finger width of ${4}~\mu \text{m}/2~\mu \text{m}$ and a total width ratio of 2:1, the device exhibits a threshold voltage of +0.8 V at a drain current of ${10}~\mu \text{A}$ /mm and a low forward ON-resistance of $12.1~\Omega \cdot \text {mm}$. The Schottky metal contacts 2-DEG directly, which results in a low reverse turn-on voltage of −0.6 V (at −1 mA/mm) and low reverse ON-state voltage of −1.7 V (at −50 mA/mm). A leakage suppression MOS field plate (FP) is applied to shield the Schottky contact from the strong electric field, leading to a low OFF-state leakage current of 14 nA/mm at +100-V drain bias and a high breakdown voltage (BV) of +698 V. The finger width and the number of fingers should be optimized. A narrow finger width benefits the current sharing at the access region, while the increasing number of fingers introduces more Schottky depletion regions along the gate width direction that degrade ${R}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

Commercially available normally-off GaN power high-electron-mobility transistor (HEMT) devices have typically adopted a p-GaN gate structure. In the gate region, there exist a Schottky junction (between gate electrode and the p-GaN layer) and a p-GaN/AlGaN/GaN heterojunction. As the p-GaN layer is not directly shorted to the gate electrode and conducting channel, it can be considered as electrically “floating.” With drain voltage changing during a switching process, the variation of net charge in the floating p-GaN layer would cause instability in threshold voltage. Besides, because of the distinctive features of the p-GaN gate HEMT structure under certain gate/drain bias, gate-related junction capacitances would exhibit behavior different from those of a Si mosfet. Consequently, the switching transient performance of a GaN transistor with a p-GaN gate could be significantly influenced by the aforementioned factors. In this work, the threshold voltage instability associated with the drain-to-gate voltage stress is first analyzed. Despite the difficulty in directly performing capacitance measurements inside the device structure, a hybrid physical-behavior modeling method is proposed. The model is capable of extracting the capacitance bias relationships with regard to the gate region from static terminal measurements. In previous works, the advanced analytical model would make modest change on a Si mosfet's model. As a result, without fully considering the specific features of a GaN transistor with the p-GaN gate, the simulated waveforms would exhibit 20–50% discrepancy from the experiment. In contrast, the proposed switching transient analytical approach would exhibit improved accuracy (<10% disparity). Consequently, the switching transient performance of the GaN transistor with the p-GaN gate could be more accurately evaluated. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiNx/PECVD-SiNx) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance (${R}_{ \mathrm{ON}}$), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET. [ABSTRACT FROM AUTHOR]

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations. [ABSTRACT FROM AUTHOR]

In this work, characterizations are conducted to investigate the threshold voltage (VTH) stability of the normally‐off GaN metal–insulator–semiconductor (MIS‐) field‐effect transistor (FET) with fully recessed gate structure and highly reliable low‐pressure chemical vapor deposition SiNx gate dielectric. We conducted bias‐temperature instability (BTI) tests under both positive and negative gate bias. We demonstrated the highly stable VTH of the high‐performance MIS‐FETs with small BTI, which benefits from the effective interfacial protection layer. More specifically, combining the BTI tests and drain current 1/f noise analysis, we present extensive investigation of the physical origins of BTI. According to the experimental evidence and analysis, we ascribe the VTH instability to the trapping/detrapping of the pre‐existing trap states located at the SiNx/GaN interface and/or in the gate dielectric. [ABSTRACT FROM AUTHOR]

(Al)GaN recess-free normally OFF technology is developed for fabrication of high-yield lateral GaN-based power devices. The recess-free process is achieved by an ultrathin-barrier (UTB) AlGaN/GaN heterostructure that features a natural pinched-off 2-D electron gas channel. The top–down manufacturing technique overcomes the challenges in etching of AlGaN barrier with well-controlled depth and uniformity, which is especially attractive for fabrication of normally OFF GaN-based high-electron-mobility transistors (HEMTs) and metal–insulator–semiconductor HEMTs (MIS-HEMTs) on large-size Si substrate. With SiNx passivation grown by low-pressure chemical-vapor deposition, on-resistance of the UTB-AlGaN/GaN-based power devices can be significantly reduced. High-uniformity low-hysteresis normally OFF HEMTs and Al2O3/AlGaN/GaN MIS-HEMTs are successfully demonstrated on the UTB AlGaN/GaN-on-Si platform. It is also a compelling technology platform for manufacturing high-performance GaN-based lateral power diodes, and normally OFF p-(Al)GaN heterojunction field-effect transistors. [ABSTRACT FROM PUBLISHER]

Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance (RON) of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been investigated by using ramped and transient back-gating characterizations as well as TCAD simulations. High voltage applied to the conductive Si substrate can modulate 2DEG conductivity through the back-gate effect, whereby the dynamics of both acceptor and donor buffer traps are identified. Distinct buffer trapping and asymmetric vertical leakage under opposite top-to-substratebias polarities have been observed, which are attributed to the fundamentally different carrier injection/transport mechanisms. It is suggested that the energy barrier at the nucleation-layer/Si interface can limit the electron injection from Si substrate into the buffer stack and consequently influence the bufferrelated current collapse. [ABSTRACT FROM AUTHOR]

In this paper, we report a systematic study of the nitridation effects on GaN surface by first-principles calculations and X-ray/ultraviolet photoemission spectroscopy (XPS/UPS). According to the calculated electronic structures, two surface bands (i.e., the upper band and the lower band) can be seen within the bandgap for the typical surface configurations that may occur in the experimental condition as a result of surface reconstruction. By the deployment of sufficient nitridation, the energy positions of the lower band are modified toward the valence band by ~1 eV, resulting in the overlapping of the lower surface band with the valence band. Meanwhile, the upper surface band is also modified toward the valence band, but by a smaller amount. The modification to the positions of the surface bands is furthermore manifested by XPS/UPS spectra characterization performed on GaN sample that underwent surface treatment with low-energy remote N2 plasma. The theoretical and experimental results insightfully proclaim the nitridation effects on material properties at atomic level, and support a surface-state ionization model for the GaN band-edge (3.4 eV) emission in metal-AlGaN/GaN Schottky-on-heterojunction diode under forward bias. [ABSTRACT FROM PUBLISHER]

Compared with the state-of-the-art Si-based power devices, enhancement-mode Gallium Nitride (E-mode GaN) transistors have better figures of merit and exhibit great potential in enabling higher switching frequency, higher efficiency, and higher power density for power converters. The bridge-leg configuration circuit, consisting of a controlling switch and a synchronous switch, is a critical component in many power converters. However, owing to the low threshold voltage and fast switching speed, E-mode GaN devices are more prone to false turn-on phenomenon in bridge-leg configuration, leading to undesirable results, such as higher switching loss, circuit oscillation, and shoot through. In order to expand gate terminal's safe operating margin without increasing reverse conduction loss during deadtime, negative gate voltage bias for turn-off and antiparallel diode could be applied to E-mode GaN device. In this paper, with consideration of strong nonlinearities in C–V and I–V characteristics of high-voltage (650 V) E-mode GaN transistors, analytical device models are first developed. Then, we develop an analytical circuit model that combines the circuit parameters with intrinsic characteristics of the high-voltage GaN transistor and antiparallel diode. Thus, key transient waveforms with regard to the false turn-on problem can be acquired, including displacement current and false triggering voltage pulse on gate terminal. The simulated waveforms are then verified on a testing board with GaN-based bridge-leg circuit. In contrast to piecewise switching process models and PSpice simulation, the proposed model exhibits outstanding performances. To provide design guidelines for mitigating false turn-on of GaN transistor, the impacts of different circuit parameters, along with the optimum negative gate voltage bias, are investigated based on the proposed model. [ABSTRACT FROM AUTHOR]

The systematic characterization of a 650-V/13-A enhancement-mode GaN power transistor with p-GaN gate is presented. Critical device parameters such as ON-resistance $R_{{\rm{ON}}}$ and threshold voltage $V_{{\rm{TH}}}$ are evaluated under both static and dynamic (i.e., switching) operating conditions. The dynamic RON is found to exhibit different dependence on the gate drive voltage $V_{{\rm{GS}}}$ from the static $R_{{\rm{ON}}}$. While reasonably suppressed at higher $V_{{\rm{GS}}}$ of 5 and 6 V, the degradation in dynamic RON is significantly larger at lower $V_{{\rm{GS}}}$ of 3–4 V, which is attributed to the positive shift in $V_{{\rm{TH}}}$ under switching operations. In addition to characterization of discrete devices, a custom-designed double-pulse test circuit with 400-V, 10-A test capability is built to evaluate the transient switching performance of the p-GaN gate power transistors. Optimal gate drive conditions are proposed to: 1) provide sufficient gate over-drive to minimize the impact of the $V_{{\rm{TH}}}$ shift on the dynamic $R_{{\rm{ON}}}$; and 2) leave enough headroom to save the device from excessive gate stresses. Moreover, gate drive circuit design and board layout considerations are also discussed by taking into account the fast switching characteristics of GaN devices. [ABSTRACT FROM AUTHOR]

A GaN/SiC hybrid field-effect transistor (HyFET) is proposed as a high-voltage power device that provides a high-mobility lateral AlGaN/GaN channel to reduce the channel resistance and a vertical SiC drift region to sustain the high OFF-state voltage. The performance of the HyFET is evaluated by numerical device simulations. Compared with the conventional SiC MOSFET, the HyFET exhibits a greatly reduced R\mathrm{\scriptscriptstyle ON} together with a low C\mathrm{ GD} and low gate charges. The figures of merit Q\mathrm{ G}\times R\mathrm{\scriptscriptstyle ON} and Q\mathrm{ GD}\times R\mathrm{\scriptscriptstyle ON} of the HyFET are dramatically improved. [ABSTRACT FROM AUTHOR]

Integration of a photon source into the AlGaN/GaN high election mobility transistor (HEMT) platform will realize the functionality of on-chip optical pumping of deep electron traps which suppress the dynamic performances of power HEMTs. Here, we report a Schottky-on-heterojunction light-emitting diode (SoH-LED) realized on the p-doping-free lateral AlGaN/GaN heterostructure. A physical mode based on hot electron induced surface states impact ionization was proposed to explain the hole generation and injection processes in this p-doping-free SoH-LED. Since the SoH-LED shares identical epitaxial structures with HEMT, integration of SoH-LED and HEMT requires no additional epi-layers during the wafer growth and minimum process modification during device fabrication. The SoH-LED structure was seamlessly integrated into the HEMT platform as an on-chip photon source. Experiment results showed that the SoH-LED photons can effectively assist the electron de-trapping processes from both of the surface and bulk deep traps, demonstrating the feasibility of using on-chip generated photons to improve the dynamic performances of AlGaN/GaN power HEMTs. [ABSTRACT FROM AUTHOR]

In this paper, we systematically investigated the leakage and breakdown mechanisms of the low-pressure chemical vapor deposition (LPCVD) silicon nitride thin film deposited on AlGaN/GaN heterostructures. The LPCVD-SiNx gate dielectric exhibits low leakage and high breakdown electric field. The dominant mechanism of the leakage current through LPCVD-SiNx gate dielectric is identified to be Poole–Frenkel emission at low electric field and Fowler–Nordheim tunneling at high electric field. Both electric-field-accelerated and temperature-accelerated time-dependent dielectric breakdown of the LPCVD-SiNx gate dielectric were also investigated. [ABSTRACT FROM PUBLISHER]

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level $E1$ with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while $E2$ with an activation energy of 0.22 eV is located in the buffer layer. [ABSTRACT FROM AUTHOR]

Effective interface trap characterization approaches are indispensable in the development of gate stack and dielectric surface passivation technologies in III-nitride (III-N) insulated-gate power switching transistors for enhanced stability and dynamic performance. In III-N metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs) that feature a buried channel, the polarized barrier layer separates the critical dielectric/III-N interface from the two-dimensional electron gas (2DEG) channel and consequently complicates interface trap analysis. The barrier layer not only causes underestimation/uncertainty in interface trap extraction using conventional ac-conductance method but also allows the Fermi level dipping deep into the bandgap at the pinch-off of the 2DEG channel. To address these issues, we analyze the frequency/temperature dispersions of the second slope in capacitance-voltage characteristics and develop systematic ac-capacitance techniques to realize interface trap mapping in MIS-HEMTs. The correlation between ac-capacitance and pulse-mode hysteresis measurements show that appropriate gate bias need to be selected in the interface trap characterization of MIS-HEMTs, in order to match the time constant of interface traps at the Fermi level with ac frequency and pulsewidth. [ABSTRACT FROM AUTHOR]

We report the first gallium nitride (GaN)-based pulse width modulation (PWM) integrated circuit (IC) featuring monolithically integrated enhancement- and depletion-mode high electron mobility transistors and lateral field-effect rectifiers on the GaN smart power technology platform. The PWM IC is able to generate 1-MHz PWM signal with its duty cycle modulated effectively by a reference voltage ( Vc) over a wide range with good linearity. It features a 5 V supply voltage and is composed of a sawtooth generator and a comparator, both of which can be operated at 1 MHz and exhibit proper functionality over a wide temperature range (from 25 °C to 250 °C). This circuit demonstration further proves the feasibility of an all-GaN solution that features monolithically integrated peripheral gate control circuits and power switches for GaN power converters. An all-GaN solution would lead to a compact system with improved efficiency and enhanced reliability. [ABSTRACT FROM AUTHOR]

Al2O3–AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) featuring indium tin oxide transparent gate electrode are fabricated for the purpose of evaluating the gate reliability. The transparent gate electrode allows electroluminescence (EL) observation in the region directly under the gate, which cannot be performed in conventional MIS-HEMTs with opaque gate electrode. Normally OFF transparent-gate MIS-HEMTs were realized by implanting fluorine ions into the AlGaN barrier prior to the deposition of Al2O3. The dependence of EL on bias condition was investigated with the color of EL resolved by filters. Gate dielectric degradation in MIS-HEMTs was induced by OFF state drain-bias stress, as detected by the increased gate leakage current. Location of the gate degradation could be clearly identified by EL imaging through the transparent gate. From the EL image, the passivation layer under the overhang of T-shaped gate is found to be vulnerable to OFF-state stress, which is confirmed by simulation. [ABSTRACT FROM AUTHOR]

We report the interface characterization of Al2O3/AlN/GaN MOS (metal-oxide-semiconductor) structures with an AlN interfacial layer. A thin monocrystal-like interfacial layer (AlN) is formed at the Al2O3/GaN to effectively block oxygen from the GaN surface and prevent the formation of detrimental Ga-O bonds. The suppression of Ga-O bonds is validated by X-ray photoelectron spectroscopy of the critical interface. Frequency-dispersion in C-V characteristics has been significantly reduced, owing to improved interface quality. Furthermore, using the conventional conductance method suitable for extracting the interface trap density Dit in MOS structures, Dit in the device with AlN was determined to be in the range of 1011-1012eV-1cm-2, showing one order of magnitude lower than that without AlN. Border traps near the gate-dielectric/GaN interface were identified and shown to be suppressed by the AlN interfacial layer as well. [ABSTRACT FROM AUTHOR]

High quality Al2O3 film grown by atomic layer deposition (ALD), with ozone (O3) as oxygen source, is demonstrated for fabrication of normally-off AlGaN/GaN metal-insulator-semiconductor high-electron-mobility transistors (MIS-HEMTs). Significant suppression of Al-O-H and Al-Al bonds in ALD-Al2O3 has been realized by substituting conventional H2O source with O3. A high dielectric breakdown E-field of 8.5 MV/cm and good TDDB behavior are achieved in a gate dielectric stack consisting of 13-nm O3-Al2O3 and 2-nm H2O-Al2O3 interfacial layer on recessed GaN. By using this 15-nm gate dielectric and a high-temperature gate-recess technique, the density of positive bulk/interface charges in normally-off AlGaN/GaN MIS-HEMTs is remarkably suppressed to as low as 0.9 x 1012cm-2, contributing to the realization of normally-off operation with a high threshold voltage of +1.6 V and a low specific ON-resistance RON,sp of 0.49 mΩ cm². [ABSTRACT FROM AUTHOR]

In this work, we attempt to reveal the underlying mechanisms of divergent V TH-thermal-stabilities in III-nitride metal-insulator-semiconductor high-electron-mobility transistor (MIS-HEMT) and MOS-Channel-HEMT (MOSC-HEMT). In marked contrast to MOSC-HEMT featuring temperature-independent VTH, MIS-HEMT with the same high-quality gate-dielectric/III-nitride interface and similar interface trap distribution exhibits manifest thermally induced VTH shift. The temperature-dependent VTH of MIS-HEMT is attributed to the polarized III-nitride barrier layer, which spatially separates the critical gate-dielectric/III-nitride interface from the channel and allows "deeper" interface trap levels emerging above the Fermi level at pinch-off. This model is further experimentally validated by distinct VG-driven Fermi level movements at the critical interfaces in MIS-HEMT and MOSC-HEMT. The mechanisms of polarized III-nitride barrier layer in influencing VTH-thermal-stability provide guidelines for the optimization of insulated-gate III-nitride power switching devices. [ABSTRACT FROM AUTHOR]

On a GaN smart power integrated circuit (IC) platform, a highly linear (i.e., proportional to absolute temperature) temperature sensor IC is demonstrated for building voltage references as well as temperature compensation functional blocks. The circuit is designed based on the temperature-dependent characteristics of GaN-based peripheral devices (e.g., heterojunction Schottky barrier diode, enhancement-/depletion-mode high electron mobility transistors, and lateral field-effect rectifiers) that are monolithically integrated with high-voltage power devices. This monolithic integration scheme facilitates the design efforts in taking full advantages of GaN’s superior capability to operate at high temperatures. Proper circuit operation was demonstrated at 275 °C. [ABSTRACT FROM AUTHOR]