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The origin of a greater decrease in kink drain voltage $V_{kink}$ in floating body PD-SOI MOSFETs with gate lengths shorter than $0.35 ~\mu m$ is newly revealed. The $V_{kink}$ formula as a function of the internal body voltage and $I_{DS}$ is derived by combining the modified impact ionization multiplication factor with the body-source junction I-V equation. The parameters in this formula are extracted from the measured data of $I_{B}$ vs. $V_{BS}$ and ${- I}_{B}/I_{DS}$ vs. $V_{DS}$ in the body contacted devices. By calculating the formula using the extracted parameters, it is newly found that a decrease of the drain-source saturation voltage at a shorter channel is a primary cause for the short-channel effect on $V_{kink}$ reduction.

This paper presents the results of charge-pumping measurements of SOI MOSFETs. The aim of these measurements is to provide information on the density of interface traps at the front and back Si-SiO2 interface. Three-level charge-pumping is used to obtain energy distribution of interface traps at front-interface

his paper presents a complete study of the impactof mechanical stress on the performance of SOI MOSFETs.This investigation includes dc, analog and RF characteristics.Parameters of a small-signal equivalent circuit are also ex-tracted as a function of applied mechanical stress. Piezore-sistance coefficient is shown to be a key element in describingthe enhancement in the characteristics of the device due tomechanical stress.

In this paper, the diode characteristics of our newly proposed super-steep subthreshold slope “PN-body tied (PNBT) silicon-on-insulator field-effect transistor” are presented, and compared with conventional diodes. We report that the device possesses super-steep characteristics, low leakage current, and sharp turn-on characteristics, even in the ultralow voltage range (50 mV). These indicate that the PNBT diode can potentially be used in high-efficiency rectification for energy harvesting, particularly in situations where there is ultralow input power. In addition, the hysteresis characteristics and the slight shift of the voltage at zero current are confirmed as specific characteristics of PNBT diodes.

In this paper, n-channel and p-channel super-steep subthreshold slope (SS) PN-body tied (PNBT) silicon on insulator field-effect transistors (SOI-FETs) are demonstrated. The PNBT structure has a symmetrical source and drain structure. The devices show super-steep SS (< 1 mV/dec) characteristics while maintaining low off current (< 1 pA/ $\mu$ m) and high on/off ratio (up to 6 decades) with low drain voltage (Vd = ± 0.1 V), good output characteristics, and threshold voltage controllability. The devices have a body current and a hysteresis characteristic; however, these can be suppressed under proper device conditions. The operation mechanism of the PNBT SOI-FET is clarified by simulation, and an inherent thyristor on the PNBT structure plays a significant role. Both the p-channel and n-channel PNBT SOI-FET characteristics are discussed, and it is indicated that an ultralow power complementary metal-oxide-semiconductor can be realized by the PNBT SOI-FET.

A new compact model is introduced to determine the drain current of an experimental short-channel silicon-on-insulator (SOI) metal–oxide–semiconductor field-effect transistor (MOSFET) analytically. The effective physical parameters of the experimental nanoscale SOI MOSFET were successfully extracted for the first time using an efficient search algorithm named particle swarm optimization (PSO) as a link between the analytical drain model and the experimental data. Seven important parameters, viz. the drain-induced barrier lowering, subthreshold swing, additional resistance at the source terminal, carrier velocity, low-field carrier mobility, and threshold voltage, were sought using the PSO algorithm to obtain the best fitness value. The results revealed that the application of this PSO strategy achieved an excellent match between the proposed drain current model and experimental data notwithstanding the initial values of the fitting parameters. Also, the internal node capacitances of the short-channel SOI MOSFET were successfully extracted for use in compact models of its small-signal operation. [ABSTRACT FROM AUTHOR]

Today submicron silicon-on-insulator (SOI) MOSFET structures are widely used in different electronic components and also can be used as sensing elements in some applications. The development of devices based on the structures with specified characteristics is impossible without computer simulation of their electric properties. The latter is not a trivial task since many complicated physical processes and effects must be taken into account. In current study ensemble Monte Carlo simulation of electron and hole transport in deep submicron n-channel SOI MOSFET with 100 nm channel length is performed. The aim of the study is investigation of the influence of interband impact ionization process on the device characteristics and determination of the transistor operation modes when impact ionization process starts to make an appreciable influence on the device functioning. Determination of the modes is very important for adequate and accurate modeling of different devices on the basis of SOI MOSFET structures. Main focus thereby is maid on the comparison of the use of two models of impact ionization process treatment with respect to their influence on the transistor current-voltage characteristics. The first model is based on the frequently used Keldysh approach and the other one utilizes the results obtained via numerical calculations of silicon band structure. It is shown that the use of Keldysh impact ionization model leads to much faster growth of the drain current and provides earlier avalanche breakdown for the SOI MOSFET. It is concluded that the choice between the two considered impact ionization models may be critical for simulation of the device electric characteristics.

This work presents a model parameter extraction method based on four-port network for RF SOI MOSFET modeling. The gate, drain, source and body terminals are served as four separate ports. Four-port measurement simplifies the determination of small-signal equivalent circuit model elements such as parameters related to the body terminal which become clear in the equivalent circuit analysis. The extraction method of the RF SOI MOSFET extrinsic parasitic elements was also presented. The accuracy of the model extraction was verified by measurement and simulation from 100 MHz to 20 GHz. [ABSTRACT FROM AUTHOR]

This paper presents an analytical threshold voltage model for back-gated fully depleted (FD), recessed-source drain silicon-on-insulator metal-oxide-semiconductor field-effect transistors (MOSFETs). Analytical surface potential models have been developed at front and back surfaces of the channel by solving the two-dimensional (2-D) Poisson's equation in the channel region with appropriate boundary conditions assuming a parabolic potential profile in the transverse direction of the channel. The strong inversion criterion is applied to the front surface potential as well as on the back one in order to find two separate threshold voltages for front and back channels of the device, respectively. The device threshold voltage has been assumed to be associated with the surface that offers a lower threshold voltage. The developed model was analyzed extensively for a variety of device geometry parameters like the oxide and silicon channel thicknesses, the thickness of the source/drain extension in the buried oxide, and the applied bias voltages with back-gate control. The proposed model has been validated by comparing the analytical results with numerical simulation data obtained from ATLAS™, a 2-D device simulator from SILVACO. [ABSTRACT FROM AUTHOR]

In short-channel silicon-on-insulatormetal-oxidesemiconductor transistors (SOI MOSFETs) the high electric field near the drain increases the floating-body effect. The aim of this article is to introduce a novel structure that reduces the electric field near the drain, so improving the floating-body effect. In the proposed structure, a dual trench is created in the buried oxide exactly under the junctions of drain/source and channel and is filled with an n-type SiGe material. The dual trench regions absorb the electric field lines and hence, the electric characteristic significantly improve. The proposed structure is named as dual SiGe trench double gate SOIMOSFET. In addition, we observe a considerable improvement in self-heating effects due to the higher thermal conductivity of SiGe in comparison with silicon dioxide. [ABSTRACT FROM AUTHOR]

In this article, we present the thermal characteristics of the MOSFET with SELBOX structure. It is observed that the device shows a reduction in the self-heating effect and exhibits improved static and dynamic thermal behavior. A thermal model is developed to explain the thermal behavior of SELBOX structure. The model was evaluated using simulation implemented by Silvaco TCAD tools. Results show the effectiveness of the structure for the minimization of the self-heating effect (SHE) observed in SOI devices. Further, the results obtained from the simulation studies fit into the model showing the validity of the thermal circuit model. [ABSTRACT FROM AUTHOR]

The initiative to standardize compact (SPICE-like) modelling has recently gained momentum in the semiconductor industry. Some of the important issues of the compact modelling must be addressed, such as accuracy, testing, availability, version control, verification and validation. Most compact models developed in the past did not account for these key issues which are of highest importance when introducing a new compact model to the semiconductor industry in particular going beyond the ITRS roadmap technological 100 nm node. An important application for non-fully depleted SOI technology is high performance microprocessors, other high speed logic chips, as well as analogue RF circuits. The IC design process requires a compact model that describes in detail the electrical characteristics of SOI MOSFET transistors. In this paper a non-fully depleted SOI MOSFET model and its Verilog-AMS description will be presented.

The acoustic phonon modulation (confinement) in semiconductor nanostructures and their interaction with electrons are reviewed. Special emphasis will be placed on free-standing and layered slabs, as well as nanowires. Analysis includes acoustic phonon dispersion relations, displacement wave functions, amplitudes, form factor, electron-phonon scattering rate, and electron mobility. [ABSTRACT FROM AUTHOR]

In this work, the novel characteristics of a FinFET with dual-material gate (DMG) are explored theoretically using a 3D numerical simulator and compared with those of a single material gate (SMG) FinFET in terms of threshold voltage roll off, drain induced barrier lowering (DIBL) and the ratio of transconductance (gm) to drain conductance (gd). Our studies show that the DMG structure achieves simultaneous suppression of short channel effects (SCEs), enhancement in carrier transport efficiency and transconductance. Also, these features can be controlled by engineering the work function and length of gate material. [ABSTRACT FROM AUTHOR]

As the semiconductor industry pushes towards ever decreasing device sizes, the need for an efficient yet accurate simulation method increases. We present a different approach to modeling ultra small semiconductor devices through the use of recursive scattering matrices. This approach is a completely quantum mechanical approach in three dimensions, yet does not suffer from excessive computation time or resources. While the transport in most small semiconductor devices is typically 2D in nature, with a 3D model we are capable of incorporating the interaction of the 3D modes in the contacts with the 2D modes in the active regions. We demonstrate this approach by presenting results for a short channel fully-depleted SOI (Silicon On Insulator) MOSFET. We present results using both hardwall potentials and self-consistent potentials as calculated through the use of an iterative Poisson solver. [ABSTRACT FROM AUTHOR]

Effects of conduction-band non-parabolicity on electron transport properties in silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistors (MOSFETs) are studied by performing Monte Carlo simulation with a full-band modeling. An empirical pseudo-potential method is adopted for evaluating the two-dimensional electronic states in SOI MOSFETs. SOI-film thickness dependence of phonon-limited mobility, drift-velocity and subband occupancy is calculated and the results are compared with those of a simple effective mass approximation. The non-parabolicity effects are found to play an important role in 4-fold valleys under higher applied electric fields or at higher temperatures. [ABSTRACT FROM AUTHOR]

We use the effective potential to include quantum mechanical effects in thin SOI MOSFETs simulated with 3D Monte Carlo. We explore the role of discrete dopant distributions on the threshold voltage of the device within the framework of the effective potential by examining the current-voltage behavior as well as the electron distributions within the device. We find that simulations with the effective potential produce a similar shift in current as classical simulations when the dopants are considered to have a random discrete distribution instead of a uniform distribution. [ABSTRACT FROM AUTHOR]

A full-band Monte Carlo simulation of two-dimensional electron gas is performed to study effects of the non-parabolicity of the energy band structure on the phonon-limited electron mobility in SOI MOSFETs with a thin Si-layer. [ABSTRACT FROM AUTHOR]

The hot-carrier-induced oxide regions in the front and back interfaces are systematically studied for partially depleted SOI MOSFET’s. The gate oxide properties are investigated for channel hot-carrier effects. The hot-carrier-induced device degradations are analyzed using stress experiments with three typical hot-carrier injection, i.e., the maximum gate current, maximum substrate current and parasitic bipolar transistor action. Experiments show that PMOSFET’s degradation is caused by hot carriers injected into the drain side of the gate oxide and the types of trapped hot carrier depend on the bias conditions, and NMOSFET’s degradation is caused by hot holes. This paper reports for the first time that the electric characteristics of NMOSFET’s and PMOSFET’s are significantly different after the gate oxide breakdown, and an extensive discussion of the experimental findings is provided. [ABSTRACT FROM AUTHOR]

A steady-state model of partially-depleted (PD) SOI MOSFETs I-V characteristics in subthreshold range is presented. Phenomena, which must be accounted for in cur- rent continuity equation, which is a key equation of the PD SOI MOSFETs model are summarized. A model of diffusion- based conduction in a weakly-inverted channel is described. This model takes into account channel length modulation, drift of carriers in the

An in uence of the selected physical phenom- ena: impact ionization in silicon and time variation of inter- nal electric field distribution in partially-depleted (PD) SOI MOSFETs on several C-V characteristics of these devices is presented. The role of avalanche multiplication in the so- called

The high frequency performances including microwave noise parameters for sub-quarter micron fully- (FD) and partially-depleted (PD) silicon-on-insulator (SOI) n-MOSFETs are described and compared. Direct extraction techniques based on the physical meaning of each small-signal and noise model element are used to extract the microwave characteristics of various FD and PD SOI n-MOSFETs with different channel lengths and widths. TiSi2 silicidation process has been demonstrated very efficient to reduce the sheet and contact resistances of gate, source and drain transistor regions. 0.25 um FD SOI n-MOSFETs with a total gate width of 100 um present a state-of-the-art minimum noise figure of 0.8 dB and high associated gain of 13 dB at 6 GHz for Vds=0.75

Original extraction techniques of microwave small-signal model and technological parameters for SOI MOSFETs are presented. The characterization method combines careful design of probing and calibration structures, rigorous in situ calibration and a powerful direct extraction method. The proposed characterization procedure is directly based on the physical meaning of each small-signal model element. Knowing the qualitative small-signal behavior of each model parameter versus bias conditions, the high frequency equivalent circuit can be simplified for extraction purposes. Biasing MOSFETs under depletion, strong inversion and saturation conditions, certain technological parameters and microwave small-signal elements can be extracted directly from the measured S-parameters. These new extraction techniques allow us to understand deeply the behavior of the sub-quarter micron SOI MOSFETs in microwave domain and to control their fabrication process

A non-quasi-static model of partially-depleted SOI MOSFETs is presented. Phenomena, which are particularly responsible for dependence of device admittances on frequency are briefly described. Several C-V characteristics of the SOI MOSFET calculated for a wide range of frequencies, preliminary results of numerical analysis and of measurements and brief analysis of the results are presented. Methods of model improvement are proposed