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The wide bandgap semiconductor diamond has been studied to develop high-power and highfrequency electronic devices. Here, high dielectric constant (high-k) TiO2/Al2O3 bilayers are deposited on hydrogenated diamond (H-diamond) channel layers using sputter deposition (SD) and atomic layer deposition (ALD) techniques. Thin ALD-Al2O3 films are employed as buffer layers for the SD-TiO2 and ALD-TiO2 on H-diamond to suppress plasma discharge effect and to decrease leakage current density (J), respectively. The electrical properties of the resulting TiO2/ALD-Al2O3/Hdiamond metal-oxide-semiconductor (MOS) capacitors, MOS field-effect transistors (MOSFETs), and MOSFET logic inverters are investigated. With the same thickness (4.0 nm) for ALD-Al2O3 buffer layer, the ALD-TiO2/ALD-Al2O3/H-diamond MOS capacitor shows a lower J and better capacitance-voltage characteristics than the SD-TiO2/ALD-Al2O3/H-diamond capacitor. The maximum capacitance of the ALD-TiO2/ALD-Al2O3/H-diamond capacitor and the k value of the ALDTiO2/ALD-Al2O3 bilayer are 0.83 μF cm-2 and 27.2, respectively. Valence band offset between ALD-TiO2 and H-diamond is calculated to be 2.3±0.2 eV based on the element binding energies measured using an X-ray photoelectron spectroscopy technique. Both the SD-TiO2/ALD-Al2O3 H-diamond and ALD-TiO2/ALD-Al2O3-diamond MOSFETs show p-type, pinch-off, and enhancement mode characteristics with on/off current ratios around 109. The subthreshold swings of them are 115 and as low as 79mV dec-1, respectively. The ALD-TiO2/ALD-Al2O3/H-diamond MOSFET logic inverters, when coupled with load resistors, show distinct inversion characteristics with gains of 6.2–12.7. [ABSTRACT FROM AUTHOR]

By a careful choice of film deposition conditions, LaAlO3 (LAO) gate dielectric film with equivalent oxide thickness (EOT) of 0.31 nm and gate leakage current density (Jg) of 0.1 A/cm2 (at Vfb+1 V) has been successfully demonstrated. Elimination of interfacial low-k layer at LAO/Si and reduction of defect density in LAO has been realized through both LAO film deposition at high-temperature (700 °C) and subsequent low-temperature (200 °C) annealing. By using thermal desorption spectroscopy technique, we find that our process reduces remnant H2O or OH- species in the LAO film, which are responsible for the degradation of EOT and Jg. [ABSTRACT FROM AUTHOR]

Highlights • Optimization of power-noise performance enables to get the best measurement resolution in minimum power and measurement time. • Noise analyses helps to find the most dominant noise sources of a circuit. • Noise analyses and hand calculation helps the circuit design with optimised power-noise performance. • The analytical results have been proved by simulation and measurement. • State of art RFoM (Resolution Figure of Merit) has achieved for BJT-based temperature sensor. Abstract This paper presents the design aspect of a BJT-based temperature sensor implemented in standard CMOS technology that is optimized for its noise-power performance. The interface electronics of the sensor consists of a continuous-time duty-cycle modulator, where a capacitor is periodically charged and discharged, with two temperature-dependent current sources, between two thresholds determined by a Schmitt trigger. In order to optimize the noise properties of the sensor, the major noise sources have been analyzed and optimized using target specifications of the manufacturer. Experimental results are in agreement with those of simulations and analytical calculations. The sensor has been implemented in 0.7μm CMOS technology. At 3.3V supply, the measured temperature resolution amounts to 3mK for a measurement time of 1.8ms. The test results show that a Resolution Figure of Merit (RFoM) of 3.2pJK2 has been achieved in this design, which is the best reported result for BJT-based temperature sensors in the market. [ABSTRACT FROM AUTHOR]

Quantum dot Cellular Automata (QCA) as a new architecture at the nanoscale is developed as a feasible alternative for the existing Complementary Metal–Oxide–Semiconductor (CMOS) designs. The decoder in the QCA is a very important circuit to address the QCA-based random access memory arrays. It plays a key role in many circuit designs, such as Controlled Logic Block (CLB), Field Programmable Gate Array (FPGA), and memory circuits’ designs. In this paper, a five-input majority gate is used in a modular design methodology to design a 2-to-4 decoder in QCA. The proposed 2-to-4 QCA-based decoder can be utilized to synthesize n-to-2 n decoders as well. The functional correctness of the proposed circuit is evaluated using QCADesigner tool. Also, QCAPro simulator as a popular power estimator tool in QCA evaluates the power dissipation. The obtained results have shown the significant success in terms of clock speed (%57), wire-crossing (%33), cell number (%27), area (%26) and power dissipation than the existing designs. [ABSTRACT FROM AUTHOR]

This paper presents a proof of concept of a differential sensor based on the phase-difference of two injection-locked MEMS resonators, strongly coupled through their actuation voltages by a digital mixer. For the first time the feasibility of a fully monolithically co-integrated CMOS-MEMS differential resonant sensor, exploiting the capabilities of the injection-locked synchronization is proved. The principle of the system is first presented, from which optimal design guidelines are derived. The design of the different blocks of the system is then addressed. Our experimental results demonstrate the sensitivity enhancement of the proposed solution, as predicted by theory, and partial thermal drift rejection in a 70 °C range. The simulated and experimental results highlight the critical points of the system design, on which the emphasis of this article is placed. [ABSTRACT FROM AUTHOR]

A novel beyond-CMOS device concept, the Bilayer pseudoSpin Junction Transistor (BiSJT), is proposed. Like the previously proposed Bilayer pseudoSpin FET (BiSFET), the BiSJT is motivated by the possibility of interlayer electron-hole exciton condensation in bilayer 2-D material systems, and could provide switching energies of a few 10 s of zJ, orders of magnitude below even end-of-the-roadmap CMOS. The BiSJT is, however, current-controlled, and may allow for simpler device design, smaller device area, and more flexible gate design. [ABSTRACT FROM AUTHOR]

Important clues for achieving well-behaved AlGaN/GaN metal-oxide-semiconductor (MOS) devices with Al-based gate dielectrics were systematically investigated on the basis of electrical and physical characterizations. We found that low-temperature deposition of alumina insulators on AlGaN surfaces is crucial to improve the interface quality, thermal stability, and variability of MOS devices by suppressing Ga diffusion into the gate oxides. Moreover, aluminum oxynitride grown in a reactive nitric atmosphere was proven to expand the optimal process window that would improve the interface quality and to enhance immunity against charge injection into the gate dielectrics. The results constitute common guidelines for achieving high-performance and reliable AlGaN/GaN MOS devices. [ABSTRACT FROM AUTHOR]

A general route to transform metal oxide semiconductors from non-SERS active to SERS-active substrates based on defect engineering is reported. The SERS enhancement factor (EF) of metal oxide semiconductors like α-MoO3 and V2O5 can be greatly enhanced and the SERS performance can be optimized according to the detecting analyte and activating laser wavelength by introducing oxygen vacancy defects. The EF of R6G on α-MoO3−x nanobelts can be as high as 1.8 × 107 with a detection limit of 10−8 M, which is the best among metal oxide semiconductors and comparable to noble metals without a “hot spot”. A model, named “effective electric current model”, was proposed to describe the photo-induced charge transfer process between the absorbed molecules and semiconductor substrates. The EF of 4-MBA, R6G and MB on α-MoO3−x nanobelts with different oxygen vacancy concentrations calculated based on the model matches very well with experimental results. As an extension, some potential metal oxide semiconductor SERS-active substrates were predicted based on the model. Our results clearly demonstrate that, through defect engineering, the metal oxide semiconductors can be made SERS-active substrates with high stability and high biocompatibility. [ABSTRACT FROM AUTHOR]

The features of the technology computer aided design of integrated magnetosensitive elements in micro and nanosystems are considered. The results of the simulation and optimization of the constructive and technological parameters for magnetosensitive transistors, integrated Hall elements based on the standard CMOS technology, the Hall field sensor based on SOI-structures, and the characteristics of magnetic field concentrators are presented. [ABSTRACT FROM AUTHOR]

In this research paper, a minimum set of low leakage variability aware ONOFIC CMOS digital standard cell library is developed. The developed standard cell library contains basic cells such as inverter, NAND, NOR, AND, OR and buffer logic cells and characterized at 32 nm bulk CMOS process technology. All cells are designed, at 32 nm technology node under TT process corner at room temperature with power supply of 0.8V by using Silvaco's EDA tools. All generated cells have same cell height of 1.58 m. The proposed logic cells attain large leakage and power delay product (PDP) reduction. ISCAS'85 benchmark circuits 74181 and c17 are designed and verified with developed logic cells at transistor level. The ONOFIC standard cell library reduces 34.40% and 42.74% leakage power and improves PDP by 18.34% and 16.46% for 74181 and c17 circuits, respectively. The result of generated standard cell library shows that it is a good choice for low leakage applications. [ABSTRACT FROM AUTHOR]

An ultra-low power, high speed dual mode CMOS logic family called DMTGDI is introduced. This logic family takes over and improves main characteristics of Gate Diffusion Input (GDI) and Dual Mode Logic (DML). Simulations have been performed in 90 nm CMOS on a single bit full adder. DMTGDI shows 60% performance improvement over conventional DML, and significant reduction of power-delay product (PDP), of about 95% in static mode, and 75% in dynamic mode. Monte Carlo simulations reveal that DMTGDI is more robust under process variation comparing to conventional DML. Post layout simulation demonstrates negligible effect of parasitic elements on performance of the single bit adder. [ABSTRACT FROM AUTHOR]

We developed a vision sensor system that performs a scale-invariant feature transform (SIFT) in real time. To apply the SIFT algorithm efficiently, we focus on a two-fold process performed by the visual system: whole-image parallel filtering and frequency-band parallel processing. The vision sensor system comprises an active pixel sensor, a metal-oxide semiconductor (MOS)-based resistive network, a field-programmable gate array (FPGA), and a digital computer. We employed the MOS-based resistive network for instantaneous spatial filtering and a configurable filter size. The FPGA is used to pipeline process the frequency-band signals. The proposed system was evaluated by tracking the feature points detected on an object in a video. [ABSTRACT FROM AUTHOR]

In this paper, a charge control model is developed for AlGaN/GaN High Electron Mobility Transistor (HEMT) and Metal Oxide Semiconductor High Electron Mobility Transistor (MOSHEMT) by considering the triangular potential well in the two-dimensional electron gas (2DEG) and simulated with matlab. The obtained results from the developed model are compared with the experimental data for drain current, transconductance, gate capacitance and threshold voltage of both devices. The physics-based models for 2DEG charge density, threshold voltage and gate capacitance have been developed. By using these developed models, the drain current for both linear and saturation modes is derived. The predicted threshold voltage with the variation of barrier thickness has been plotted. A positive threshold voltage can be obtained by decreasing the barrier thickness that builds up the foundation for enhancement mode MOSHEMTs. The predicted C-V, Id-Vgs, Id-Vds and transconductance characteristics show an excellent agreement with the experimental results from the literature and hence validate the developed model. The results clearly establish the potential of using AlGaN/GaN MOSHEMT approach for high power microwave and switching applications. Copyright © 2015 John Wiley & Sons, Ltd. [ABSTRACT FROM AUTHOR]

The performance of nanoscale radio frequency integrated circuits (RFIC) is influenced by the circuit parasitics and device dimensions. The present work predicts the design parameters of CMOS ring oscillator (CMOS RO) for its optimal performance and designs the CMOS RO using these parameters in Cadence Virtuoso Analog Design Environment with GPDK 90 nm process. An efficient optimization technique, non-dominated sorting based genetic algorithm (NSGA-II) is used to minimize the power consumption and phase noise of the circuit at its schematic and physical levels. This optimization is also carried out by taking into account the extracted parasitics that would be present in the physical integrated circuit and by considering the variations in the process parameters. The optimization algorithm, effectively converts several time consuming design iterations to a single step design, ensuring the near best performance of the CMOS RO with all possible real time constraints. In this proposed design methodology the optimization objectives such as frequency, power and phase noise are formulated in such a manner that those are implicitly parasitic aware. The design of CMOS RO with different number of stages is verified by performing simulations for transient and noise analysis using Cadence tools. [ABSTRACT FROM AUTHOR]

The frequency dependent irradiation influences on Sm 2 O 3 MOS capacitors have been investigated and possible use of Sm 2 O 3 in MOS-based radiation sensor was discussed in this study. To examine their gamma irradiation response over a range of doses, the fabricated MOS capacitors were irradiated up to 30 grays. Capacitance–Voltage ( C – V ) measurements were recorded for various doses and the influences of irradiation were determined from the mid-gap and flat-band voltage shifts. In addition, the degradations of irradiation have been studied by impedance based leakage current–voltage ( J – V ) characteristics. The results demonstrate that J – V characteristics have not been significantly change by irradiation and implying that the excited traps have a minor effect on current for given dose ranges. However, the frequency of applied voltage during the C – V measurements affects the irradiation response of devices, significantly. The variations on the electrical characteristics may be attributed to the different time dependency of acceptor and donor-like interface states. In spite of the variations on the device characteristics, low frequency measurements indicate that Sm 2 O 3 is a potential candidate to be used as a dielectric layer in MOS based irradiation sensors. [ABSTRACT FROM AUTHOR]

A radio frequency (RF) low voltage and low power down conversion mixer with high linearity using TSMC 0.18-μm technology is presented which operates in 2.4 GHz Industrial Scientific and Medical (ISM) band. The local oscillator (LO) frequency is 2.1 GHz with an input power of 5 dBm, whereas IF frequency is 300 MHz. Multiple gated transistors (MGTRs) method is used to increase the linearity of Gilbert cell mixer. In this method an auxiliary transistor is used parallel to the transconductance stage transistor. This increases linearity by decreasing of transconductance stage transistor. The simulation results show an IIP3 improvement of 16.55 dBm. The proposed low power and highly linear mixer consumes a power of 4.46 mW from 1.8 V a supply voltage. The noise figure (NF) and gain conversion are about 13.8 dB and 9.11 dB, respectively. [ABSTRACT FROM AUTHOR]

A novel technique to extend the tuning range of voltage-controlled oscillators (VCOs) is proposed based on magnetic tuning of a transmission line (TL) resonator. A controllable distributed magnetic coupling in a coplanar strip TL is used to tune the TL parameters in general and the inductance in particular, achieving 222% inductance change of the TL at a center frequency of 60 GHz in order to achieve a wide range of frequency tuning. This technique was implemented with a standard cross-coupled pair oscillator, and an additional varactor. The design was implemented in 65-nm CMOS technology, and achieves a tuning range of 55.1–70.4 GHz (24.6%) with a measured average phase noise of -\92.2 dBc/Hz at 1-MHz offset across the entire band. The power consumption is 21.5 mW, including the output buffer. The VCO core area is 50 \mum\,\times\,155 \mum excluding the buffer and 83 \mum\,\times\,245 \mum including the buffer. [ABSTRACT FROM AUTHOR]

One of the most important issues in designing VLSI circuits is power consumption. Reversible logic which is widely utilized in quantum computing, low power CMOS design, optical information processing, bioinformatics and nanotechnology-based systems decreases power loss. A reversible circuit has zero internal power dissipation because it does not lose information. Reversible barrel shifters are required to construct reversible embedded digital signal and general-purpose processors. Data shifting is often used in high-speed/low-power error-control applications, floating point normalization, address decoding and bit indexing. This paper proposes a novel reversible bidirectional universal barrel shifter which is applied in high speed and high performance applications. The proposed barrel shifter is designed in a single circuit with overflow and zero flags. It performs three operations consisting of rotating, logical and arithmetic shifting that transfers and shifts data in both directions. The design is evaluated and formulated in terms of number of garbage outputs, number of constant inputs, quantum cost, number of reversible gates and hardware complexity. All the scales are in nanometric area. [ABSTRACT FROM AUTHOR]

Reversible logic circuits are of high interests to calculate with minimum energy consumption having applications in low-power CMOS design, optical computing and nanotechnology, especially in quantum computer. Quantum computer requires quantum arithmetic. A new design of a reversible arithmetic logic unit (reversible ALU) for quantum arithmetic has been proposed in this article. As we known, ALU is an important part of central processing unit (CPU) as the execution unit. So this article provides explicit construction of reversible ALU effecting basic arithmetic operations. By provided the corresponding control unit, the proposed reversible ALU can combine the classical arithmetic and logic operation in a reversible integrated system. This article provides a new more powerful ALU which contains more functions and it will make contribute to the realization of reversible Programmable Logic Device (RPLD) in future using reversible ALU. [ABSTRACT FROM AUTHOR]

In this paper, a novel current-mode Four-quadrant analog multiplier is proposed. The newly designed current squarer circuits and one current mirror which all operate in low supply voltage (2 V) are the basic building blocks in realization of the mathematical equations. The multiplier circuit is designed by using 0.35 μm standard CMOS technology and to validate the circuit performance, the proposed multiplier has been simulated in HSPICE simulator. The simulation results demonstrate a linearity error of 0.17%, a THD of 0.16% in 1 MHz, a −3 dB bandwidth of 485 MHz and a maximum power consumption of 0.232 mW while the static power consumption is 0.111 mW. [ABSTRACT FROM AUTHOR]

A novel structure, which is achieved by inserting P+ slots into the polygate of traditional LDMOS-SCR, has been designed to improve the holding voltage. The proposed structure called GateDot was fabricated in 0.5 μm 18 V CDMOS process. In this study, comparative analysis is carried out to make detailed comparisons between conventional LDMOS-SCR and the new proposed structure. GateDot not only maintains superiorities of low trigger voltage and strong capability of shunting ESD current in conventional LDMOS-SCR structure, but also increases the holding voltage greatly. To verify its advantages, theoretical analysis and TCAD device simulations were provided during the course of research. TLP (Transmission Line Pulse) test has been done and the results show that the holding voltage can effectively increase from 7.00 V to 10.17 V, 45.29% increment compared to traditional LDMOS-SCR, which is highly appeal to the simulation results. [ABSTRACT FROM AUTHOR]

In this paper, we propose a systematic design methodology in the category of hybrid-CMOS logic style. A huge library of circuits appropriate for low-power and high-speed applications can be obtained by employing the proposed design methodology. The methodology is before used for designing XOR/XNOR and demonstrates the excellence of the new design features. The question of whether the method can be taken advantage to design the function of Carry and its complement (Carry and InverseCarry), as the third important module of a full adder, and what to extend the answer contributes to move towards the general systematic design. All the presented designs as before have high driving capability, balanced full-swing outputs with less glitches and small number of transistors. Also these only consist of one pass-transistor in the critical path, which causes low propagation delay and high drivability. As known, hybrid-CMOS full adders can be divided into three modules, e.g., SUM, Carry and XOR. Optimising these modules has reduced power consumption, delay and the number of transistors of full adders. Therefore by embedding the balanced full-swing circuits in carry module, it can be expected that 11 new full adder circuits will possess high performance. Simulation results show that the proposed circuits exhibit better performances compared to previously suggested circuits in the proposed realistic test bench. These circuits, outperform their counterparts, are showing 24–126% improvement in the power-delay product (PDP) and 57–82% improvement in the area. All simulations have been performed with TSMC 0.13-μm technology in new full adder test bench, using HSPISE to achieve the minimum PDP. [ABSTRACT FROM AUTHOR]

The CMOS-MEMS mechanically coupled filters fabricated using a mature CMOS-MEMS platform together with simple post-CMOS release processes are proposed in this work for the low-loss and channel-select applications at intermediate frequency (IF) region to enable the MEMS/IC integration in wireless transceivers. For the capacitive transducers implemented in the proposed CMOS-MEMS filters, the combination of the pull-in gap reduction and high-velocity arrayed coupling scheme is adopted in our metal-rich design to reduce the motional impedance (Rm). On the other hand, due to the high electromechanical coupling (ηe) and low material loss (high-Q), the SiO2 structure (i.e., oxide-rich design) is also developed in this work to attain better filter performance as compared to the metal-rich counterpart. As a result, by the use of the extraction technique (i.e., removal of feedthrough effects) and proper termination resistance (i.e., impedance matching), the flattened and properly terminated transmission with filter bandwidth less than 0.72% and stopband rejection greater than 25 dB is successfully demonstrated. [ABSTRACT FROM AUTHOR]

In this paper, a novel power gating method has been proposed with the combination of complementary metal oxide semiconductor (CMOS) logic and FinFET for better sub-threshold leakage current minimization. Sub-threshold leakage currents take the paramount part in overall contribution to total power dissipation which comprises of scaling and power reduction. Power gating technique takes up priority among the different leakage current reduction mechanisms. The novel approach has been applied to a CMOS inverter and a two input CMOS NAND gate. The inverter simulated with high threshold voltage metal oxide semiconductor field effect transistor (MOSFET), VGOT MOSFET and fin field effect transistor (FinFET) as sleep transistor reduces the sub-threshold leakage current by 45.529%, 47.265% and 86.431%, respectively, when compared with inverter in absence of sleep transistor. This proves substantial improvement as compared to the planar CMOS inverter. Further, these techniques applied for a two input NAND gate resulted in reduction of leakage current by 20.536%, 23.955% and 99.942%, respectively. [ABSTRACT FROM AUTHOR]

This paper presents an approach to the design of a high-precision CMOS voltage reference. The proposed circuit is designed for TSMC 0.35 μm standard CMOS process. We design the first-order temperature compensation bandgap voltage reference circuit. The proposed post-simulated circuit delivers an output voltage of 0.596 V and achieves the reported temperature coefficient (TC) of 3.96 ppm/°C within the temperature range from -60°C to 130°C when the supply voltage is 1.8 V. When simulated in a smaller temperature range from -40°C to 80°C, the circuit achieves the lowest reported TC of 2.09 ppm/°C. The reference current is 16.586 μA. This circuit provides good performances in a wide range of temperature with very small TC. [ABSTRACT FROM AUTHOR]

Reversible logic is a new field of study that has applications in optical information processing, low power CMOS design, DNA computing, bioinformatics, and nanotechnology. Low power consumption is a basic issue in VLSI circuits today. To prevent the distribution of errors in the quantum circuit, the reversible logic gates must be converted into fault-tolerant quantum operations. Parity preserving is used to realize fault tolerant in this circuits. This paper proposes a new parity preserving reversible gate. We named it NPPG gate. The most significant aspect of the NPPG gate is that it can be used to produce parity preserving reversible full adder circuit. The proposed parity preserving reversible full adder using NPPG gate is more efficient than the existing designs in term of quantum cost and it is optimized in terms of number of constant inputs and garbage outputs. Compressors are of importance in VLSI and digital signal processing applications. Effective VLSI compressors reduce the impact of carry propagation of arithmetic operations. They are built from the full adder blocks. We also proposed three new approaches of parity preservation reversible 4:2 compressor circuits. The third design is better than the previous two in terms of evaluation parameters. The important contributions have been made in the literature toward the design of reversible 4:2 compressor circuits; however, there are not efforts toward the design of parity preservation reversible 4:2 compressor circuits. All the scales are in the nanometric criteria. [ABSTRACT FROM AUTHOR]

We study the design of different 6T and DICE SRAM blocks based on a commercial 65 nm CMOS technology and discuss the experimental results for X-ray, proton and heavy ion irradiation campaigns. The results obtained show that the number of affected bits depends not only on LET value, but also on the location of a strike. MCU patterns are discussed. The sensitive area is estimated as the whole SRAM cell area after deduction of the region between N+ and P+ guard rings. The results for normally incident particles clearly showed the advantages and trade-offs of different circuit and layout techniques. [ABSTRACT FROM PUBLISHER]

ABSTRACT A design method for a common-gate (CG) low-noise amplifier (LNA) for LTE applications is presented to have a boosted transconductance (gm) value in a single-ended configuration. To overcome the constraint of the gm value for conventional CG LNAs for input matching, a notch filter is utilized at the singled-ended LNA output load. With this topology, the effective gm can be freely increased for a high gain and low noise figure (NF) without affecting input impedance matching. Moreover, the linearity is also enhanced because the notch filter load can reduce high-order harmonics of the operating frequency. A single-ended LNA implemented in a 0.18-μm CMOS process with this technique delivers a maximum voltage gain of 20.9 dB with a minimum NF of 2.6 dB, a third-order intermodulation intercept point of −9 dBm with power consumption of 5.8 mW at 2.6 GHz. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:1409-1412, 2014 [ABSTRACT FROM AUTHOR]

Bandgap and stress engineering using group IV materials—Si, Ge, and Sn, and their alloys are employed to design a FinFET-based CMOS solution for the 7-nm technology node and beyond. A detailed simulation study evaluating the performance of the proposed design is presented. Through the use of a common strain-relaxed buffer layer for p- and n-channel MOSFETs and a careful selection of source/drain stressor materials, the CMOS design is shown to achieve performance benefits over strained Si, meet the $I_{{\rm OFF}}$ requirements, and provide a path for continued technology scaling. [ABSTRACT FROM PUBLISHER]

Abstract: We present a novel and efficient thermal sensor design methodology. The growing demand for power management on VLSI systems drives the need for accurate thermal sensors. Conventional design techniques for on-chip thermal sensors in nanometer technologies consume expensive design iterations and result in increased power consumption and area overhead. Power-efficient, high-sensitivity thermal sensors are important for reducing the thermal stress on the systems or circuits which are being monitored. The proposed design flow methodology, which incorporates a stochastic gradient descent (SGD) algorithm, optimizes the power consumption (including leakage) of IC subsystems. An illustration of the proposed design methodology is presented using a ring oscillator (RO) based on-chip thermal sensor which was designed using 45nm CMOS technology. The RO based thermal sensor has a resolution of 0.097°C/bit. Experimental tests and analysis of the design methodology on a full layout-accurate parasitic netlist of the RO demonstrate the applicability of our methodology towards optimization of the power consumption with temperature resolution as a design constraint. A reduction of power consumption by 52% with a final area of is obtained. [Copyright &y& Elsevier]

ABSTRACT A 1.9-22.5 GHz wideband low-noise amplifier (LNA) based on the current-reused cascade configuration in 90 nm CMOS is reported. The wideband input-impedance matching was achieved by taking advantage of the resistive shunt-shunt feedback in conjunction with a parallel LC load to make the input network equivalent to two parallel resistor-inductor-capacitor (RLC) branches, that is, a second-order wideband band-pass filter (BPF). The wideband output-impedance matching was also achieved by making the output network equivalent to a second-order wideband BPF. Theoretical analysis shows that both the frequency response of input matching and noise figure (NF) can be described by second-order functions with quality factors as parameters. The LNA (LNA-1) dissipates 9.96 mW and achieves low and flat NF of 3.24 ± 0.5 dB and high and flat S21 of 12.02 ± 1.5 dB for frequencies 1.9-22.5 GHz. The corresponding figure of merit (FOM) is 7.44 GHz/mW, one of the highest FOMs ever reported for a wideband LNA with bandwidth around 20 GHz. To study the effect of self-forward body bias (SFBB) on LNA-1, an LNA-2 consisting of LNA-1 and SFBB is implemented for comparison. The results show LNA-2 consumes less power at the expense of a worse NF due to the body noise. © 2014 Wiley Periodicals, Inc. Microwave Opt Technol Lett 56:677-684, 2014 [ABSTRACT FROM AUTHOR]

The design and characterisation of a 60 GHz frequency quadrupler implemented in a conventional 90 nm CMOS technology is presented. The proposed fully differential frequency quadrupler is formed by properly combining a 15 GHz to 30 GHz doubler, two 30 GHz amplifiers, a polyphase filter, a 30 to 60 GHz doubler and two 60 GHz amplifiers. The proposed design is based on a differential architecture and achieves enhanced characteristics in terms of harmonics rejection, bandwidth, power consumption and die area. Conversion loss of 9.3 dBm at 60 GHz with 1.1 dBm input power is achieved. The 3 dB bandwidth lies between 51.5 GHz and 61 GHz, while the total current consumption is 100 mA from a 1.2 V supply voltage for the fully balanced implementation. [ABSTRACT FROM AUTHOR]

Two dual channel three-terminal transmission-gate-like n-p-lateral double-diffused metal oxide semiconductor (n-p-LDMOS) power devices with majorities of both types for conduction are proposed. Based on the method of generating a control signal for one of the gates inside the devices, each proposed n-p-LDMOS device only needs one gate control signal. One of the power devices can be used as an n-LDMOS device and the other can be used as a p-LDMOS device. The safe operating area is widened than the conventional n-LDMOS because of the compensation of electric flux density introduced by electron and hole currents. In addition, the specific ON-resistances of the new devices are reduced by \sim20\% and over 23% compared with that of the conventional n-LDMOS, respectively. The proposed power devices and their control methods are analyzed and verified by numerical simulations. [ABSTRACT FROM AUTHOR]

The GaSb-on-GaAs growth was optimized for the fabrication of metal-oxide-semiconductor (MOS) capacitors (Caps) with low interface state trap density (D it ) using in-situ deposited amorphous silicon (a-Si) interface passivation layer (IPL) and high-k oxides. The best top surface with the average roughness R a =0.37nm and with spiral type “step-flow” growth mode was observed in the GaSb structure with the initial 0.5μm grown at 410°C and the top 0.5μm grown at 485°C. N- and p-type GaSb MOSCaps with reasonable capacitance–voltage(C–V) characteristics at room temperature (RT) were demonstrated using all in-situ 0.5nm a-Si IPL and 10nm Al2O3+HfO2 or Al2O3. A-Si IPL was found essential for n-MOSCaps but not in the case of p-MOSCaps where comparable C–V characteristics with a similarly low D it =1–2×1012 cm−2 eV−1were demonstrated without IPL. [ABSTRACT FROM AUTHOR]

Abstract: This paper discusses about analog circuit design methodology through hierarchical abstraction. A method of translating optimal specifications from a higher level of an hierarchy to a lower level, has been proposed. The specification-translation method has been integrated with an existing Geometric Programming based robust CMOS analog circuit sizing method. A 4th order, Sallen–Key low-pass filter has been designed using the integrated top-down design methodology targeting a technology. Total time taken to design the circuit is approximately 1.5h. A good agreement between simulated performances of the final design with targeted specification proves efficiency of the methodology. [Copyright &y& Elsevier]

Abstract: The Substitution box (S-Box) forms the core building block of any hardware implementation of the Advanced Encryption Standard (AES) algorithm as it is a non-linear structure requiring multiplicative inversion. This paper presents a full custom CMOS design of S-Box/Inversion S-Box (Inv S-Box) with low power GF (28) Galois Field inversions based on polynomial basis, using composite field arithmetic. The S-Box/Inv S-Box utilizes a novel low power 2-input XOR gate with only six devices to achieve a compact module implemented in 65nm IBM CMOS technology. The area of the core circuit is only about 288μm2 as a result of this transistor level optimization. The hardware cost of the S-Box/Inv S-Box is about 158 logic gates equivalent to 948 transistors with a critical path propagation delay of 7.322ns enabling a throughput of 130 Mega-SubBytes per second. This design indicates a power dissipation of only around 0.09μW using a 0.8V supply voltage, and, is suitable for applications such as RFID tags and smart cards which require low power consumption with a small silicon die. The proposed implementation compares favorably with other existing S-Box designs. [Copyright &y& Elsevier]

Nano-scale area-efficient MOS devices are employed in this article to stabilize high-speed operational amplifiers (opamps) for those applications that deal with negative feedback. As an alternative choice, metal-insulator-metal (MIM) capacitors cannot be integrated in every technology as they require additional process masks. Moreover, these components suffer from large silicon area. In this paper, considerations of a successful MOSFET-only amplifier design are highlighted and described. These considerations make it possible to fabricate these amplifiers for a nano-scale digital system-on-chip (SoC). Circuit-level simulations include comparison between MOS capacitors (MOSCAPs) with MIM capacitors (MIMCAPs) in two identical processes. The efficiency of the given design considerations are also validated through simulation in 90-nm CMOS technology. A MOSFET-only amplifier is designed as the main part of a 5 MS/s sample-and-hold. Using the proposed design techniques, the MOSFET-only amplifier with Miller compensation recovers 51% silicon die with respect to a MIMCAP amplifier for identical signal-to-noise-plus-distortion (SNDR) ratio. [ABSTRACT FROM AUTHOR]

Many design techniques have been incorporated into modern CMOS design practices to improve radiation tolerance of integrated circuits. Annular-gate NMOS structures have been proven to be significantly more radiation tolerant than the standard, straight-gate variety. Many circuits can be designed using the annular-gate NMOS and the inherently radiation tolerant PMOS. Bandgap reference circuits, however, typically require p-n junction diodes. These p-n junction diodes are the dominating factor in radiation degradation in bandgap reference circuits. This paper proposes a different approach to bandgap reference design to alleviate the radiation susceptibility presented by the p-n junction diodes. [ABSTRACT FROM PUBLISHER]

Abstract: In this work we investigate the impact of process-induced mechanical stress in narrow width devices and its implication on circuit design. We observe that the channel stress and hence drive strength of narrow width devices significantly depend upon the width of a device. We present a model for estimating width dependent channel stress and effective drive current in strain engineered devices. Width dependent change in drive strength causes W P/W N ratio (also referred to as ‘β’) in inverters to change with inverter scaling factor ‘S’. If not accounted for, this results into a suboptimal circuit design and unaccounted change in performance. Finally, considering the narrow width effects (NWEs), we propose a model to design variable-taper CMOS buffer. In our model the taper factor from one inverter stage to the next is a variable and depends upon the location of an inverter in the buffer chain. We observe that buffer designed using our model takes less area, consumes less power and gives marginal improvement in delay also. [Copyright &y& Elsevier]

Abstract: Device performance in the electronic circuits degrades with elapsed time. Therefore it is important to design a new device to have a reliable performance. In this paper, we present the unique features exhibited by a novel nanoscale silicon-on-insulator (SOI) metal-oxide-semiconductor field effect transistor (MOSFET) in which the silicon active layer consists of an insulator region (IR-SOI). The high-K dielectric HfO2 as an insulator material is located in the silicon active layer and drain region. Our simulation results demonstrate that this leads to improve the hot electron reliability of the IR-SOI in comparison with the conventional SOI-MOSFET (C-SOI). The insulator region HfO2 considerably decreases the electric field in the channel and drain regions. Therefore, the degradation mechanism in the proposed structure is lower than that in the C-SOI structure because of reduction of hot carrier effect (HCE). Also using two-dimensional and two-carrier device simulation, we have investigated the improvement in device performance focusing on the HCE, off current, gate current and gate induced drain leakage (GIDL) which can effect on the reliability of the CMOS devices. [Copyright &y& Elsevier]

In this paper, the design and analysis of a CMOS variable gain amplifier (VGA) with the built-in linearizers and noise reduction technique are presented. A V-band low power and miniature VGA is designed and fabricated. To maximize the gain control range and to improve the linearity, an auxiliary nMOS transistor is added in the cascode structure as a built-in linearizer. Moreover, to reduce the noise figure (NF), an inductor is placed between the transistors in the cascode structure. At the high gain state, the VGA offers a maximum gain of 22 dB with a minimum NF of 4.8 dB at 62 GHz. Due to the built-in linearizers, the VGA demonstrates 40-dB gain control range with a third-order input intercept point (IIP3) of -19 dBm at 60 GHz. At the low gain state, the VGA has 3 dBm of IIP3. In both states, the power consumption is 26 mW from a 2-V voltage supply. The chip size is 0.91\,\times\,0.69 mm^2, including pads. To the authors' knowledge, this VGA demonstrates largest gain control range, the lowest power consumption, and the lowest NF at the high gain state for reported 90-nm CMOS millimeter-wave VGAs. [ABSTRACT FROM AUTHOR]

This paper deals with the design and the implementation of an isolated gate driver system using a CMOS integrated circuit for interleaved dc/dc converters. It is based on a novel gate driver topology for power switches like MOSFETs and insulated-gate bipolar transistors. Composed of two legs of a CMOS inverter, a high-frequency pulse transformer, and two Zener diodes connected in antiseries configuration with the gate of the power switch, this driver topology provides an optimal bipolar gate driver waveform with greater positive and negative gate biases to fasten the switch on and off. It represents a simple ultracompact isolated gate driver simple to integrate in CMOS technology. Power consumption, system size, and robustness of the gate driver are therefore optimized. This integrated driver circuit can be used for any multitransistor applications. We detail the operation principle of the proposed driver topology in this paper. We implemented the gate driver to control a three-phase interleaved boost converter; the results show the effectiveness of the proposed driver system. [ABSTRACT FROM AUTHOR]

A remarkable feature of modern silicon electronics is its ability to remain physically invariant, almost indefinitely for practical purposes. Although this characteristic is a hallmark of applications of integrated circuits that exist today, there might be opportunities for systems that offer the opposite behavior, such as implantable devices that function for medically useful time frames but then completely disappear via resorption by the body. We report a set of materials, manufacturing schemes, device components, and theoretical design tools for a silicon-based complementary metal oxide semiconductor (CMOS) technology that has this type of transient behavior, together with integrated sensors, actuators, power supply systems, and wireless control strategies. An implantable transient device that acts as a programmable nonantibiotic bacteriocide provides a system-level example. [ABSTRACT FROM AUTHOR]

In our previous work (Lazarus and Fedder 2011 J. Micromech. Microeng. 21 0650281), we demonstrated a CMOS-MEMS capacitive humidity sensor with a 72% improvement in sensitivity over the highest previously integrated on a CMOS die. This paper explores a series of methods for creating a faster and more manufacturable high-sensitivity capacitive humidity sensor. These techniques include adding oxide pillars to hold the plates apart, spin coating polymer to allow sensors to be fabricated more cheaply, adding a polysilicon heater and etching away excess polymer in the release holes. In most cases a tradeoff was found between sensitivity and other factors such as response time or robustness. A robust high-speed sensor was designed with a sensitivity of 0.21% change in capacitance per per cent relative humidity, while dropping the response time constant from 70 to 4s. Although less sensitive than our design, the sensor remains 17% more sensitive than the most sensitive interdigitated designs successfully integrated with CMOS [ABSTRACT FROM AUTHOR]

This paper presents optimized very high performance CMOS slow-wave shielded CPW transmission lines (S-CPW TLines). They are used to realize a 60-GHz bandpass filter, with T-junctions and open stubs. Owing to a strong slow-wave effect, the longitudinal length of the S-CPW is reduced by a factor up to 2.6 compared to a classical microstrip topology in the same technology. Moreover, the quality factor of the realized S-CPWs reaches 43 at 60 GHz, which is about two times higher than the microstrip one and corresponds to the state of the art concerning S-CPW TLines with moderate width. For a proof of concept of complex passive device realization, two millimeter-wave filters working at 60 GHz based on dual-behavior-resonator filters have been designed with these S-CPWs and measured up to 110 GHz. The measured insertion loss for the first-order (respectively, second-order) filter is -2.6 dB (respectively, -4.1 dB). The comparison with a classical microstrip topology and the state-of-the-art CMOS filter results highlights the very good performance of the realized filters in terms of unloaded quality factor. It also shows the potential of S-CPW TLines for the design of high-performance complex CMOS passive devices. [ABSTRACT FROM PUBLISHER]

Abstract: Gate-to-channel capacitance C gc(Vg ) data obtained on FD-SOI MOS devices with gate lengths down to 35nm are first reported. Thus, a 2D numerical simulation procedure allowing to calculate the total device capacitance and parasitic capacitances is developed. This enabled us to discriminate the respective contributions of all parasitic components such as spacer, overlap, inner fringe and buried oxide capacitances in the structure. [Copyright &y& Elsevier]

Abstract: Regular layouts that follow restrictive design rules are essential to robust CMOS design in order to alleviate many manufacturing induced effects, such as the effect of non-rectangular gate (NRG) due to sub-wavelength lithograph. NRG dramatically increases the leakage current by more than 15X compared to that of ideal physical layout. To mitigate such a penalty, we developed a technique to optimize regular layout through restrictive design rule parameters and to benchmark post-lithography circuit performance. We propose a procedure to systematically optimize key layout parameters in regular layout to minimize the leakage energy with minimal over head to active energy, circuit speed and area. The proposed layout optimization technique is demonstrated with a 65nm technology and projected for 45nm and 32nm technology nodes. Experimental results show that more than 70% reduction in leakage can be achieved with area penalty of ∼10% and 9–12% overhead on circuit speed and active energy. [Copyright &y& Elsevier]

The magnetic ground states of the isostructural double perovskites Ba2NaOsO6 and Ba2LiOsO6 are investigated with muon-spin relaxation. In Ba2NaOsO6 long-range magnetic order is detected via the onset of a spontaneous muon-spin precession signal below Tc = 7.2 ± 0.2 K, while in Ba2LiOsO6 a static but spatially disordered internal field is found below 8 K. A probabilistic argument is used to show from the observed precession frequencies that the magnetic ground state in Ba2NaOsO6 is most likely to be low-moment (≈0.2μB) ferromagnetism and not canted antiferromagnetism. Ba2LiOsO6 is antiferromagnetic and we find a spin-flop transition at 5.5 T. A reduced osmium moment is common to both compounds, probably arising from a combination of spin-orbit coupling and frustration. [ABSTRACT FROM AUTHOR]

Abstract: Power efficiency of a UHF rectifier circuit, which is part of long-range IC-based passive RFID tags, has become a serious bottleneck in implementing power-hungry intelligent sensors. This paper presents an analytical approach for multi-stage rectifiers, which provides design tradeoffs as well as a set of design rules to improve power efficiency of the rectifier. As an example, three-stage rectifiers are designed with ST 90nm CMOS technology for optimized performance at both 10 and 22m distances. When compared with existing results at the same level of output power, the proposed rectifiers show a 3× better performance in power efficiency (73%) and 55% reduction in power-up threshold with longer operating range. [Copyright &y& Elsevier]