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Abstract— To support 3D Sequential integration with a cost-effective layer transfer, SmartCut™ process at low temperature (below 500 °C) is proposed. Excellent SOI & BOX layer thickness uniformities are demonstrated, while layer integrity, electron and hole mobility performances are already compliant with development grade requirements. Keywords—SmartCut, 3D Integration, Low Temperature, CMOS I. SmartCut Proposal for 3D Sequential Integration In support of the semiconductor evolution, 3D integration is considered, addressing several challenges: integration of multiple types of devices including specialized components, continuous footprint reduction as well as optimization of performance and cost [1]. However, a key challenge for 3D integration, shown on Figure 1 reported in reference [2], is the preparation of a top tier device using as handle surface a fully processed bottom tier device. Hence, the top tier device thermal budget needs to be reduced to avoid degradation of the bottom devices [3]. A mandatory 500 °C thermal budget limitation for 3D Sequential Top layer transfer and MOSFET fabrication is then considered [2, 4]. In order to take advantage of the SmartCut process to transfer at reduced cost (i.e. avoiding a conventional but costly SOI bonding & grinding process) a high quality, highly uniform crystalline layer, we propose the use of a new Low Temperature SmartCut process as an alternative for 3D integration. This paper reports on our findings from such transfer demonstrations on bare handle materials, including for the first time SOI-like layer electrical characterization results. II. Low Temperature SmartCut for 3D Integration For 3D integration, SmartCut process is adapted as schematically shown on Figure 2 in order to transfer at low temperature ultra-thin layers compatible with fully depleted requirements. This process option includes the use of engineered, epitaxial processed donor wafers. The epitaxial process on conventional bulk material allows creation of a first Silicon-Germanium layer, to be used as an etch stop layer after SmartCut splitting. Then a subsequent Si layer, defined accordingly to the SOI film thickness target, is epitaxied. Implant, surface preparation, bonding, splitting process steps, all being compliant with maximum 500 °C low temperature requirement, benefit from conventional FD-SOI experience. Finishing process includes selective etching to recover SOI layer [5]. Then a dedicated curing process step is considered in order to optimize SOI layer electrical properties. Silicon Phase Epitaxial Regrowth (SPER) as described in reference [6] is proposed. Figure 3 highlights such low temperature layer transfer process on a patterned handle wafer. Picture is obtained after SmartCut splitting process step. A visual defect free layer is obtained. III. Low Temperature SOI Performance on Bare Handle wafer The SOI layer thickness variability, over the full spatial wavelength spectrum from device to wafer scale, is driven by the donor epitaxy performance. Figure 4 shows Atomic Force Microscopy (AFM) roughness performance, through 30x30 µm² scan. RMS of 1.0 and 0.9 Å are measured on high and low temperature process options respectively. Best in class performance is then obtained thanks to Low Temperature SmartCut. Figure 5 shows (a) BOX and (b) SOI layers ellipsometry thickness mapping, on a 12 nm SOI / 20 nm BOX sample. BOX layer variability is primarily driven by thermal oxide growth, thus demonstrating a within wafer uniformity << 10 A. SOI layer thickness variability is mainly driven by epitaxy performance on the engineered donor wafer. Figure 6 shows typical KLA Tencor SP3 @ 65 nm threshold defect mapping, as measured on 12 / 20 nm low temperature R&D sample. Micro-defect density on this early development product already demonstrates less than 0.1 defect / cm² performance. Then Figure 7 compares PsiMOS measured electron and hole mobility in the SOI layer using High and Low Temperature SmartCut processes. A as low as 10% mobility performance difference between both processes vintage is already demonstrated. IV. Conclusion To support 3D sequential integration, layer transfer at low temperature (< 500 °C) is demonstrated thanks to an adapted SmartCut process. Next research step will confirm this capability with low temperature layer transfer on patterned substrate for 3DS device assessment. V. References [1] J. Macri, Proc. IEEE S3S Conference, 2018 [2] L. Brunet et al., Technical Digest – IEDM Conference, 2018, pp 7.2.1 – 7.2.4 [3] A. Vandooren et al., Proc. IEEE S3S Conference, 2018 [4] C. Fenouillet-Beranger et al., Proc. IEDM Conf., 2014. [5] J. Widiez et al. ECS Trans., 2014, vol. 64(5), pp. 35-48 [6] G. Gaudin et al., ECS J. Solid. State. Sci Tech., 2(12), 2013, pp 534 - 538 Figure 1

We have designed and fabricated LiNbO 3 Film Bulk Acoustic Resonators operating around 4.2 GHz, suitable for C-band filters, with various bandwidths (60, 170, 300 and 500 MHz). They are based on common crystal cuts suitable for the excitation of longitudinal waves (Z, Y+64° and Y+36°cuts) and of shear waves (Y+163°-cut). Electromechanical coupling factors of 3.5, 9.2, 15.4 and 24% were respectively obtained. Electrodes and piezoelectric film thicknesses were optimized to ensure energy trapping in the resonators. In all cases, quality factors close to 300 are obtained, leading to a Q×f product higher than 1012 Hz, which is the highest value reported so far for LiNbO 3 film bulk acoustic wave resonators. Particularly, with an impedance ratio of 56 dB, an electromechanical coupling coefficient of 15.4% and a quality factor at antiresonance close to 390 at 4.1 GHz, Y+36°-cut LiNbO 3 resonators offer promising performances towards filtering applications in the C-band.

The aim of this paper is to present the 3D-sequential integration and its main prospective application sectors. The presentation will also give a synoptic view of all the key enabling process steps required to build high performance Si CMOS integrated by 3D-sequential with thermal budget preserving the integrity of active devices and interconnects and will sketch a status and prospect on current low temperature device performance.

International audience; The interactions of a moving crack with self-emitted acoustic waves are studied in ion-implanted circular plates of crystalline silicon, where complex reproducible surface patterns made of local roughness variations are observed. A simple geometrical model, considering the sole propagation of A0 Lamb waves inside the assembly, allows full prediction of all of these pattern shapes and their dependence on system parameters (crack velocity, elastic properties). Acoustic waves propagating along and behind the crackfront are shown to play a central role in fracture-pattern formation. When the crack front is curved, surface patterns originate independently of any edge reflection or frequency preselection from acoustic waves propagating along and behind the crack. As in case of Kelvin wake patterns, fracture patterns emerge from geometrically induced coherence.

3D analysis of an arsenic-doped silicon fin sample is performed in a transmission electron microscope (TEM). High angle annular dark-field scanning TEM (STEM-HAADF) and energy-dispersive x-ray spectroscopy (STEM-EDX) modes are used simultaneously to extract 3D complementary multi-resolution information about the sample. The small pixel size and angular step chosen for the STEM-HAADF acquisition yield reliable information about the sidewall roughness and the arsenic clusters’ average volume. The chemical sensitivity of STEM-EDX tomography gives insights into the 3D conformality of the arsenic implantation and its depth distribution. Non-negative matrix factorization method is employed to identify the chemical phases present in the sample automatically. A total variation minimization algorithm, implemented in 3D, produces high-quality volumes from heavily undersampled datasets. The extension of this correlative approach to electron energy-loss spectroscopy STEM tomography and atom probe tomography is also discussed.

In the present work, Film Bulk Acoustic Resonators (FBAR) based on 700 nm-thick LiTaO3 films have been fabricated and characterized. Two orientations of single crystal LiTaO3 thin films have been investigated: (i) $\mathrm{Y}+42^{\circ}$ -cut, in which the longitudinal wave exhibits an electromechanical coupling factor similar to the one of the longitudinal wave in c-axis AlScN; and (ii) X-cut, in which the fast shear wave displays a larger electromechanical coupling coefficient and a lower Temperature Coefficient of Frequency (TCF) than for $\mathrm{Y}+42^{\circ}$ -cut. In both cases, we have demonstrated resonators in the 1–3 GHz range, with electromechanical coupling factors close to respectively 6.6 and 17.4% and quality factors of 230 and 400. Moreover, the X-cut LiTaO3 FBAR displays lower TCF values than those previously reported for LiNbO3 FBAR, with measured temperature coefficients of the resonance and antiresonance frequency of +16 (± 3) and −42 (± 2) ppm/K, respectively. LiTaO3 appears therefore as an appealing candidate for the next generation of wide bandwidth RF filters.

In this paper, Y+163°-cut LiNbO 3 (LNO) Film Bulk Acoustic Resonators (FBAR) with patterned bottom electrodes (AlSi or W) and a sacrificial layer cavity have been fabricated using a layer transfer process (4-inch). Unlike previous work based on films oriented towards the X axis [1], the Y+163° orientation provides a single resonance at 2.2 GHz, with an effective electromechanical coupling factor (k t 2) of 26 %. Thanks to this single mode behavior and to the energy trapping induced by the heavy tungsten electrodes, the quality factor at antiresonance (Q a ) is increased to 600. Moreover a Temperature Coefficient of Frequency (TCF) of –45 ppm/°C is obtained. This demonstrates a significant improvement towards introducing LiNbO 3 as an alternative to AlN in Bulk Acoustic Wave (BAW) filters for the new generation of RF filters.

International audience; Vibrations induced by crack propagation in a strip of bonded silicon wafers are studied. A new optical setup enables the fast recording of crack-originated acoustic waves, emitted both ahead and behind the crack front, in bonded and separated wafers, respectively. Three types of crack-induced vibrations are identified, corresponding to different excitations and responses of the system: (1) “pneumatic” vibrations involving inertia and gas expansion/compression, (2) standard flexural waves involving inertia and bending rigidity, and (3) post-crack vibrations involving inertia, bending rigidity, and coupling to gas pressure. We show that a standard “beam on elastic foundation” model can explain these latter vibrations that occur along crack edges and is consistent with the observed frequencies.

International audience; MeV energy hydrogen implantation in silicon followed by a thermal annealing is a very smart way to produce high crystalline quality silicon substrates, much thinner than what can be obtained by diamond disk or wire sawing. Using this kerf-less approach, ultra-thin substrates with thicknesses between 15 pm and 100 pm, compatible with microelectronic and photovoltaic applications are reported. But, despite the benefits of this approach, there is still a lack of fundamental studies at this implantation energy range. However, if very few papers have addressed the MeV energy range, a lot of works have been carried out in the keV implantation energy range, which is the one used in the smart-cut (R) technology. In order to check if the nature and the growth mechanism of extended defects reported in the widely studied keV implantation energy range could be extrapolated in the MeV range, the thermal evolution of extended defects formed after MeV hydrogen implantation in (100) Si was investigated in this study. Samples were implanted at 1 MeV with different fluences ranging from 6 x 10(16) H/cm(2) to 2 x 10(17) H/cm(2) and annealed at temperatures up to 873 K. By cross-section transmission electron microscopy, we found that the nature of extended defects in the MeV range is quite different of what is observed in the keV range. In fact, in our implantation conditions, the generated extended defects are some kinds of planar clusters of gas filled lenses, instead of platelets as commonly reported in the keV energy range. This result underlines that hydrogen behaves differently when it is introduced in silicon at high or low implantation energy. The activation energy of the growth of these extended defects is independent of the chosen fluence and is between (0.5-0.6) eV, which is very close to the activation energy reported for atomic hydrogen diffusion in a perfect silicon crystal. (C) 2017 Elsevier B.V. All rights reserved.

Non-planar Fin Field Effect Transistors (FinFET) are already present in modern devices. The evolution from the well-established 2D planar technology to the design of 3D nanostructures rose new fabrication processes, but a technique capable of full characterization, particularly their dopant distribution, in a representative (high statistics) way is still lacking. Here we propose a methodology based on Medium Energy Ion Scattering (MEIS) to address this query, allowing structural and compositional quantification of advanced 3D FinFET devices with nanometer spatial resolution. When ions are backscattered, their energy losses unfold the chemistry of the different 3D compounds present in the structure. The FinFET periodicity generates oscillatory features as a function of backscattered ion energy and, in fact, these features allow a complete description of the device dimensions. Additionally, each measurement is performed over more than thousand structures, being highly representative in a statistical meaning. Finally, independent measurements using electron microscopy corroborate the proposed methodology.

Improving the thermal stability of Ni/GeSn intermetallics is of great importance to avoid surface degradation and Sn segregation. For this purpose, we studied the effects of pre-amorphization by ion implantation (PAI) of GeSn layers prior to metallization. The impact of Si, Ge, C, or Ge + C PAI was evaluated in terms of phase sequence, morpohological, and electrical evolution during the solid-state reaction. The overall phase sequence, followed by in situ x-ray diffraction, was comparable with or without PAI and went as follows: the Ni 5(GeSn) 3 hexagonal phase was obtained first, followed by the mono-stanogermanide phase: Ni(GeSn). Nevertheless, the threshold temperature for phase formation varied. These variations, depending on the nature of the implanted ions, can be related to kinetic and/or thermodynamic factors as supported by the analysis of bibliography for silicides and germanides. Additionally, it was reported that the use of Si or Ge implantation did not significantly impacted the surface morphology of the layers. On the other hand, the implantation of C positively impacts the surface morphology evolution by delaying Sn long-range diffusion and Ni(GeSn) agglomeration. This trend was then highly beneficial for preserving electrical stability in an enhanced process window.

Bulk silicon device technologies are reaching fundamental scaling limitations. The 28 nm and 22 nm technology nodes have seen the introduction of Ultra-Thin Body and Buried Oxide Fully Depleted SOI (UTBB-FDSOI) [1] and FinFETs [2], respectively. Fully Depleted transistor technologies are mandatory to suppress short channel effects. Today, all major research and development alliances carry the message that the silicon and its Fully Depleted transistor technologies have the potential to address roadmap requirements down to the 10 nm node. High mobility materials are expected to replace silicon as the channel material: attention has recently been focused on III-V (such as GaAs or InGaAs) and germanium (Ge). Ge has a privileged status: indeed, it belongs to column IV of Mendeleiev Table and it is a good candidate for high mobility p-channel and n-channel devices. Hole mobility (respectively electron mobility) in bulk Ge is indeed roughly 4 times (2 times) that in bulk Si. Nevertheless, changing from Si to Ge influences more than just the on-state current. The smaller bandgap value of Ge (0.66 eV versus 1.12 eV for Si) increases the junction leakage, and may therefore lead to a significant increase in the transistor off-state current [3-4]. SiGe alloy material with a high Ge ratio is a good compromise. Recently high-Ge-content (HGC) SiGeOI finFET have been demonstrated with record mobility values and good cut-off behavior [5] indicating the potential of such a channel material. In this paper, we will present our work on 300 mm SiGe-on-insulator (SiGe-OI) substrates with high Ge concentrations (70%). The process flow is illustrated in Fig.1. The standard SOI Smart CutTM process has been adapted for SiGe-OI substrates. The first focus is on the donor substrate and the SiGe epilayers. The donor surface quality should be carefully controlled and optimized before the bonding step. Fig. 2 shows the X-ray reflectivity measurements on the top layers of the Si0.3Ge0.7stack at the end of the epitaxial process steps. The significant interference fringes indicate the good quality of the different surfaces and interfaces which is confirmed by the roughness measurement (Atomic Force Microscopy image in Fig. 2 - right) with a Root Mean Square (RMS) roughness value as low as 0.18 nm on top of the donor substrates. The bonding process and the adapted Hydrogen-induced layer transfer inside the HGC SiGe layer will be presented. The second focus is on the finishing process steps to obtain the desired HGC SiGe-OI substrate. To ensure a good thickness control, the combination of multi-layer donor materials and selective chemical etching process has replaced the polishing removal process. As shown in Fig. 3, it enables to reach a SiGe-OI layer of 56 nm with a uniformity of +/- 3.5 nm at a 300 mm substrate scale. Final RMS surface roughness as low as 0.3 nm is obtained on finished HGC SiGe-OI substrate. Acknowledgment: The authors are grateful for the support given by the European Commission (ECSEL-WAYTOGO FAST 662175) [1] J. Hartmann, FDSOI workshop, 2012 [2] C. Auth, VLSI-T, 2012 [3] C. Claeys and E. Simoen, Eds., Germanium-based technologies – From materials to devices. Elsevier, 2007. [4] G. Eneman, ESSDERC 2007. [5] Hashemi, VLSI 2015. Figure 1

The use of plasma immersion ion implantation (PIII) is a relevant approach for the development of advanced solar cells technologies at lower cost (€/W p ). In this paper, we report on the development of homogeneous boron (B) doping of n-type crystalline silicon (cSi) substrate by the PIII technique. Using diborane (B 2 H 6 ) as gas precursor, various doping profiles were identified fitting the requirements for boron-doped emitters in n-type PERT solar cells. Particularly, saturation current density (J 0e ) of 50 fA/cm 2 were achieved on symmetrical samples for a 94 Ω/sg textured B-emitter passivated with SiO 2 /SiN stack. Bifacial n-type Passivated Emitter Rear Totally-diffused (n-PERT) solar cells were fabricated using the PIII technology and conversion efficiencies up to 19.8% on 239 cm 2 Cz-Si wafers were obtained. As a consequence, these results indicate that PIII can compete with beamline technology but will have lower running cost. It is therefore a promising technology to create high efficiency cSi solar cells.

3D sequential integration enables the full use of the third dimension thanks to its unique contact density far above the possibilities of 3D packaging solutions. However, as the transistors are sequentially stacked over each other, the thermal budget allowed for the fabrication of the top transistor is limited by the maximal temperature accepted by the already made bottom one. It was previously described that a thermal budget of T > 500 °C is enough to degrade the bottom transistors performance. So the technological challenge is to develop low temperature routines for the fabrication of the top devices. For that, different processes have to be adapted, mainly the dopant activation step, where the T > 1000 °C spike annealing must be replaced. In this contribution, we present the feasibility to dope by solid phase epitaxial regrowth (SPER) at 450 °C thin Si films (22 nm) containing high dopant concentration of 5 × 10 20 at/cm 3 . For n- and p-type dopants, the 450 °C SPER rendered low sheet resistance values, as low as the ones obtained with the high temperature activation method.

We have studied the influence of thermal treatments on the redistribution of Mg implanted in GaN on Si. SIMS results highlights the strong effect of Mg concentration on its diffusion behaviour. In the range of 1018 at/cm3 or below, the Mg distribution is not modified after annealing up to 1100°C. In the order of 1019 at/cm3 or higher, such thermal treatment lead to fast diffusion of the implanted Mg in the [0001] direction and a trapping of the Mg at the GaN/capping layer interface. AFM analysis of the GaN surface after capping etching suggest that emerging dislocations are favourable diffusion path for Mg toward the GaN surface. APT analysis reveals that this diffusion behavior go-on with the formation of Mg rich clusters containing about typically a hundred atoms in our process conditions. This diffusion and aggregation behaviors are specific to the Mg specie and have to be taken into account to expect successful integration of p type doping process via Mg implantation in GaN on Si.

International audience

International audience; The interaction of a propagating crack in implanted silicon with self-emitted acoustic waves is studied and reveals the generation of periodic patterns on wafers surfaces after separation. The measurement and identification of the acoustic waves have been experimentally achieved showing the emergence of dominant shear waves acoustic frequencies related to the crack velocity. The surface modifications are made of roughness modulations at large scale due to periodic deviations of the crack front. A physical mechanism explaining the pattern formation is proposed accounting for the observed wavelengths.

session 32: Process and Manufacturing Technology (32.2); International audience; For the first time, a low temperature (LT) FinFET process is demonstrated, using Solid Phase Epitaxy Regrowth (SPER), gate last integration and Self Aligned Contact (SAC). The LT devices exhibit performances close to those of the High Temperature Process Of Reference (HT POR). Several techniques of SPER doping are investigated and an innovative Double SPER (DSPER) process using two amorphization/recrystallization steps, is demonstrated. This DSPER process has the advantage of doping the bulk of the S/D junctions. This work opens the door to the fabrication of high-performance LT FinFETs for 3D sequential integration.

session: Monolithic 3D 3; International audience; This work investigates the possibility to reduce the Solid Phase Epitaxy Regrowth (SPER) temperature for dopant activation needed in 3D sequential integration. The electrical results obtained on 28nm FDSOI devices show that 500°C SPER can yield similar performance to that of 600°C SPER and 1050°C spike anneal. This paper highlights the advantages of using a -oriented channel and tilted implantation to successfully reduce the SPER thermal budget. It also confirms that the channel can be used as a seed for the recrystallization. The analysis takes into account the SPER rate dependence on temperature, crystalline orientation, dopant type and dopant concentration.

Localized p-doping is a keystone in the development of many GaN based devices that need selectively doped pocket area such as MOSFETs or PIN diodes. Electrical activation of implanted Mg has been obtained lately with GaN grown on sapphire substrate using an AlN based protective layer combined with multi cycle of rapid thermal annealing at very high temperature (>1300 °C) proving the feasibility and interest of the method [1]. The use of Si (111) substrate allows a better integration of the process on microelectronic production line. However the growth of GaN on Si (111) is less mature and necessitates a buffer usually composed of a complex staking based on AlN intermediate layers [2]. The difference in lattice parameters and thermal extension coefficient in the stacking may make the samples more unstable during the high thermal budget required for doping activation. In the last few years, several groups focused their research on the prevention of GaN surface degradation at high temperature [3] and we have shown that a combination of in situ epi deposited AlN and SiN thin layers is very efficient to avoid this phenomena [4]. Here, we propose to study the impact of high thermal annealing on the evolution of the damage in Mg-implanted GaN (on Si). Indeed, comprehensive studies of the GaN healing mechanism in this kind of structures are not yet reported. We use samples of GaN layer grown by MOCVD on Si (111) using an AlN based buffer layer and protected by an AlN/SiNx cap layer. These samples are implanted with Mg fluences ranging from 1013 to 1015 at/cm² corresponding to maximum effective concentration between 5.1017 and 5.1019 at/cm3 in the implanted layer. 400 °C -1100 °C anneals are proceeded in controlled N2 atmosphere. X-Ray Diffraction (XRD) and Photoluminescence (PL) measurements point out that ion implantation induced damage are healed thanks to different mechanisms: both lattice strain relaxation and point defect annihilation can occur during annealing with different kinetics. Indeed as we can see on Fig.1a, on samples implanted with low to medium fluence (up to 1014 at/cm²), relatively low temperature anneals (< 450 °C) are enough to obtain a near complete correction of the lattice deformation. However, surprisingly, the PL spectra of 400 °C annealed samples shown on Fig1.b indicates that a lot of non-radiative defects are still present and shutting down the PL intensity. The spectra of the sample annealed at 1100°C exhibits bands characteristic of Mg in Ga site (Mg(Ga)) which proves the necessity of a higher thermal treatment to reduce non radiative defects concentration and promote Mg incorporation in the GaN lattice. As shown on Fig 2.a, an increase of the fluence (1015 at/cm²) leads to an increase of the induced strain but also of the temperature necessary to fully relax it (1100°C). However, the PL spectra (Fig 2.b) indicates that even after such a high thermal treatment, the PL intensity of the bands associated with Mg(Ga) is weaker than for medium fluence despite the higher Mg concentration in the matrix [4]. We assume that this behavior may be due to residual damage. This is supported by Transmission Electron Microscopy images of the layer (not shown here) that evidence remaining defective pockets after a 1 h 1100 °C in N2 annealing. These results give insight on the healing mechanism occurring during the activation anneal of Mg implanted in GaN. They also highlight that damage management is a critical parameter for GaN (on Si) p-doping via Mg implantation. To reach this objective, we will show that it is necessary to implement further specific processes to limit the implantation induced damage and to improve the damage recovery efficiency. 1. Tadjer, M.J., et al., Selective p-type Doping of GaN:Si by Mg Ion Implantation and Multicycle Rapid Thermal Annealing. ECS Journal of Solid State Science and Technology, 2015. 5(2): p. P124-P127. 2. Charles, M., et al., The effect of AlN nucleation temperature on inverted pyramid defects in GaN layers grown on 200 mm silicon wafers. Journal of Crystal Growth, 2017. 464: p. 164-167. 3. El-Zammar, G., et al., Surface state of GaN after rapid-thermal-annealing using AlN cap-layer. Applied Surface Science, 2015. 355: p. 1044-1050. 4. Lardeau-Falcy, A., et al., Capping stability of Mg-implanted GaN layers grown on silicon. physica status solidi (a), 2016. Figure 1

H implantation in Si/Si:B/Si structures is a promising route to improve the Smart Cut™ process and transfer thin Si layers of reduced roughness and controlled thickness onto regular Si wafers. However, the mechanisms driving this process are unknown and thus difficult to model or optimize. For this reason, we have experimentally studied the redistribution of H which takes place in such structures after implantation and during annealing using SIMS and TEM. We show that the Si:B layer already traps H during implantation and form platelets parallel to the wafer surface. During annealing, the H atoms implanted in the Si regions are slowly transferred toward the Si:B layer where they are trapped on large platelets which grow further during annealing. Routes to optimize this process go through the minimization of H precipitation in the pure Si regions. This can probably be achieved by optimizing the implantation conditions.

International audience; Production costs and energy efficiency are the main priorities for the photovoltaic (PV) industry (COP21 conclusions). To lower costs and increase efficiency, we are proposing to reduce the number of processing steps involved in the manufacture of N-type Passivated Rear Totally Diffused (PERT) silicon solar cells. Replacing the conventional thermal diffusion doping steps by ion implantation followed by thermal annealing allows reducing the number of steps from 7 to 3 while maintaining similar efficiency. This alternative approach was investigated in the present work. Beamline and plasma immersion ion implantation (BLII and PIII) methods were used to insert n-(phosphorus) and p-type (boron) dopants into the Si substrate. With higher throughput and lower costs, PIII is a better candidate for the photovoltaic industry, compared to BL. However, the optimization of the plasma conditions is demanding and more complex than the beamline approach. Subsequent annealing was performed on selected samples to activate the dopants on both sides of the solar cell. Two annealing methods were investigated soak and spike thermal annealing. Best performing solar cells, showing a PV efficiency of about 20%, was obtained using spike annealing with adapted ion implantation conditions.

The Smart Cut™ technology [1] is currently the industry standard for manufacturing Silicon-On-Insulator (SOI) wafers. The implantation of relatively high doses of hydrogen ions in a silicon substrate leads to the formation of a buried weakened layer. This wafer is bonded onto a host substrate using direct wafer bonding. Under annealing, the implanted species evolve into microcracks lying parallel to the surface, and finally, a controlled fracture process occurs along the implanted layer. While Si/SiO2 direct wafer bonding statics and dynamics have been extensively studied [2],[3], the fracture dynamics during Smart Cut™ remains largely a field to be explored. Since the SOI standard thickness for microelectronics devices is always decreasing, the detailed understanding of the fracture becomes of greater interest e.g. to improve the post-split SOI wafer surfaces. In this paper, the crack propagation during the silicon layer transfer of the Smart Cut™ process is studied using an original patented optical bench[4] (Fig.1). The measurements are based on the transmission monitoring of infrared laser beams through the sample when the fracture wave front crosses the beams. The crack can be mechanically initiated by inserting a blade between the two wafers or thermally initiated by putting the sample into an appropriate oven. Combination of the two split modes is also possible. This set up allows the determination of the crack propagation velocity which is typically in the km.s-1 range. An in-depth study of the post wave front signal oscillations (Fig.2) enabled us to recover the deformation profile of the sample just after the fracture front has gone through it (Fig.3). At first, the two newly separated wafers drift away because of the strong internal pressure of the gas filled microcracks. The energy released during the crack opening separates the silicon beams by several micrometres, until reaching a maxima where the external atmospheric pressure becomes large enough to stop the two silicon arms diverging movement. Subsequently the motion will invert and the wafers will get closer again and reach a minima where the internal pressure will enable the two beams to pull away. Therefore, the wave crack "wake" is made of series of oscillations until the internal pressure equilibrates to the atmospheric one. The typical wavelength of such deformations is about several centimetres, while the vertical speed of displacement is quite slow, around 1µm.µs-1. The dynamics of this motion has been successfully modelled using beam elasticity and thermodynamics. From the modelling, it is e.g. possible to recover the amount of gas trapped inside the microcracks and better understand the driver of Smart Cut™ splitting technique. References: [1] US 5374564, B. Michel, "Process for the production of thin semiconductor material films”, (1994) [2] F. Rieutord, B. Bataillou and H. Moriceau, Phys. Rev. Lett., 94, pp. 236101, (2005). [3] H. Moriceau, F. Rieutord, F. Fournel, Y. Le Tiec, L. Di Cioccio, C. Morales, A.M. Charvet, and C. Deguet. Adv. Nat. Sci.: Nanosci. Nanotechnol., 1(2010) 043004 [4] WO 2013/140065, F. Mazen, F. Rieutord, J.D. Penot, P. Montmayeul, “System for measuring a zone of separation in a substrate”, (2011)

In this work, we demonstrate for the first time a 300-mm indium–gallium–arsenic (InGaAs) wafer on insulator (InGaAs-OI) substrates by splitting in an InP sacrificial layer. A 30-nm-thick InGaAs layer was successfully transferred using low temperature direct wafer bonding (DWB) and Smart CutTM technology. Three key process steps of the integration were therefore specifically developed and optimized. The first one was the epitaxial growing process, designed to reduce the surface roughness of the InGaAs film. Second, direct wafer bonding conditions were investigated and optimized to achieve non-defective bonding up to 600 °C. Finally, we adapted the splitting condition to detach the InGaAs layer according to epitaxial stack specifications. The paper presents the overall process flow that achieved InGaAs-OI, the required optimization, and the associated characterizations, namely atomic force microscopy (AFM), scanning acoustic microscopy (SAM), and HR-XRD, to insure the crystalline quality of the post transferred layer.

We have studied the development of cracks in gas-implanted silicon, from nano-scale to wafer-scale which is at the heart of the SmartCut™ technology. We will discuss the results of X-ray scattering experiments that allow the monitoring of growth of nanometer-size cavities (platelets) from implantation to their full development where they reach sizes of several tens of nanometers. The nucleation, growth and coarsening mechanisms of these nanometer size platelets are interpreted within the Ostwald ripening framework. At larger annealing times, some micron-size defects called microcracks appear, and experience again some competitive growth, dominated by coalescence. The growth of these micron-size objects depends on their interactions with smaller-size platelets. The modelling of this interaction can explain the dependance of split time with temperature. Microcrack development is a key step in the SmartCut™ process. Finally the propagation of the fracture front will be discussed. We will discuss the velocity dependence of the crack front with temperature and present some new measurements of dynamic crack opening displacement. Figure 1

International audience; 3D sequential integration requires top FETs processed with a low thermal budget (500-600°C). In this work, high performance low temperature FDSOI devices are obtained thanks to the adapted extension first architecture and the introduction of mobility boosters (pMOS: SiGe 27% channel / SiGe:B 35% RSD and nMOS: SiC:P RSD). This first demonstration of n and p extension first FDSOI devices shows that low temperature activated device can match the performance of a device with state-of-the-art high temperature process (above 1000°C).

In this paper, we report on implantation parameters allowing the delamination of large surface of ultra-thin silicon substrates by using MeV hydrogen implantation. We particularly focus on the effects of both hydrogen fluence and implantation energy, on the size of the largest delaminated surface in one piece. We demonstrate that thin silicon substrates with thicknesses between 30 µm and 70 µm can be extracted from silicon commercial wafers. In this study, the used-material, the implantation energy and the hydrogen fluence ranges are (100) Si, 1.5 MeV-2.5 MeV, 1×1017cm–2-2×1017cm–2, respectively. We find that, by increasing hydrogen fluence, the maximum achievable surface of delaminated substrates in one piece can be doubled. Indeed, by XTEM, we observed that fracture precursor defects are mostly oriented along {111} in the case of the lowest fluence, which are unfavorable for a good surface-parallel crack propagation. For the highest fluence, precursors are oriented along {100} which are parallel to the substrate surface, therefore they allow propagation over longer distances of cracks parallel to the substrate surface. We also find that, despite of the raise of the proportion of precursors oriented along {111}, the total surface of delaminated substrates significantly increases with the implantation energy. (© 2016 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

The doping of n-type silicon solar cells was investigated using two ion implantation techniques: beam line and plasma immersion. Initially, we evaluated the benefits of beamline ion implantation in replacement of diffusion anneal doping process. Two different annealing routines were studied. The first one using a single annealing to activate both B implanted emitter and P implanted BSF, while the second one used two different annealing to separately activate each dopant. Good yield was reached with a record cell of 20.33% efficiency. Secondly, we investigated the doping by plasma immersion ion implantation where the final objective was the fabrication of a solar cell fully doped by plasma. BF3 and B2H6 were compared as precursor gases for the boron emitter doping, while PH3 was used for the BSF doping. Hybrid cells were fabricated using both implantation techniques and a maximum efficiency of 19.8% was obtained. First cells fully doped by plasma shown promising results with a yield of 18.8%.

This paper reports the first demonstration of 300 mm In0.53Ga0.47As-on-insulator (InGaAs-OI) substrates. The use of direct wafer bonding and the Smart Cut™ technology lead to the transfer of high quality InGaAs layer on large Si wafer size (300 mm) at low effective cost, taking into account the reclaim of the III–V on Si donor substrate. The optimization of the three key building blocks of this technology is detailed. (1) The III–V epitaxial growth on 300 mm Si wafers has been optimized to decrease the defect density. (2) For the first time, hydrogen-induced thermal splitting is made inside the indium phosphide (InP) epitaxial layer and a wide implantation condition ranges is observed on the contrary to bulk InP. (3) Finally a specific direct wafer bonding with alumina oxide has been chosen to avoid outgas diffusion at the alumina oxide/III–V compound interface.

High energy protons implantation in the 1-3 MeV range can be used to detach free-standing thin silicon films with thickness between 15 and 100 µm. Recently, we showed that Si orientation has a strong effect on the layer separation threshold fluence and efficiency. While complete delamination of (111)Si films is achieved, (100)Si films separation is more challenging due to blistering phenomena or partial separation of the implanted layer. In this work, we study the fracture mechanism in (100)Si after high energy implantation in order to understand the origin of such a behaviour. We notably point out that fracture precursor defects, i.e. the platelets, preferentially form on (111) planes, as a consequence of the low strain level in the damaged region in our implantation conditions. Despite this unfavourable precursors orientation, fracture propagation in (100)Si can be achieved by increasing the hydrogen fluence. (© 2012 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim)

Proton implantation in silicon and subsequent annealing are widely used in the Smart Cut™ technology to transfer thin layers from a substrate to another. The low implantation energy range involved in this process is usually from a few ten to a few hundred of keV, which enables the separation of up to 2 μm thick layers. New applications in the fields of 3D integration and photovoltaic wafer manufacturing raise the demand for extending this technology to higher energy in order to separate thicker layer from a substrate. In this work, we propose to investigate the effect of proton implantation in single crystalline silicon in the 1–3 MeV range which corresponds to a 15–100 μm range for the hydrogen maximum concentration depth. We show that despites a considerably lower hydrogen concentration at R p , the layer separation is obtained with fluence close to the minimum fluence required for low energy implantation. It appears that the fracture propagation in Si and the resulting surface morphology is affected by the substrate orientation. Defects evolution is investigated with Fourier Transform Infrared Spectroscopy. The two orientations reveal similar type of defects but their evolution under annealing appears to be different.

The Smart Cut™ process technology was originally developed to manufacture silicon on insulator wafers (SOI). The process is based on ion implantation (hydrogen, helium, argon, etc.) and wafer bonding and allows single crystal layers transferred onto substrates. This generic process is suited for creating advanced or composite engineered wafers, combining different thin layer materials on a given substrate in order to address requirements of many diverse applications. This article is first focused on hydrogen ion implantation impacts and on mechanisms enabling splitting for silicon layer transfer. Using transmission electron microscopy, infrared spectroscopy and X-ray diffraction, the formation and evolution of extended defects formed in Si has been studied, from the as-implanted state to the splitting. Mechanism for platelet growth by Ostwald ripening, diffusion of atomic hydrogen to molecular hydrogen in the microcavities and mechanic effects (stress, gas pressure) leading to microcavity expansion, microcrack propagation and splitting are detailed in the specific case of thermal annealing. Splitting kinetics and mechanisms are deduced. Then window on other natures of implanted ions is opened and described for co-implantation for instance. Advantages of such as (H, He) co-implantation are highlighted as it allows high crystal quality of transferred layer and fast splitting kinetics. Finally, diverse applications are described to illustrate the versatility of the Smart Cut™ process with other materials than silicon.

In this work we demonstrate for the first time 300 mm InGaAs on Insulator (InGaAs-OI) substrates. A 30 nm thick InGaAs layer was successfully transferred using low temperature Direct Wafer Bonding (DWB) and the Smart CutTM technology. The epitaxial growing process has been optimized to reduce the surface roughness of the InGaAs film at around 1.5 nm RMS. HR-XRD characterization on the transferred InGaAs layer indicates that the layer remains crystalline.

SOITEC, Parc Technologique des Fontaines, F38190, Bernin, France The recent progress in the fabrication of GeOI substrates and devices is reviewed. Improvements have been made in threading dislocation density, Ge-buried oxide interface passivation, device performance. The potential of various co-integration schemes (lateral and vertical) has been illustrated as alternatives to the fabrication of n-type germanium channel devices. GeOI is also shown to be a versatile platform for the monolithic integration of Si and III-V devices and tunneling field effect transistors.

International audience; Crack propagation in implanted silicon for thin layer transfer is experimentally studied. The crack propagation velocity as a function of split temperature is measured using a designed optical setup. Interferometric measurement of the gap opening is performed dynamically and shows an oscillatory crack "wake" with a typical wavelength in the centimetre range. The dynamics of this motion is modelled using beam elasticity and thermodynamics. The modelling demonstrates the key role of external atmospheric pressure during crack propagation. A quantification of the amount of gas trapped inside pre-existing microcracks and released during the fracture is made possible, with results consistent with previous studies. (C) 2015 AIP Publishing LLC.

We have investigated the effects of hydrogen implantation in silicon wafers by x-ray scattering methods. Different crystalline orientations for the Si single crystals were studied, namely (100), (110) and (111) Si. Large strains normal to the surface were evidenced after implantation, which depends on the Si orientation and can be explained on the basis of the different alignment of the Si-Si bonds with respect to the crystal surface. A comparison with the results from infrared spectroscopy shows that strain is associated to specific H- related point defects, such as monohydride multivacancy and H2*. Finally the evolution of the stressed structure during annealing is discussed.

Germanium-on-insulator (GeOI), which combines high mobility of charge carriers with the advantages of an SOI structure, is an attractive integration platform for the future IC technology. Also, due to its low lattice mismatch with GaAs, III–V compounds transistors as well as optoelectronic functions can be integrated on GeOI. In this paper, we review GeOI fabrication methods, and then applications that utilize GeOI wafers. The Smart Cut™ layer transfer technology is found to be the best method to form wafer-level GeOI structures of different diameters and thickness range down to

An atomic force microscopy (AFM) tip has been used to manipulate silicon nanocrystals deposited by low-pressure chemical vapour deposition on thermally oxidized p-type Si wafer. Three nanomanipulation methods are presented. The first one catches a nanocrystal with the AFM tip and deposits it elsewhere: the tip is used as an electrostatic 'nano-crane'. The second one simultaneously manipulates a set of nanocrystals in order to draw well-defined unidimensional lines: the tip is used as a 'nano-broom'. The third one manipulates individual nanocrystals with a precision of about 10 nm using both oscillating and contact AFM modes. Switching from strong interaction forces (chemical) to weak ones (van der Waals, electrostatic or capillarity) is the basis of these manipulation methods. We have applied the second method to connect two electrodes drawn by e-beam and lift-off with a 70 nm long silicon nanocrystal chain. Current versus voltage characterization of the nanofabricated device shows that the increase in nanocrystal density gives rise to conduction between the connected electrodes. Resonant tunnelling effects resulting from Si nanocrystal (nc-Si) multiple tunnel junctions have been observed at 300 K. We also show that offset charges directly influence the position of the resonant tunnelling peaks. Finally, the possibility of manipulating nc-Si with a diameter of around 5 nm is shown to be a promising way to fabricate single electron devices operating at room temperature and fully compatible with silicon technology.

We present a study of the influence of H2 as a carrier gas on the nucleation and growth of silicon quantum dots (Si-QDs) on SiO2 by chemical vapor deposition (CVD). Compared to deposition from pure SiH4, the dilution of SiH4 in H2 leads to a strong decrease of the nucleation/growth rate, with the same Si-QDs morphology however. The effects of doping gas, phosphine and diborane, on Si-QDs nucleation and growth were also investigated. Silanol groups at the SiO2 surface were identified as nucleation sites for Si-QDs. We study the influence of H2 and doping gases on their activity toward Si-QDs nucleation.

We present a study of the influence of H 2 as a carrier gas on the nucleation and growth of silicon quantum dots (Si-QDs) on SiO 2 by CVD. Compared with Si-QDs deposition from pure SiH 4 , the dilution of SiH 4 in H 2 leads to a strong increase of the deposition time without significant modification of the Si-QDs morphology. The effects of doping gas, phosphine and diborane on Si-QDs nucleation and growth are also investigated. We show that the nucleation of Si-QDs is strongly dependent on the SiO 2 substrate surface chemistry. Si–OH groups are identified as nucleation sites for Si-QDs. We study the influence of H 2 carrier gas and doping gases on their impact on Si-QDs nucleation.

We present a study of nucleation and organization of Si quantum dots (Si QDs) grown on insulating layers. The samples were investigated by scanning electron microscopy, high-resolution transmission electron microscopy, and scanning tunneling microscope (STM). We demonstrate that the chemical nature of the surface influences the Si QDs nucleation. We have organized the Si QDs using a buried array of dislocations obtained by molecular bonding of Si wafers. The electrical properties of individual Si QDs were investigated and memory effects were shown in C-MOS transistors integrating Si QDs within the gate oxide.

The morphological stability during activation annealing of Mg-implanted GaN layers (2 μm thick) grown on Si (111) is studied for several protective layers and fluencies in the 1013–1015 at. cm−2 range. We show that a thin capping, composed of a few nanometer thick AlN and SiNx stacks grown in situ just after GaN deposition, provides a good solution to retain flat morphology and no strain cracking up to 1 h annealing at 1100 °C in N2. These results are compared to thicker protective stackings with AlN layers of Si3N4 or SiO2 deposited after the implantation that withstand a thermal budget of up to 1 h at 1200 °C in N2. The efficiency of these different cap layers to limit GaN damage during high-temperature annealing is studied as well as the impact of Mg implantation process on the cap resilience. The quality of the GaN sublayer is studied by low-temperature photoluminescence to analyze structural/optical defects and Mg related complexes. X-ray diffraction is performed to evaluate residual strains at the different process stages.

Nonvolatile memory structures using Ge nanocrystals embedded in SiO2 have been characterized by room and low temperature current–voltage and capacitance–voltage measurements. The Ge nanocrystals have been fabricated by low pressure chemical vapor deposition process which is shown to be well suited for a real control of the tunnel oxide thickness. The deposition conditions allow a separate control of nc-Ge density and size. Using capacitance–voltage characterizations on nonvolatile memory structures, we have measured the charging and discharging kinetics of holes for tunnel oxides in the range 1.2–2.5 nm. Using current–voltage measurements and simulations, we have also shown that nc-Ge are at the origin of a tunnel-assisted current. Simulations have demonstrated that the hole’s charging effects strongly reduce the current density across the nonvolatile memory structure. Combined with a good control of nc-Ge properties, the use of Ge dots with large diameters (>10 nm) seems to be a promising way for p-type ...

We present a detailed study of the growth of Ge nanocrystals (NCs) on SiO2 by chemical vapor deposition. A two-step process was developed. First, Si nuclei are deposited on SiO2 using SiH4 as a gaseous precursor. Then, Ge NCs grow selectively on the Si nuclei previously formed. The density of the Ge NCs is adjustable in between 109 and 1012 cm−2. Their mean size varies between 5 and 50 nm. We have shown, combining grazing incidence x-ray diffraction and x-ray photoelectron spectroscopy, that pure Ge NCs are grown in a polycrystalline phase on a SiO2 surface.

We present a detailed study of the growth of Si quantum dots (Si QDs) by low pressure chemical vapor deposition on alumina dielectric deposited by atomic layer deposition. The Si QDs density is very high, 1012 cm−2, for a mean diameter between 5 and 10 nm. Al2O3/Si QD stacks have been integrated in memory devices as granular floating gate. The devices demonstrate good charge storage and data retention characteristics.

High energy protons implantation in the 1-1.5 MeV range can be used to detach free-standing thin silicon films with thickness between 15 and 30 μm. Recently, we showed that Si orientation has a strong effect on the layer separation threshold fluence and efficiency. While complete delamination of (111)Si films is achieved, (100)Si films separation is more challenging due to blistering phenomena or partial separation of the implanted layer. In this work, we study the fracture mechanism in (100) and (111)Si after high energy implantation in order to understand the origin of such a behavior. We notably point out that fracture precursor defects, i.e. the platelets, preferentially form on (111) planes, as a consequence of the low strain level in the damaged region in our implantation conditions. Fracture therefore propagates easily in (111)Si, while it requires higher fluence to overcome unfavorable precursors orientation and propagate in (100)Si.

Substrate Requirements & Product Roadmap Bulk silicon device technologies are reaching fundamental performance scaling limitations. To support Fully-Depleted SOI design introduction at 28nm node, SmartCut® technology has demonstrated in the past years its capability to deliver ultra-thin SOI (i.e ultra-thin silicon and ultra-thin buried oxide) substrates, in volume production mode with high quality and ultra-low roughness. [1, 2] These UTBOX (or UTBB) materials are routinely prepared with a typical SOI layer of 12nm thick controlled wafer to wafer and across the wafer at maximum +/- 0.5 nm. Buried Oxide layer can be thinned down to 10nm. Silicon on Insulator technology can also be adapted for other device architectures, such as FinFet on SOI. However, even if Silicon & Fully Depleted technology can support the electrostatic scaling down to 14nm node, material innovation is necessary for advanced technologies such as node 10nm and beyond. Strained-SOI material already demonstrates some of its substrate capability [3], performance benefit [4] and integration advantages [5] for 10nm FDSOI MOSFET. High mobility is also targeted using Germanium-rich materials, already known for extremely high hole mobility and low hole effective mass. [6] Thus SiGeOI material is included in product roadmap, as shown on Figure 1. This paper will report latest achievement in sSOI, GeOI, & SiGeOI materials preparation, developed to support technology nodes beyond 10nm. Substrate Preparation Fig. 2 shows typical SmartCut ® process, adapted for sSOI, GeOI & SiGeOI material preparation. It benefits of previous FDSOI developments optimizing buried oxide growth, ionic implant, bonding & splitting process steps for highly uniform thin layer transfer. It introduces engineered donor wafer including SiGe and/or strained-silicon Epi layers. Refresh process is also adjusted, to be able to re-use donor epitaxy, optimizing material cost & quality. During finishing process, specific steps including polishing, thermal treatment & cleanings are introduced to manage stress & germanium. GeOI Substrate Demonstration Fig. 3a shows TEM cross section of GeOI material, including 10nm Oxide capping, 60nm Ge layer and 150nm Buried Oxide. No crystal defect is observed by cross-sectional TEM. Using chemical etching for defect delineation, Threading Dislocation density, numbered from optical microscope view as on Fig. 3b, is estimated in E7 cm-2range. SiGe0.70OI Substrate Demonstration Germanium concentration on finished product, 70% on current development samples, is determined by donor epitaxy layer.To ensure tight thickness control, in addition to excellent Epitaxy uniformity & optimized SmartCut process, SiGeOI finishing process step implements the selective chemical etching instead of using the substantial polishing removal process as previously reported for GeOI substrate preparation.[7] As shown in Fig. 4a, it enables to reach the SiGe layer uniformity better than +/- 8% on 300mm substrates. Finished SiGeOI surface roughness is also characterized using 30x30 µm² AFM with a RMS value lower than 3 A (Fig. 4b). References [1] W. Schwarzenbach et al., ECS Trans., vol. 45, p.227, 2012 [2] W. Schwarzenbach et al., ECS Trans., vol. 53, p.39, 2013 [3] W. Schwarzenbach et al, ICICDT 2012 [4] A. Khakifirooz et al, VLSI Symp. 2012 [5] F. Andrieu et al, VLSI Symp. 2014 [6] S. Takagi, IEEE TED, 2008 [7] J. Widiez et al, ECS Trans., Vol. 64, p 35, 2014 Figure 1