Search

A class of deformation processing applications based on the severe plastic deformation (SPD) inherent to chip formation in machining is described. The SPD can be controlled, in situ, to access a range of strains, strain rates, and temperatures. These parameters are tuned to engineer nanoscale microstructures (e.g., nanocrystalline, nanotwinned, and bimodal) by in situ control of the deformation rate. By constraining the chip formation, bulk forms (e.g., foil, sheet, and rod) with nanocrystalline and ultrafine grained microstructures are produced. Scaling down of the chip formation in the presence of a superimposed modulation enables production of nanostructured particulate with controlled particle shapes, including fiber, equiaxed, and platelet types. The SPD conditions also determine the deformation history of the machined surface, enabling microstructural engineering of surfaces. Application of the machining-based SPD to obtain deformation-microstructure maps is illustrated for a model material system--99.999% pure copper. Seemingly diverse, these unusual applications of machining are united by their common origins in the SPD phenomena prevailing in the deformation zone. Implications for large-scale manufacturing of nanostructured materials and optimization of SPD microstructures are briefly discussed. [DOI: 10.1115/1.4001665] Keywords: machining, nanostructured materials, severe plastic deformation, particle

In this technical note, we demonstrate a squeeze-film based spacer-free method for creating controllable submicrometer hydrogel films on planar substrates that can be used to photolithographically fabricate hydrogel microstructures. This new technique improves the photolithographic resolution and yield by providing a uniform and low-defect hydrogel film. The optimum polymerization initiation time for achieving such a layer was determined to be around 1 min. For patterning, the dried hydrogel film was coated with a parylene-C masking layer. Subsequent etching in oxygen plasma was used to transfer selected patterns of hydrogel to the substrate in a batch scale. 10.1021/ac100579v

Chip electrochemistry is one of the top ambitions of today's electrochemistry. Here, a study for manufacturing electrochemical microcells on chips in a cost-effective, facile, and mass-producible way is presented. The ultrasmall, planar electrochemical cells, ranging from 140 femtoliter to 14 attoiiter, can work independently as electroanalyfical devices with embedded functional microelectrodes. Electrochemical responses of the miniaturized cells have been characterized by cyclic voltammetry. Ideal steady-state voltammograms were recorded with femtoliter volume cells, indicating the domination of a radical diffusion regime and a greatly improved signal/ background ratio. Quasi-thin-layer behavior was observed for attoliter volume cells, which exhibited a special capability of offering accurately confined domains for redox processes. Positive feedback effect of the cells indicated that interactions between the close-by working and reference/counter microelectrodes can be well developed and potentially utilized for trace level electroanalysis. This study vividly offers i) a new protocol of electrochemical chip for applications, ii) a new tool for trace electroanalysis, and iii) a more approachable insight for single molecule electrochemistry in the near future. 10.1021/ac902681g

We find that the number of failing chips per wafer has a probability distribution with a consistent structure across multiple technologies and product types. We further show that a general extreme value provides an accurate and efficient means of describing this distribution. We also show that chips on a wafer tend to fail together, particularly if they are physically close to one another; this behavior results in dusters of failed chips on a wafer. A method for the direct measurement of clusters of fairing chips on a wafer is described, along with a model to relate this measurements to the distribution of the number of failing chips. The methods described here are potentially applicable for identifying wafer outliers or for monitoring of the manufacturing process. Index Terms--Clustering, faults, number of failing chips (NFC), yield.

Integrated circuit (IC) foundry fabs are difficult to model due to the increasing product mixes and flexible routes. An imprecise fab model cannot be used to evaluate fab performance or estimate product cycle time. The distributed colored timed Petri net (DCTPN) is a type of high-level Petri net with embedded entity attribute, time, communication, and remote object invocation properties that contribute to realistic descriptions, distributed modeling, and manufacturing execution system integration. Furthermore, the resource-oriented DCTPN modeling extends product mix and flexible route modeling capabilities. The DCTPN conflict resolution and token competition rules are used to construct the dispatching system for a controlled IC fab. A simplified 200 mm IC fab with six functional areas is discussed and demonstrated based on different control policies. Index Terms--Dispatching system, distributed colored timed Petri net (DCTPN), integrated circuit (IC) foundry fab, manufacturing execution system (MES), performance evaluation, semiconductor manufacturing.

This paper presents an adaptive control approach for achieving the control of the wafer temperature in a rapid thermal processing system (RTP). Numerous studies have addressed the temperature control problem in RTP and most researches on this problem require exact knowledge of the systems dynamics. However, it is difficult to acquire this exact knowledge. Thus, various approaches cannot guarantee the desired performance in practical application when there exist some modeling errors between the model and the actual system. In this paper, an adaptive control scheme is applied to RTP without exact information on the dynamics. The system dynamics are assumed to be an affine nonlinear form, and the unknown portion of the dynamics are estimated by a neural network referred to a piecewise linear approximation network (PLAN). The controller architecture is based on an adaptive feedback linearization scheme and augmented by sliding mode control. The performance of the proposed method is demonstrated by experimental results on an RTP system of Kornic Systems Corporation, Korea. Index Terms--Adaptive feedback linearization, PLAN, RTP, sliding mode control.

The exponentially weighted moving average (EWMA) feedback controller (with a fixed discount factor) is a popular run by run control scheme which primarily uses data from past process runs to adjust settings for the next run. Although the EWMA controller with a small discount factor can guarantee a long-term stability (under fairly regular conditions), it usually requires a moderately large number of runs to bring the output of a process to its target. This is impractical for process with small batches. The reason is that the output deviations are usually very large at the beginning of the first few runs and, as a result, the output may be out of process specifications. In order to reduce a possibly high rework rate, the authors propose a variable discount factor to tackle the problem. They state the main results in which the stability conditions and the optimal variable discount factor of the proposed EWMA controller are derived. An example is given to demonstrate the performance. Moreover, a heuristic is proposed to simplify the computation of the variable discount factor. It is seen that the proposed method is easy to implement and provides a good approximation to the optimal variable discount factor. Index Terms--Run by run process control, single EWMA controller, variable discount factor.

Sensitivity of critical transistor parameters to halo implant tilt angle for 0.14-[micro]m CMOS devices was investigated. [V.sub.th] sensitivity was found to be 3% per tilt degree. A tilt angle mismatch between two serial ion implanters used in manufacturing was detected by tracking [V.sub.th] performance for 0.14-[micro]m production lots. Even though individual implanters may be within tool specifications for tilt angle control ([+ or -]0.5[degrees] for our specific tool type), the relative mismatch could be as large as 1[degrees], and therefore, result in a [V.sub.th] mismatch of over 3% from nominal. The [V.sub.th] mismatch results are in qualitative agreement with simulation results using SUPREM and MEDICI software. Index Terms--CMOSFETs, halo implant, high tilt angle, ion implantation, SUPREM simulation.

This study examines the airflow and particle characteristics of a front opening unified pod/load port unit (FOUP/LPU) minienvironment system. The airflow and particle number were measured by using a three-dimensional ultrasonic anemometer and an He--Ne laser airborne particle counter, respectively. A large vortex is produced below an extracted wafer in the minienvironment. This vortex extends to the lower part of the minienvironment and reaches the door opener of the LPU. Particles produced on the moving parts of the LPU were carried to the back surface of the wafer, which were at the lowest position (the first wafer). How the open ratio of the perforated plate of the minienvironment affects the pressure difference between the minienvironment and surrounding environment and the airflow through the minienvironment was determined. The thoroughly elucidated information is useful for mitigating contamination when planning a fabrication line and designing a production tool. Index Terms--Contamination control, front opening unified pod (FOUP), load port unit (LPU), minienvironment.

As integrated circuit feature size continues to shrink, yield loss due to parametric variation will become more and more significant. Real-time feedback control provides a means of reducing parametric variation and therefore limiting this type of yield loss. A challenge in applying feedback control to semiconductor manufacturing processes is selecting the variables to feed back. In many manufacturing processes, the important product variables cannot be measured in real-time and therefore cannot be directly controlled using real-time feedback control. An alternative, which has proven effective, is to feed back process variables closely related to the product variables. Typically, selection of process variables to feed back is based upon qualitative knowledge about the process, which in many cases is limited. In this paper, an empirical methodology for selecting the best process variables for feedback in order to minimize variation in the product variables is presented. Two versions of this methodology are described, a full version and a 'lite' version. The latter is an abridged version of the former. Prior to introducing this methodology, a condition under which real-time feedback control will reduce product variable variation is derived. This condition is used to highlight the sources of variance in the product variables, information which is used to explain how the methodology works. The methodology is evaluated using simulated experiments. Both the full and lite versions prove to be effective under the assumptions stated for this study although the full version is clearly superior in terms of performance. Application of the methodology to a reactive ion etch process is described in a companion work. Index Terms--Feedback control, feedback variable selection, semiconductor process model, simulation, variance reduction.

The PVVM methodology for feedback variable selection introduced in a companion paper (Patterson et al., 2003) is applied to a gate etch process. The primary purpose of this paper is to illustrate the practical aspects of utilizing this methodology. Particular attention is given to the challenging task of process modeling. The model-building procedure and constraint-limited exhaustive search is demonstrated to perform superior to other model-building procedures including principal component regression and partial least squares regression for use in this methodology. A second purpose is to present the results for the etch process. Advanced sensors considered for real-time process control of this process include an RF probe, mass spectroscopy and optical emission spectroscopy. Feedback variables are selected to reduce variation in etch rate, nonuniformity and lateral etch rate. The advantages of treating location on the wafer as a disturbance to the etch rate model so that both etch rate and nonuniformity may be captured in one model are presented and experimentally verified. Index Terms--Feedback control, feedback variable selection, parametric variarion, reactive ion etch, regression analysis, subset selection, variance reduction.

A study on the developmental trends in hybrid wafer scale integration technology reveals that future multichip module (MCM) circuits design trends will be on high performance digital MCMs as well as analog mixed signal and microwave MCMs. MCMs will be available in three-dimensional stacked configurations. Present day MCM manufacturing processes are the chip on board and MCM-laminate method, MCM-substrate method and the MCM-ceramic method.

The instantaneous switch-off of the gas precursors during the ramp-down cycle in a spike ramp process is demonstrated to be an effective method to enhance the reliability of rapid thermal oxide. Due to the slow ramp-down rate (60[degrees]C-90[degrees]C/s) of a rapid thermal process, the oxidation during the slow ramp-down cycle may produce the inferior oxide, especially for ultrathin oxide. To avoid the oxidation in the slow ramp-down cycle, the oxidation precursor (oxygen) is switched off during the ramp-down cycle. The reliability of resulting oxide without oxidation during the ramp-down cycle is enhanced as compared with the conventional oxide, which is still oxidized during the ramp-down cycle. Index Terms--Gas switching, rapid thermal oxidation, reliability, spike ramp.

Byline: Jian (Jessie) Wu, Xuekun Sun, Z.J. Pei, X. Jack Xin, Kelli Simmelink Silicon wafers are the primary semiconductor substrates used to fabricate Integrated Circuits (ICs). Recently, the industry is making a transition from 200 to 300 mm wafers. To attain very flat 300 mm silicon wafers, grinding has been used to flatten the wire-sawn wafers. However, it is challenging for grinding to remove the waviness induced in wire sawing. To enhance the waviness removal ability of grinding process, several approaches have been explored including soft-pad grinding. This paper presents a study on soft-pad grinding of 300 mm wire-sawn silicon wafers through Finite Element Analysis (FEA) with designed experiments. A 25 (five factors, two levels) full factorial design is employed to reveal the main effects as well as the interaction effects of five factors (elastic modulus, Poisson's ratio and thickness of the soft pad; waviness wavelength and waviness height of silicon wafers) on the effectiveness of waviness removal. FEA simulation results are compared with relevant experimental results. Implications of this study to manufacturing are also discussed.