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The demands of future applications in computing (from self-driving cars to bioinformatics) overwhelm the projected capabilities of current electronic systems. The need to process unprecedented amounts of loosely structured data is driving the push for ultradense and fine-grained integration of traditionally off-chip components (e.g., sensors, memories) with energy-efficient computation units—all within a single chip. Monolithic 3-D integration is a leading approach for building such future systems, as it naturally enables ultradense connectivity between various heterogeneous technologies inside a single chip. This article discusses exciting recent progress toward realizing monolithic 3-D systems and elucidates key benefits that these new systems offer. Monolithic 3-D integration promises to enable the next wave of gains in performance (both energy and speed) for coming generations of applications as well as provides the means for developing rich additional functionalities such as sensing-immersed-in-computation that lie beyond the scope of traditional computing today. [ABSTRACT FROM AUTHOR]

The article discusses the potential of the spin-transfertorque magnetic random access memory (STT-MRAM) devices using different physical mechanisms. Details about the STT-MRAM are provided which store information in the magnetization of a nanoscale magnet. Also tackled are the difference in which the design specifications for memory.

Abstract: We report an effect in vertically-aligned carbon nanotube growth in which small catalyst features in proximity to large features show an enhanced growth rate. We apply this so-called “synergetic growth” effect in micrometer-scale patterns to produce vertical-like growth horizontally. This approach enables carbon nanotube integration into device applications requiring a fair degree of carbon nanotube alignment. The synergetic growth effect corroborates growth mechanisms describing carbon nanotube growth as a more complex process than elemental carbon supersaturating metal catalyst. [Copyright &y& Elsevier]

Semiconducting carbon nanotubes are robust molecules with nanometer-scale diameters that can be used in field-effect transistors, from larger thin-film implementation to devices that work in conjunction with silicon electronics, and can potentially be used as a platform for high-performance digital electronics as well as radio-frequency and sensing applications. Recent progress in the materials, devices, and technologies related to carbon nanotube transistors is briefly reviewed. Emphasis is placed on the most broadly impactful advancements that have evolved from single-nanotube devices to implementations with aligned nanotubes and even nanotube thin films. There are obstacles that remain to be addressed, including material synthesis and processing control, device structure design and transport considerations, and further integration demonstrations with improved reproducibility and reliability; however, the integration of more than 10,000 devices in single functional chips has already been realized. [ABSTRACT FROM AUTHOR]

This paper introduces a novel structure for filamentary-conduction-type resistance change memory. The new structure utilizes the fringing field from the top metal electrode to effectively confine the position of the filaments in the cell. Nanoscale (100–50 nm) memory cells are fabricated using nickel oxide (NiO) thin film as the resistance-switching layer to demonstrate the feasibility and functionality of the new structure. The fabricated nanoscale memory cells achieved low reset current (100–200 \mu\A), narrower distribution in low-resistance states, and higher on/off ratio than those of the standard structure. In addition, good scalability down to 50 nm was demonstrated. [ABSTRACT FROM AUTHOR]

A physics-based compact device model is developed for the conducting-bridge random-access memory (CBRAM). By considering the dependence of ion migration velocity on the electric field, the vertical and lateral growth/dissolution dynamics for the metallic filament are investigated. Both time-dependent transient and “quasi-static” switching characteristics of the CBRAM are captured. Moreover, the I–V characteristics of the CBRAM can be reproduced. By further considering the compliance effect on the size of the metallic filament, the on-state resistance modulation is fitted, and the multilevel capability is included in the model. This model is verified by the experiments data from the \Ag/Ge0.3\Se0.7-based CBRAM cells. This model reveals that experimentally measured switching parameters such as the threshold voltage and the cell resistance are dynamic quantities that depend on the programming duration time. The time-dependent switching process of the CBRAM is quantified, thus paving the way for a compact SPICE model for circuit simulation. [ABSTRACT FROM PUBLISHER]

A physics-based compact model is developed for III–V field-effect transistors for digital logic applications. Quasi-ballistic ratios, trapezoidal quantum-well subband energy levels, and 2-D source/drain influence on both electrostatics and capacitance are considered. Furthermore, gate tunneling leakage current and parasitic capacitance models are included. These latter effects are important in future technology logic applications, particularly in circuits such as high-density cache arrays. In this paper, we describe the III–V compact model including the gate leakage current and parasitic capacitance analytical models. The efficacy of the compact model in a practical circuit environment is demonstrated using transient simulations of a 6T-static random access memory cell. In addition, we provide design guidelines for optimization of the intrinsic and the extrinsic structure with regard to the parasitic effects. [ABSTRACT FROM AUTHOR]

Cross-point memory architecture offers high device density, yet it suffers from substantial sneak path leakages, which result in large power dissipation and a small sensing margin. The parasitic resistance associated with the interconnects further degrades the output signal and imposes an additional limitation on the maximum allowable array size. In this paper, we study the device requirements of a resistive cross-point memory array under the worst-case write and read operations. We focus on the data pattern dependence of the memory array and compare the effect of the memory cell resistance values and resistance ratio for determining the maximum array size. The number of cells in the array can reach \10^6 with a signal swing > 50% of the reading voltage when Ron is beyond 3 \M\Omega and Roff/Ron is greater than 2. A large memory cell resistance value can further reduce the power consumption, obviate the need for a large Roff/Ron ratio, and avoid the inclusion of cell selection devices. The effect of the nonlinearity of the I–V characteristics of the memory cells is also investigated. The nonlinearity calls for a substantial tradeoff between the memory cell resistance values and the resistance ratio, and must be taken into consideration for the device design. [ABSTRACT FROM PUBLISHER]

A physics-based analytical compact model of InGaAs field-effect transistors (FETs) for digital logic applications is developed. This model neither heavily depends on parameter extraction nor requires any time-consuming computation while capturing the essential physics, enabling digital circuit design and circuit-level performance estimation for III-V FETs. The model captures short channel effects, trapezoidal-shape quantum-well energies, bias-dependent ballistic ratios, and capacitances including 2-D potential profile information. Each is verified via numerical calculations and 2-D electrostatic simulation, followed by a comparison o the model I-V characteristics with experiment data. Finally, the transient response of FO4 inverters demonstrates the use of the compact model for future technology circuit simulations. [ABSTRACT FROM AUTHOR]

In this brief, the impact of parasitic resistance and capacitance on InGaAs HEMT digital logic circuits is investigated via device simulations and circuit analysis. We present the correlation between device geometry and circuit delay for various structural scenarios. When the gate-to-S/D contact distance Lsg is scaled down to logic device standards, high integration density and additional circuit performance can be expected as compared with experimental devices that are demonstrated to date. This brief highlights the importance of engineering the device structure outside the channel region to achieve high device performance and device density. Scaled InGaAs HEMTs show superior performance over experimental devices and 27% less power consumption for the same circuit-speed constraint. [ABSTRACT FROM AUTHOR]

This paper presents a complete circuit-compatible compact model for single-walled carbon-nanotube field-effect transistors (CNFETs) as an extension to Part 1 of this two-part paper. For the first time, a universal circuit-compatible CNFET model including the practical device nonidealities is implemented with HSPICE. In addition to the nonidealities included in the companion paper, this paper includes the elastic scattering in the channel region, the resistive source/drain (S/D), the Schottky-barrier resistance, and the parasitic gate capacitances. More than one nanotube per device can be modeled. Compared to silicon technology, the CNFETs show much better device performance based on the intrinsic CV/I gate-delay metric (six times for nFET and 14 times for pFET) than the MOSFET device at the 32-nm node, even with device nonidealities. This large speed improvement is significantly degraded (by a factor of five to eight) by interconnect capacitance in a real circuit environment. We performed circuit-performance comparison with all the standard digital library cells between CMOS random logic and CNFET random logic with HSPICE simulation. Compared to CMOS circuits, the CNFET circuits with one to ten carbon nanotubes per device is about two to ten times faster, the energy consumption per cycle is about seven to two times lower, and the energy-delay product is about 15-20 times lower, considering the realistic layout pattern and the interconnect wiring capacitance. [ABSTRACT FROM AUTHOR]

This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large- (digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET- device model incorporating the additional device/circuit-level nonidealities and multiple CNTs reported in the paper of Deng and Wong. [ABSTRACT FROM AUTHOR]

This paper presents accurate analytical models to calculate the electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. Gate capacitance Cgg is decomposed into three major components: 1) capacitance Cgc between the gate and the parallel cylindrical conducting channels (the number of channels ≥ 1) in dual-layer dielectric materials; 2) outer fringe capacitance Cof between the gate and the source/drain cylinder conductors; and 3) coupling capacitance Cgtg between the adjacent gates. A realistic planar-gate structure with high-k gate dielectric material is considered in this paper, including the screening effect of the parallel conductors and different dielectric materials on capacitance. An accuracy of 10% is achieved from the analytic models, compared with the values that were simulated by 3-D numerical field solvers. Using a simple analytical expression for the gate delay that includes the parasitic capacitance and screening of multiple parallel conducting channels, this paper also shows that both increasing the number of channels per gate and reducing the gate height are effective ways to improve device speed. [ABSTRACT FROM AUTHOR]

Devices exhibiting negative differential resistance (NDR), such as resonant tunneling diodes and Esaki-type diodes, offer the promise of converting a dynamic random access memory (DRAM) cell to operate like a static random access memory cell with potentially lower dynamic power dissipation and faster READ and WRITE operations than a conventional DRAM. However, a circuit model that describes the operation of the resulting novel memory cell and is of use for both hand analysis and design, and circuit simulation as has yet been developed due to the non-analytical current-voltage curve of the two NDR devices in the cell. In this paper, we present a "composite" circuit model that describes the relationship between current and voltage at the common node of connection of the two NDR devices. The composite model is analytical and can easily be implemented in SPICE or any circuit simulator. It is also useful for hand analysis of the READ/WRITE performance metrics. Finally, comparisons of composite models are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a simple and accurate expression for inverter effective drive current for nanoscale Si and carbon nanotube FET (CNFET) performance benchmarking. The choice of Ieff = (INL + INM + INH - IP)/3, where INL = IDS(N-FET) (VGS = 0.5VDD, VDS = VDD), INM = IDS(N-FET) (VGS = 0.75VDD, VDS = 0.75VDD), INH = IDS(N-FET) (VGS = VDD, VDS = 0.5VDD), and IP = ISD(P-FET) (VSG = 0.25VDD, VSD = 0.25VDD), includes the effects of both the nFET and the pFET of an inverter and accurately captures the inverter delay performance over many CMOS technology nodes and in the presence of device nonidealities. The proposed metric indicates that the performance enhancement of CNFETs over Si MOSFETs is not as large as that predicted by IDSsat in a circuit environment because of the nonideal I-V characteristics. [ABSTRACT FROM AUTHOR]

As device sizes approach the nanoscale, new opportunities arise from harnessing the physical and chemical properties at the nanoscale. It is now feasible to contemplate new nanoelectronic systems based on new devices with completely new system architectures. This paper will give an overview of the materials, technology, and device opportunities in the nanoscale era. So far, much of the nanoscale sciences have been researched in the physics, chemistry, and materials science communities. While there have been plenty of good science in the nano world, nanotechnology is still at its infancy. The engineering community is poised to make a major impact in transforming good nanoscience into useful nanotechnology. The disciplined performance benchmarking against alternatives as practiced by the engineering community will prove to be invaluable to the development of new nanotechnologies. Examples of such performance benchmarking exercises will be shown and directions for future work will be suggested. [ABSTRACT FROM AUTHOR]

Self-assembling diblock copolymer, polystyrene-b-poly-4-vinylpyridine (PS-b-P4VP), was used as the template for fabricating phase change nanostructures. The high density GeSb nanodots were formed by etching into an amorphous GeSb thin film using silica hard mask which was patterned on top of polymer. The nanodot arrays are 15 nm in diameter with 30 nm spacing. This is smaller than most structures obtained by e-beam lithography. Time-resolved x-ray diffraction studies showed that the phase transition occurred at 235 °C, which is 5 °C lower than blanket GeSb film but higher than that of Ge2Sb2Te5 (150 °C). GeSb showed good temperature stability for fabrication of small memory devices. [ABSTRACT FROM AUTHOR]

In this work, we introduce a novel nonalloyed contact structure for n-GaAs and n-In0.53Ga0.47As by using single metals in combination with a thin dielectric to tune the effective metal/III-V work function toward the conduction band edge. We reduced the effective Schottky barrier height ([uppercase_phi_synonym]B,eff) of Al/GaAs from 0.75 to 0.17 eV through the use of a thin atomic layer deposition Al2O3. Barrier height reduction was verified for a variety of metals (Y, Er, Al, Ti, and W) through direct measurements and deduced from increased diode current and reduced contact resistance. Similar results were observed on n-In0.53Ga0.47As. Two possible underlying mechanisms are discussed: one based on the formation of a dielectric dipole and the other based on the blocking of metal induced gap states. This structure has applications as a nonalloyed low resistance ohmic contact for III-V metal-oxide-semiconductor field-effect transistors (MOSFETs) or high electron mobility transistors (HEMTs), and as a near zero barrier height contact for III-V Schottky barrier field-effect transistors or diodes. [ABSTRACT FROM AUTHOR]

A full-band analytical model of the equilibrium carrier density for single-wall semiconducting carbon nanotubes (sCNTs) is presented. The carrier density, which is a fundamental property of all semiconductors, is obtained using a semiempirical method for degenerate positions of the Fermi level and shows good agreement with numerical tight-binding results. The quantum capacitance is subsequently derived from the carrier density and used to develop a C-V model with good agreement with experimental quantum capacitance measurements. An analytical model of the gate coupling function of sCNTs is also reported which relates the internal surface potential with the external applied gate voltage. The diameter temperature and Fermi level dependency, and the essential properties of carbon nanotubes device physics are captured in these analytical equations. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) have great potential for future high-performance and energy-efficient transistor technology. To realize this potential, methods to dope the CNTs need to be developed to achieve low parasitic resistance of the transistor. Two key issues present themselves: (a) understanding the doping mechanism of the various methods and (b) stability of the doping method. For instance, although studies on molybdenum oxide (MoOx) demonstrate its ability to heavily dope nanomaterials, the interaction between MoOx and the CNT is unclear. Here, we observe an unstable effect of MoOx on the CNT and demonstrate dielectric passivation as a means to preserve the doping strength. The semiconducting CNTs exhibit greater than 103× reduction in resistance after stably doped with MoOx. By exploiting the instability of MoOx, we delve deeper into clarifying the doping mechanism. The relationship between the time-dependent material property of MoOx and the change in the electrical measurements of CNT devices is investigated to study the role of work function in doping the CNTs. We conclude that the doping mechanism of MoOx on the CNT is due to bandgap modulation by charge transfer, which occurs due to the difference in work function between MoOx and the CNT. [ABSTRACT FROM AUTHOR]

Continuous monitoring of physiological parameters inside a living cell will lead to major advances in our understanding of biology and complex diseases, such as cancer. It also enables the development of new medical diagnostics and therapeutics. Progress in nanofabrication and wireless communication has opened up the potential of making a wireless chip small enough that it can be wholly inserted into a living cell. To investigate how such chips could be internalized into various types of living single cells and how this process might affect cells’ physiology, we designed and fabricated a series of multilayered micron-scale tag structures with different sizes as potential RFID (adio requency entification) cell trackers. While the present structures are test structures that do not resonate, the tags that do resonate have similar structure from device fabrication, material properties, and device size point of view. The structures are in four different sizes, the largest with the lateral dimension of 9 μm × 21 μm. The thickness for these structures is kept constant at 1.5 μm. We demonstrate successful delivery of our fabricated chips into various types of living cells, such as melanoma skin cancer, breast cancer, colon cancer and healthy/normal fibroblast skin cells. To our surprise, we observed a remarkable internalization rate difference between each cell type; the uptake rate was faster for more aggressive cancer cells than the normal/healthy cells. Cell viability before and after tag cellular internalization and persistence of the internalized tags have also been recorded over the course of five days of incubation. These results establish the foundations of the possibility of long term, wireless, intracellular physiological signal monitoring. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) has undergone significant academic and industrial research in the last 15 years. After much development, it is now poised to enter the market as a storage-class memory (SCM), with performance and cost between that of NAND flash and DRAM. In this paper, we review the history of phase-transforming chalcogenides leading up to our current understanding of PCM as either a storage-type SCM, with high-density and better than NAND flash endurance, write speeds, and retention, or a memory-type SCM, with fast read/write times to function as a nonvolatile DRAM. Several of the key findings from the community relating to device dimensional scaling, cell design, thermal engineering, material exploration, and storing multiple levels per cell will be discussed. These areas have dramatically impacted the course of development and understanding of PCM. We will highlight the performance gains attained and the future prospects, which will help drive PCM to be as ubiquitous as NAND flash in the upcoming decade. [ABSTRACT FROM AUTHOR]

Introduces series of articles which deals on digital imaging. Information on the processes of color filter array interpolation; Image display.

Phase Change Memory (PCM) is a leading candidate for next generation data storage, but it typically suffers from high switching (RESET) current density (20–30 MA/cm2). Interfacial Phase Change Memory (IPCM) is a type of PCM using multilayers of Sb2Te3/GeTe, with up to 100× lower reported RESET current compared to the standard Ge2Sb2Te5-based PCM. Several hypotheses involving fundamentally new switching mechanisms have been proposed to explain the low switching current densities, but consensus is lacking. Here, we investigate IPCM switching by analyzing its thermal, electrical, and fabrication dependencies. First, we measure the effective thermal conductivity (∼0.4 W m−1 K−1) and thermal boundary resistance (∼3.4 m2 K GW−1) of Sb2Te3/GeTe multilayers. Simulations show that IPCM thermal properties account only for an ∼13% reduction of current vs standard PCM and cannot explain previously reported results. Interestingly, electrical measurements reveal that our IPCM RESET indeed occurs by a melt-quench process, similar to PCM. Finally, we find that high deposition temperature causes defects including surface roughness and voids within the multilayer films. Thus, the substantial RESET current reduction of IPCM appears to be caused by voids within the multilayers, which migrate to the bottom electrode interface by thermophoresis, reducing the effective contact area. These results shed light on the IPCM switching mechanism, suggesting that an improved control of layer deposition is necessary to obtain reliable switching. [ABSTRACT FROM AUTHOR]

Low-dimensional (low-D) semiconductors such as carbon nanotubes (CNTs) and 2-D materials are promising channel materials for nanoscale field-effect transistors (FETs) due to their superior electrostatic control. However, classical scale length theory (SLT) does not incorporate the effect of channel extensions, which becomes crucial for thin channels (< 10 nm) and short gate lengths. Here, we extend the classical SLT by introducing two boundary coupling parameters, which describe the impact of gate and drain biases on the source- and drain-channel junction potentials. Moreover, we introduce a general expression for the scale length specifically for low-D FETs. This extended SLT accurately describes electrostatic short-channel effects (SCEs) of low-D FETs, with < 5% error in subthreshold slope over a wide range of parameters versus > $2\times $ error using the classical SLT. The extended SLT is based on three parameters (scale length, gate, and drain boundary coupling parameters) which can be extracted from potential profiles or FET transfer characteristics. In addition, the extended SLT uses analytical closed-form expressions that can be easily included in a compact model to facilitate design-technology co-optimization (DTCO) with low-D FETs to leverage the crucial role of their extensions. [ABSTRACT FROM AUTHOR]

In this paper, the recent progress of synaptic electronics is reviewed. The basics of biological synaptic plasticity and learning are described. The material properties and electrical switching characteristics of a variety of synaptic devices are discussed, with a focus on the use of synaptic devices for neuromorphic or brain-inspired computing. Performance metrics desirable for large-scale implementations of synaptic devices are illustrated. A review of recent work on targeted computing applications with synaptic devices is presented. [ABSTRACT FROM AUTHOR]

Learning from a few examples (one/few-shot learning) on the fly is a key challenge for on-device machine intelligence. We present the first chip-level demonstration of one-shot learning with Stanford Associative memory for Programmable, Integrated Edge iNtelligence via life-long learning and Search (SAPIENS), a resistive random access memory (RRAM)-based non-volatile associative memory (AM) chip that serves as the backend for memory-augmented neural networks (MANNs). The 64-kb fully integrated RRAM-CMOS AM chip performs long-term feature embedding and retrieval, demonstrated on a 32-way one-shot learning task on the Omniglot dataset. Using only one example per class for 32 unseen classes during on-chip learning, SAPIENS achieves 79% measured inference accuracy on Omniglot, comparable to edge software model accuracy using five-level quantization (82%). It achieves an energy efficiency of 118 GOPS/W at 200 MHz for in-memory L1 distance computation and prediction. Multi-bank measurements on the same chip show that increasing the capacity from three banks (24 kb) to eight banks (64 kb) improves the chip accuracy from 73.5% to 79%, while minimizing the accuracy excursion due to bank-to-bank variability. [ABSTRACT FROM AUTHOR]

Phase-change memory (PCM) is a promising candidate for data storage in flexible electronics, but its high switching current and power are often drawbacks. In this study, we demonstrate a switching current density of ~0.1 mega-ampere per square centimeter in flexible superlattice PCM, a value that is one to two orders of magnitude lower than in conventional PCM on flexible or silicon substrates. This reduced switching current density is enabled by heat confinement in the superlattice material, assisted by current confinement in a pore-type device and the thermally insulating flexible substrate. Our devices also show multilevel operation with low resistance drift. The low switching current and good resistance on/off ratio are retained before, during, and after repeated bending and cycling. These results pave the way to low-power memory for flexible electronics and also provide key insights for PCM optimization on conventional silicon substrates. [ABSTRACT FROM AUTHOR]

HfO2-based resistive RAM (RRAM) is an emerging nonvolatile memory technology that has recently been shown capable of storing multiple bits-per-cell. The energy/delay costs of an RRAM write operation are dependent on the number of pulses required for RRAM programming. The pulse count is often large when existing programming approaches are used for multiple bits-per-cell RRAM, especially when resistance ranges are allocated to account for retention. We present a new technique, Range-Dependent Adaptive Resistance (RADAR) Tuning, for fast and energy-efficient programming of multiple bits-per-cell RRAM arrays, using a combination of coarse- and fine-grained RRAM resistance tuning. Experimental data are collected on 16k cells from two 1Megacell (1M physical cells) 1T1R HfO2-based RRAM arrays fabricated in a 130-nm CMOS process. RADAR reduces the programming pulse count by 2.4X (for both uncycled cells and cells that have undergone 8k cycles) on average over existing programming techniques tested on the same RRAM arrays, with the same bit error rate targets. [ABSTRACT FROM AUTHOR]

Using the model developed in Part I of this two-part paper, the simulated dc sweep and pulse transient characteristics of a metal oxide resistive random access memory cell are corroborated with the experimental data of \HfOx memory. Key switching features such as the abrupt SET process, gradual RESET process, current fluctuation in the RESET process, and multilevel resistance state distributions are captured by the simulation. The current fluctuation in the RESET process is caused by the competition between the simultaneous oxygen vacancy recombination and generation processes. The origin of the high-resistance state variation and the tail bit problem are attributed to the variation of the tunneling gap distances and the stochastic nature of new Vo generation in the tunneling gap region, respectively. The use of the write–verify technique and a bilayer oxide structure are proposed to achieve a tighter resistance distribution. [ABSTRACT FROM AUTHOR]

The variation of switching parameters is one of the major challenges to both the scaling and volume production of metal-oxide-based resistive random-access memories (RRAMs). In this two-part paper, the source of such parameter variation is analyzed by a physics-based simulator, which is equipped with the capability to simulate a large number (\sim1000) of cyclic SET–RESET operations. By comparing the simulation results with experimental data, it is found that the random current fluctuation experimentally observed in the RESET processes is caused by the competition between trap generation and recombination, whereas the variation of the high resistance states and the tail bits are directly correlated to the randomness of the trap dynamics. A combined strategy with a bilayer dielectric material and a write-verification technique is proposed to minimize the resistance variation. We describe the simulation methodology and discuss the dc results in Part I. The corroboration of the model and the device optimization strategy will be discussed in Part II. [ABSTRACT FROM AUTHOR]

The subthreshold conduction in the amorphous state of the phase-change material is dominated by the hopping of the carriers through the trap states or localized states with the assistance of the electric field across the material. It is important to understand the nature and number of these traps to properly model the physics of the conduction, threshold switching, and drift in phase-change materials. In this paper, we present a device structure and a methodology to extract the trap spacing directly from the I–V characteristics of the device. Furthermore, the dependence of the trap spacing on the amorphous region thickness, reset voltage, and drift is also discussed. These results are then correlated with the \1/f noise measurements of the device. [ABSTRACT FROM AUTHOR]

Historically, the off-state current Ioff and the supply voltage Vdd are specified as technology targets for Si metal–oxide–semiconductor field-effect transistors (MOSFETs) at each technology node. Emerging device technologies such as III–V transistors, carbon-nanotube FETs (CNFETs), and tunneling FETs (TFETs) are often targeted to outperform Si MOSFETs at the same Ioff and Vdd values. However, the conclusions from the conventional methodology are limited for advanced technology and diversified applications, when Dennard scaling is inefficient and different device structures are invented. We present a new device-technology assessment methodology based on energy–delay optimization, which takes into consideration key circuit-level information, such as logic depth, activity factors, and fanout (FO). Our methodology starts from device I– V and C –V characteristics and treat Ioff and Vdd as “free variables.” Together with device and supply-voltage variations, we obtain a corresponding and different optimal set of Ioff and Vdd and optimal energy–delay for each emerging device. We show that today's best available III–V transistors and CNFETs can outperform the best Si FETs by 1.5–2 and 2–3.5 times in terms of energy efficiency, respectively. Projected into the 10-nm-gate-length regime, III–V-on-insulator, CNFETs, and TFETs are 1.25, 2–3, and 5–10 times better than the International Technology Roadmap for Semiconductors target, for FO1 delays of 0.3, 0.1, and 1 ns, respectively. [ABSTRACT FROM PUBLISHER]

The theoretical performance of carbon nanotube field-effect transistors (CNFETs) with Schottky barriers (SBs) is examined by means of a general ballistic model. A novel approach is used to treat the SBs at the metal-nanotube contacts as mesoscopic scatterers by modifying the distribution functions for carriers in the channel. Noticeable current reduction is observed compared to previous ballistic models without SBs. Evanescent- mode analysis is used to derive a scale length and the potential profile near the contacts for radially symmetric CNFET structures. Band-to-band tunneling current and ambipolar conduction are also treated. The effects of different device geometries and different nanotube chiralities on the drain-current are studied using this simple model. Quantum conductance degradation due to SBs is also observed. [ABSTRACT FROM AUTHOR]

The rapid growth and development of technology has had significant implications for healthcare, personalized medicine, and our understanding of biology. In this work, we leverage the miniaturization of electronics to realize the first demonstration of wireless detection and communication of an electronic device inside a cell. This is a significant forward step towards a vision of non-invasive, intracellular wireless platforms for single-cell analyses. We demonstrate that a 25 μ m wireless radio frequency identification (RFID) device can not only be taken up by a mammalian cell but can also be detected and specifically identified externally while located intracellularly. The S-parameters and power delivery efficiency of the electronic communication system is quantified before and after immersion in a biological environment; the results show distinct electrical responses for different RFID tags, allowing for classification of cells by examining the electrical output noninvasively. This versatile platform can be adapted for realization of a broad modality of sensors and actuators. This work precedes and facilitates the development of long-term intracellular real-time measurement systems for personalized medicine and furthering our understanding of intrinsic biological behaviors. It helps provide an advanced technique to better assess the long-term evolution of cellular physiology as a result of drug and disease stimuli in a way that is not feasible using current methods. [ABSTRACT FROM AUTHOR]

Addresses the problem of hot-carrier degradation and lifetime monitoring in silicon-on-insulator (SOI) metal oxide semiconductor field-effect transistors (MOSFET). Devices fabrication and experimental setup; Emission characteristics; Correlation between emission and degradation; Conclusions.

Increasing computation demand of machine learning (ML) applications (recommender system, image classification, speech recognition, and so on) calls for the development of specialized hardware for ML and neuromorphic computing. New memories, such as resistive random access memory (RRAM), can be used to store weights of neural networks and to accelerate matrix multiplication, the dominant operation in neural networks. One of the key challenges for RRAM-based neural networks is to achieve bidirectional analog conductance modulation for online training. This article provides a programming scheme (SRA: small RESET voltage amplitude and appropriate SET voltage) to achieve bidirectional analog conductance modulation of RRAM devices. We find that both abrupt and gradual SET can be obtained for the same device. The controlling parameters for modulating the gradual SET behavior are the SET voltage and the local device temperature. We suggest that the filament morphology before SET may be the key to understanding this phenomenon; gradual SET is obtained when the filaments have a single-layer gap in the RESET state, and abrupt SET is obtained when the filaments have a multilayer gap in the RESET state. [ABSTRACT FROM AUTHOR]

To increase the density of magnetoresistive random access memory (MRAM) beyond the 1T1MTJ MRAM cell in use today, the design space for 1S1MTJ MRAM array is analyzed by cooptimizing both selectors and MTJs. Current low-resistance MTJs for 1T1MTJ MRAM are not suitable for 1S1MTJ MRAM. Threshold-type selectors would induce a strong read disturb on the MTJ due to the snapback voltage (VTH – VHOLD) when the selector is turned on. Also, exponential-type selectors would degrade the read margin (RM) due to its large ON-state resistance. When using existing selectors to achieve a 1-M-bit 1S1MTJ array, it is necessary to adjust the product of resistance and area (RA) and the diameter of the MTJ. An MTJ with the RA = 15 Ω ⋅ μm2 and the diameter = 50 nm can meet the criterion of RM > 10% for both exponential-type selectors (exponential slope = 300–500 mV/decade with the current density ~ 1 MA/cm2) and threshold-type selectors (VTH – VHOLD ~250 mV). A design space accommodating a selector variation of around 1% can be found for MTJs with tunnel magnetoresistance ratio (TMR) < 250%. With an increased TMR of 250%–350% of the MTJ, the tolerance of variations for exponential-type selectors and threshold-type selectors can be improved to 2% and 4%, respectively. This provides a chance for the 1S1MTJ MRAM with existing selectors. [ABSTRACT FROM AUTHOR]

The conduction mechanism of metal oxide resistive switching memory is debated in the literature. We measured the I-V characteristics below the switching voltages through TiN/HfOx/Pt memory stack and found the conduction cannot be described by the commonly used Poole-Frenkel model, because the fitted dielectric constant and the trap energy are unreasonable as compared to their known values. Therefore, we provide an alternate viewpoint based on a trap-assisted-tunneling model. Agreement of the bias polarity/temperature/resistance state-dependent conduction behavior was achieved between this model and experimental data. And insights for the multilevel capability due to the control of tunneling distance were obtained. [ABSTRACT FROM AUTHOR]

HfOx/AlOx bilayer resistive switching devices were fabricated for the study of the switching dynamics of the metal oxide memory. An exponential voltage-time relationship was experimentally observed as follows: the programming pulse widths need for switching exponentially decreased with the increase in the programming pulse amplitudes. Two following programming schemes were proposed to modulate the high resistance state values: (1) exponentially increase the programming pulse width; (2) linearly increase the programming pulse amplitude. Although both of these schemes were effective to achieve the target resistance, the transient current response measurements suggest the second scheme consumes considerably less energy in the programming. A field-driven oxygen ions migration model was utilized to elucidate the above experimentally observed phenomenon. [ABSTRACT FROM AUTHOR]

We demonstrate the integration of a nonalloyed contact structure developed for III-V semiconductors to the source/drain of an In0.53Ga0.47As metal-oxide-semiconductor field effect transistor (MOSFET) with atomic layer deposition (ALD) Al2O3 high-κ dielectric. This nonalloyed contact utilizes single metals in combination with dielectric dipoles to tune the metal/semiconductor Femi level pinning toward the semiconductor's band edge for minimal contact resistance and barrier height. The metal/III-V semiconductor effective barrier heights have been reduced by as much as 0.40 eV using SiN and 0.55 eV using Al2O3 dielectrics. With this InGaAs nMOSFET as a starting point, this contact can be applied to other III-V n-type MOSFETs, p-type MOSFETs, and Schottky Barrier field effect transistors. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RSM) shows potentials for high-capacity storage because of its simple cell structure, small footprint, and good scalability. This two-part article discusses how to implement ultrahigh-density (~terabits) storage with RSM covering design considerations from device to memory array architecture. In Part I of this two-part article, an accurate and computationally efficient model is developed to study 3-D vertical RSM (VRSM). In this article, we use 3-D VRSM with a hexagon-patterned pillar layout (3-D hexagon VRSM) as an example to elaborate our approach. Using the parasitic resistance extracted from physics-based 2-D field solver as the reference, we develop a lumped resistor network for SPICE simulation to accurately capture all leakage currents of the array. This full resistor network is further simplified to a reduced network to achieve high computational efficiency and maintain the full network accuracy (with a relative error <2%). Without this simplification, practical memory array sizes cannot be simulated efficiently. The interplay between the memory cell resistance values and selector nonlinearity (NL) on the maximum array size and the write/read margins under the worst case scenarios is discussed. Large memory cell resistance (low-resistance states ≥100 k) with enough NL (~103) from the selector is recommended for successful write/read operations in a single 3-D hexagonal VRSM array of megabit scale. [ABSTRACT FROM AUTHOR]

Using the reduced resistor network developed in Part I of this two-part article, we present practical design guidelines from device to architecture levels to achieve ultrahigh-density 3-D vertical resistive switching memory (VRSM). We first design both hexagon and comb arrays using 7-nm FinFET as pillar driving transistors (pillar drivers). Small-footprint pillar drivers are necessary for a high pillar areal density competitive to 3-D NAND. We then organize the arrays into an architecture using the compact staircase and highly conductive wordplane connection (WPC) to maximize array efficiency and chip density. We investigate the memory and selector requirements, tolerance of parasitic resistances, latency, and energy consumption for both hexagon and comb architectures. The results indicate that the hexagon array with large low-resistance state (LRS) and nonlinearity (NL) is required for ultradense 3-D VRSM. Compared to the comb array, the hexagon array benefits from a continuous WP pattern and yields a better tolerance of parasitic resistances and a smaller latency. The energy consumptions of both architectures are similar. Compared to the most advanced 3-D NAND, 3-D VRSM has higher chip density and shows better potential for future ultradense storage. [ABSTRACT FROM AUTHOR]

For high-volume manufacturing of 2-D transistors, area-selective chemical reaction deposition (CVD) growth is able to provide good-quality 2-D layers and may be more effective than exfoliation from bulk crystals or wet/dry transfer of large-area as-grown 2-D layers. We have successfully grown continuous and uniform WS2 film comprising around seven layers by area-selective CVD approach using patterned tungsten source/drain metals as the seeds. The growth mechanism is inferred and supported by the transmission electron microscope (TEM) images, as well. The first top-gate MOSFETs of CVD-WS2 channels on SiOx/Si substrates are demonstrated to have good short channel electrical characteristics: ON-/OFF-ratio of 106, a subthreshold swing of 97 mV/decade, and nearly zero drain-induced barrier lowering (DIBL). [ABSTRACT FROM AUTHOR]

In this work, we investigate a low temperature boron (B) and phosphorus (P) activation in amorphous (α)-Ge using metal-induced crystallization technique. Eight candidates of metals (Pd, Cu, Ni, Au, Co, Al, Pt, and Ti) are used to crystallize the α-Ge at a low temperature. Resistivity measurement, transmission electron microscopy, and x-ray diffraction analyses reveal behaviors of the metal-induced dopant activation process using the metals reacting with α-Ge. It is revealed that Co achieves the highest B and P activation ratio in Ge below 360 °C with a slow diffusion rate. This method can be utilized to activate gate, source, and drain of transistors on upper layers in three-dimensional integrated circuits, where low temperature processing is critical. [ABSTRACT FROM AUTHOR]