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Partial bias schemes reduce the disturbance during the writing of crossbar arrays (CBAs). Detailed analysis of two partial bias schemes is presented in this paper: 1) 1/2 bias scheme for low-power operation and 2) 1/3 bias scheme for high-performance (i.e., high Vdd) operation. With partial bias schemes, a sneak leakage reversal phenomenon may occur due to line-resistance-induced voltage degradation, which provides a measure of voltage driving range along access lines. Voltage dividing effect of selector devices reduces disturbance in CBAs and leads to similar writing voltage margin in both bias schemes. Matching a proper partial bias scheme with the selector device choice optimizes the performance of CBAs. [ABSTRACT FROM AUTHOR]

This paper provides new insights into the effect of device characteristics on multilevel-cell (MLC) operation, aiming at potential benefits, such as the reduction of write latency and peripheral circuit design overhead. A general categorization of the MLC-operating schemes in storage-class memory (SCM) is proposed to connect the total number of write inputs with fundamental device properties. The categorization method is validated using two resistive random access memory devices based on different switching mechanisms. Favorable device characteristics and the corresponding simplified MLC operating schemes are addressed to facilitate future development of MLC SCM. [ABSTRACT FROM AUTHOR]

In this paper, the use of HfO2-based oxide-based resistive memory (OxRAM) devices operated in binary mode to implement synapses in a convolutional neural network (CNN) is studied. We employed an artificial synapse composed of multiple OxRAM cells connected in parallel, thereby providing synaptic efficacies. Electrical characterization results show that the proposed HfO2-based OxRAM technology offers good electrical properties in terms of endurance ( > 10^8 cycles), speed (<10 ns), and low energy (<10 pJ), and thus being well suited for neuromorphic applications. A device physical model is developed in order to study the variability of the resistance as a function of the stochastic position of oxygen vacancies in 3-D. Finally, the proposed binary OxRAM synapse has been used for CNN system-level simulations. High accuracy (recognition rate > 98%) is demonstrated for a complex visual pattern recognition application. We demonstrated that the resistance variability and the reduced memory window of the OxRAM cells when operated at extremely low programming conditions (<10 pJ per switching event) have a small impact on the performances of proposed OxRAM-based CNN (recognition rate 94%). [ABSTRACT FROM AUTHOR]

In this paper, we investigate the random telegraph noise (RTN) in hafnium-oxide resistive random access memories in high resistive state (HRS). The current fluctuations are analyzed by decomposing the multilevel RTN signal into two-level RTN traces using a factorial hidden Markov model approach, which allows extracting the properties of the traps originating the RTN. The current fluctuations, statistically analyzed on devices with a different stack reset at different voltages, are attributed to the activation and deactivation of defects in the oxidized tip of the conductive filament, assisting the trap-assisted tunneling transport in HRS. The physical mechanisms responsible for the defect activation are discussed. We find that RTN current fluctuations can be due to either the coulomb interaction between oxygen vacancies (normally assisting the charge transport) and the electron charge trapped at interstitial oxygen defects, or the metastable defect configuration of oxygen vacancies assisting the electron transport in HRS. A consistent microscopic description of the phenomenon is proposed, linking the material properties to the device performance. [ABSTRACT FROM AUTHOR]

Hf0.5Zr0.5O2 (HfZrO) thin-film ferroelectric materials have recently drawn considerable attention due to their attractive properties such as large bandgap (>5 eV), extreme thin thickness ( ${\le} 10$ nm), and good Si-compatibility. However, high crystallization temperature (600 °C–1000 °C) and relatively low remanent polarization ( ${P}_{r}$ ) compared to conventional perovskite ferroelectric materials are not suitable for flexible energy related devices, and are insufficient to overcome the barriers of conventional ferroelectric memory. In this paper, we investigated the effect of high-pressure postmetallization annealing (HPPMA) on the ferroelectric properties of the HfZrO metal–ferroelectric–metal (MFM) devices. HfZrO MFM capacitors annealed at 450 °C/50 bar shows a ${P}_{r}$ value of over 20 $\mu \text{C}$ /cm2 which is very advanced ${P}_{r}$ value. Based on the short-pulse switching technique, we quantitatively and systematically examined the improved characteristics of HfZrO prepared by HPPMA in terms of coercive field ( ${E}_{c}$ ) and possibly involved interfacial capacitance ( ${C}_{i}$ ). [ABSTRACT FROM AUTHOR]

A model of resistive random access memory (RRAM) cells aimed at providing an optimal programming/erase scheme in which the timing and biasing can be accurately optimized is proposed and implemented. To expedite technology development with an emphasis on ICs, a predictive model to capture the physical operation of every memory cell is needed. Although a number of compact RRAM models have been developed, this paper further considers the time-dependent reset process and the heat transfer in the conductive filaments. These phenomena are becoming critical in scaled memory cells and need to be carefully addressed. Due to the physical nature of the model, model parameters can be straightforwardly calibrated, relying on limited measurement data. The compact model is implemented using Verilog-A, and it is flexible for different circuit simulators. [ABSTRACT FROM PUBLISHER]

All resistive switching memory devices face a critical voltage-time dilemma, as they require fast write at moderate voltage together with disturb immunity at lower (read) voltage. In this paper, excellent voltage-time characteristics are demonstrated on a 90-nm CMOS-friendly W/Al2O3/TiW/Cu conductive-bridging memory cell. The switching voltage was evaluated in the large write pulsewidth range between 10 ns and 10 s, from which a very low slope of $\sim 75$ mV/decade was extracted. These characteristics allow, on the one hand, a fast switching (10 ns) at <3 V, and, on the other hand, excellent voltage-disturb immunity extrapolated to ±0.5 V for 10 years. Both constant-voltage-stress and read-endurance tests supported these predictions. By means of conductive-atomic-force microscopy tomography, the hourglass shape of the Cu filament was evidenced. Both the more distributed electrical field induced by this shape along the filament and the analysis of a charge-transfer (redox) reaction as rate-limiting mechanism in the switching process are discussed as the origins of this excellent disturb immunity. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive simulation analysis of the dynamic operation of T-RAM cells. The analysis addresses the evolution of cell electrostatics and of carrier concentrations and flows in the device when the gate voltage undergoes a fast low-to-high switch, as required by both read and write operations. The results clarify, first of all, the basic physics making holes in the p-base the physical element allowing information storage in the device. From this starting point, the working principles exploited for DRAM operation of the memory cell are then explained. [ABSTRACT FROM AUTHOR]

Recently, spin-transfer torque magnetic random access memory (STT-MRAM) has been considered as a promising universal memory candidate for future memory and computing systems, thanks to its nonvolatility, high speed, low power, good endurance, and scalability. However, as technology scales down, STT-MRAM suffers from serious process variations and thermal fluctuations, which greatly degrade the performance and stability of STT-MRAM. In general, the optimization and robustness of STT-MRAM under process variations often require a hybrid design flow and multilevel codesign strategies. In this paper, we quantitatively analyze the impacts of process variations and thermal fluctuations on the STT-MRAM performances from physics, technology, and circuit design point of views. Based on the analyses, we found that readability is becoming the newest challenge for deeply scaled STT-MRAM due to the conflict between sensing margin and read disturbance. To deal with this problem, a novel reconfigurable design strategy from device, circuit, and architecture codesign perspective is then presented. Finally, a conceptual hybrid magnetic/CMOS design flow is also proposed for STT-MRAM in deeply scaled technology nodes. [ABSTRACT FROM AUTHOR]

The current-induced perpendicular magnetic anisotropy magnetic tunnel junctions (p-MTJs) offer a number of advantages, such as high density and high speed. As p-MTJs downscale to $\sim 40$ nm, further performance enhancements can be realized thanks to high spin-torque efficiency, i.e., lower critical current density and higher thermal stability. In this paper, we investigate the origin of high spin-torque efficiency and give a phenomenological theory to describe the critical current reduction due to the subvolume activation. Based on various physical theories and structural parameters, a compact model of nanoscale MTJ is developed and demonstrates a satisfactory agreement with experimental results. Dynamic, static, and stochastic switching behaviors have been addressed and validated. Then, we perform mixed simulations for hybrid MTJ/CMOS read/write circuits, magnetic random access memory, and magnetic flip-flop to evaluate their performance. Analyses of energy consumption are given to show the prospect of MTJ technology node miniaturization. [ABSTRACT FROM AUTHOR]

Through their high gain and low saturation voltage, source-gated transistors (SGTs) have applications in both analog and digital thin-film circuits. In this paper, we show how we can design SGT-based logic gates, which are practically unaffected by temperature variations. We discuss design characteristics, which ensure reliable operation in spite of SGT temperature dependence of drain current, and their implications for manufacturability and large signal operation. [ABSTRACT FROM AUTHOR]

This paper reports on modeling and analysis of power delivery network (PDN) impedance and switching noise in through silicon via (TSV)-based 3-D integration. PDN is simulated in SPICE with the combination of lumped-element models and distributed-element models, where the elements are extracted from full-wave electromagnetic modeling. PDN impedance explicitly distinguishes the contributions from off-chip PDN and on-chip PDN, and reveals the TSV-induced resonant effect associated with the 3-D chip stack. The simultaneously switching noises in PDN are simulated and analyzed in different frequency regions, in which 3-D integration has distinct impacts on the PDN impedance. [ABSTRACT FROM AUTHOR]

This paper presents ferroelectric single-electron transistors (SETs) with tunable tunnel barriers and their application in a reconfigurable binary decision diagram (BDD) logic architecture. In this experimental demonstration, the SETs can be programmed into short, open, and Coulomb blockade modes to construct the BDD fabric. We experimentally demonstrate the decision node, consisting of two SETs, with robust path switching characteristics. Harnessing such programmability and path switching features, a nonvolatile reconfigurable low-power BDD logic is achieved. A ferroelectric dielectric-based split gate configuration and a differential biasing scheme are utilized to share the programming resources and reduce the energy consumption. Peripheral interface circuits are designed to recover the output signal swing for cascaded BDD logic demonstration and to provide noise immunity. The simulation shows that with sufficient circuitry complexity or a latched dynamic CMOS interface, the proposed BDD architecture achieves higher power efficiency than CMOS at the same throughput delay. [ABSTRACT FROM AUTHOR]

This paper proposes a domain-wall-coupling-based magnetic device for high-speed and robust on-chip cache applications. The read and write current paths are magnetically coupled and electrically isolated, which significantly improves the reliability of the read and write operations. Our proposed device makes use of fast and energy-efficient domain wall motion for write operation. A complementary polarizer structure is used to achieve low-power, high-speed, and high-sensing margin read operations. A device-to-circuits simulation framework was also developed to evaluate our proposed multiterminal domain-wall-coupling-based spin-transfer torque (DWCSTT) magnetic random access memory (MRAM) cell. Compared with the conventional 1T-1MTJ STT-MRAM bit cell, the proposed DWCSTT bit cell achieves >3.5\times improvement in write power under iso-area and iso-write margin conditions, and $>\!\!3\times $ better sensing margin with low read power consumption and higher read disturb margin. [ABSTRACT FROM AUTHOR]

The modular multilevel converter (MMC) is the most promising converter topology for medium- and high-power applications. One of the main concerns in the operation of the MMC, particularly for high-power applications, is its efficiency, which should be maximized. Silicon Carbide (SiC)-based devices have the potential to provide significant efficiency improvement compared with silicon devices. However, the possibility and impact of using SiC-based devices instead of silicon devices for high-power conversion have not been thoroughly explored. This paper reports on the results obtained from a detailed study to evaluate the performance of MMCs based on medium-voltage SiC MOSFETs and diodes with hybrid MMCs that employ silicon IGBTs and SiC diodes. The results are based on detailed circuit simulations that use simple physics-based circuit models. The study suggests the potential for significant efficiency gain for MMCs based on SiC power devices. [ABSTRACT FROM AUTHOR]

Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density ( D\mathrm {\mathbf {it}} ) of 3\times 10^11 \mathrmcm^-2~\mathrmeV^-1 , which causes the high channel mobility of 80 \mathrmcm^2~\mathrmV^-1~\mathrms^-1 results in very low channel resistance. The buried p+ regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 m \Omega ~\mathrmcm^\mathrm \mathbf 2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm $\times 6$ mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 m \Omega ~\mathrm{cm}^{2} and the blocking voltage of 3850 V are obtained for 3300 V application. [ABSTRACT FROM AUTHOR]

The nonlinear junction capacitances of power devices are critical for the switching transient, which should be fully considered in the modeling and transient analysis, especially for high-frequency applications. The silicon carbide (SiC) MOSFET combined with SiC Schottky Barrier Diode (SBD) is recognized as the proposed choice for high-power and high-frequency converters. However, in the existing SiC MOSFET models only the nonlinearity of gate-drain capacitance is considered meticulously, but the drain–source capacitance, which affects the switching commutation process significantly, is generally regarded as constant. In addition, the nonlinearity of diode junction capacitance is neglected in some simplified analysis. Experiments show that without full consideration of nonlinear junction capacitances, some significant deviations between simulated and measured results will emerge in the switching waveforms. In this paper, the nonlinear characteristics of drain–source capacitance in SiC MOSFET are studied in detail, and the simplified modeling methods for engineering applications are presented. On this basis, the SiC MOSFET model is improved and the simulation results with improved model correspond with the measured results much better than before, which verify the analysis and modeling. [ABSTRACT FROM AUTHOR]

Gallium nitride (GaN) devices are gathering momentum, with a number of recent market introductions for a wide range of applications such as point-of-load converters, OFF-line switching power supplies, battery chargers, and motor drives. This paper studies the basic characteristics of a 600 V cascode GaN switch, such as voltage distribution during the turn-ON and turn-OFF transition. The switching loss mechanism of the cascode GaN switch is analyzed in detail, including the impact of the package parasitic inductance in both hard- and soft-switching modes. A soft-switching 5 MHz boost converter is developed and shows the advantages and the potential of the cascode GaN. [ABSTRACT FROM AUTHOR]

Owing to their nonvolatility, outstanding endurance, high write and read speeds, and CMOS process compatibility, spin-transfer torque magnetoresistive memories (MRAMs) are prime candidates for innovative memory applications. However, the switching delay of their core components—the magnetic tunnel junctions (MTJs)—is a stochastic quantity. To account for this in electronic design, only partial models (working in extreme regimes) are available. In this paper, we propose an analytical model for the stochastic switching delay of a current-driven MTJ, with in-plane magnetization, that agrees with physical simulations, from low- to high-current regimes through intermediate regime. We performed physical macrospin simulations of MTJs for a wide range of current. We developed an analytical model for the mean switching delay that fits those simulations results, and smoothly connects well-accepted models for the extreme low and extreme high currents limits. In addition, a probability distribution in agreement with our simulations results is proposed, leading to a full model of the stochastic switching delay. An example for the application of the model is proposed. Our analytical model can help to evaluate the error rate in MRAM designs, and allow designing innovative electronic circuits that exploit the intrinsic stochastic behavior of MTJs as a beneficial feature. [ABSTRACT FROM PUBLISHER]

Electrical control of magnetic tunnel junctions (MTJs) provides opportunities to introduce MTJs into high-performance applications requiring low power consumption. The magnetic state of an MTJ can be electrically controlled through: 1) the spin transfer torque (STT) effect; 2) the voltage controlled magnetic anisotropy (VCMA) effect; and 3) the fusion of STT and VCMA. Several compact models have been published for MTJs. All of these models consider an MTJ whose magnetic state is controlled through the STT effect. In this paper, a model of an MTJ comprising a free layer, an analysis layer, and a spin polarizing layer is described. The MTJ compact model, adaptive compact MTJ (ACM) model, includes the effects of asymmetry on the MTJ behavior, and models a device controlled through the STT, VCMA, or a fused STT–VCMA mechanism. The ACM model includes the dynamics of the junction temperature. The proposed model can be adapted to experimental configurations including in-plane MTJ (IMTJ), IMTJ with a perpendicular-to-the-plane polarizer, perpendicular-to-the-plane MTJ (PMTJ), and PMTJ with an additional easy axis. The ACM model is validated with published experimental data, showing reasonably accurate results with an average error of less than 6%. [ABSTRACT FROM AUTHOR]

Chalcogenide glass-based programmable metallization cell (PMC) devices undergo Ag+-ion transport and controlled resistance change under the application of electrical bias. In this paper, photo-doped PMC devices are characterized with impedance spectroscopy. Photo doping is an important step in PMC fabrication as it introduces the mobile Ag into the electrolyte and, therefore, has a significant effect on device characteristics. Data obtained from measurements on devices with different areas in both their high resistance state (HRS) and low resistance state (LRS) are used to parameterize equivalent circuit models. The models elucidate the differences in the HRS and LRS electrical properties. [ABSTRACT FROM AUTHOR]

This paper studies the application of tunnel FET (TFET) in designing a low power and robust cellular neural network (CNN)-based associative memory (AM). The lower leakage, steeper switching slope, and higher output resistance of TFET are exploited in designing an ultralow-power TFET-based operational transconductance amplifier (OTA). A TFET-OTA is utilized as a programmable synaptic weight multiplier for CNN. The ultralow-power of TFET-OTA enables a higher connectivity network even at a lower power, and thereby improves the memory capacity and input pattern noise tolerance of CNN-AM for low power applications. The TFET-based higher connectivity CNN also exploits the unique characteristics of TFET to improve the throughput efficiency of CNN-AM. [ABSTRACT FROM AUTHOR]

The recently discovered ferroelectric behavior of HfO2-based dielectrics yields the potential to overcome the main challenges of the ferroelectric field-effect transistors (FeFETs)—CMOS compatibility as well as scalability to the state-of-the-art technology nodes of logic transistors. In this paper, we study the impact of scaling on the memory performance of FeFET devices employing Si:HfO2 ferroelectric films. The operation capability was proven down to a gate length of 28 nm. Program/erase characteristics, endurance behavior, and retention properties were analyzed for FeFETs with gate lengths scaled down to 32 nm. The detected difference in the performance between the long and short channel devices could be for the most part attributed to transistor short channel effects. In addition, the effect of temperature on the device properties of Si:HfO2-based FeFETs was investigated in detail. The program/erase speed was ascertained to be independent of temperature. On the other hand, increase in temperature resulted in reduced initial memory window accompanied by its slightly accelerated decay with time. [ABSTRACT FROM AUTHOR]

An ideal switch with hysteresis-free \(S_{\rm ideal}=0~{\rm mV/decade}\) switching is desired to keep Moore’s law alive, but has never been achieved. Classical field-effect transistors (FETs) have supported Moore’s law for 50 years, albeit with a thermodynamically limited value of subthreshold swing \(S\ge 60\) mV/decade. Alternatives, such as, tunnel FETs, impact ionization FETs, and negative capacitance FETs promise \(S <60\) mV/decade, but ideal switching is not expected, even in theory. In this paper, we propose a zero subthreshold swing FET (ZSubFET), which is similar to a classical FET with a suspended-gate and a ferroelectric gate insulator. ZSubFET exhibits ideal switching through integration of two negative capacitors (namely, a ferroelectric and an air-gap) in the gate-stack, in series with the channel capacitance. We believe that the proposed device concept should not only lower the power dissipation in an IC, but also open up new research directions for the alternative of classical-FET. [ABSTRACT FROM AUTHOR]

This paper reports the design, fabrication, characterization, and scaling analysis of novel buckling-based nanoelectromechanical relays that use, for the first time, piezoelectric actuation. The generated stress from anchored piezoelectric films is employed to buckle a clamped-clamped beam to connect suspended source and drain terminals, while the residual stress in the beam is used to control the actuation voltage. This demonstration is the first of its kind to exploit residual stress to deliver a highly scalable switching mechanism that exhibits low actuation voltage ( \(\sim 1.8\) V), very fast switching ( \(\sim 80\) ns), and uniquely achieves an equivalent electric body bias via mechanical methods. Finite-element analysis and analytical simulations show a linear dependence of the switching voltage on the residual stress, while the voltage versus stress tuning slope is reduced linearly with scaling the piezoelectric film thickness (−16.6 mV/MPa for 10-nm thick aluminum nitride film). A scaling analysis shows that millivolt switching is possible for aggressively miniaturized relays, which highlights the great impact this technology could have on demonstrating ultralow power digital circuits and memories. [ABSTRACT FROM PUBLISHER]

Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable V \(_{\rm TH}\) shifts and fluctuations, which are even visible during the I \(_{D}\) –V \(_{G}\) tracing in nanometer-scaled devices. Exploiting this feature, we have developed a methodology for random telegraph noise assessment capable of determining the capture and emission times \(\tau _{c}\) and \(\tau _{e}\) , and their impact on V \(_{\rm TH}\) as a function of gate voltage V \(_{G}\) and temperature T. This information is crucial for developing circuit simulators that assess the impact of single traps in the full V \(_{G}\) swing and operational temperatures. [ABSTRACT FROM PUBLISHER]

A compact microelectromechanical (MEM) switch design and associated family of logic gates, memory cells, and other basic very-large-scale integration (VLSI) digital circuit sub blocks are proposed to ensure zero crowbar current in addition to zero leakage current while minimizing mechanical delay. The circuit design methodology introduced in this paper also provides for lower device count and hence lower operating power consumption. A prototype of the MEM switch design is demonstrated. [ABSTRACT FROM PUBLISHER]

Resistive switching memory (RRAM) relies on the voltage-driven formation/disruption of a conductive filament (CF) across a thin insulating layer. Due to the 1-D structure of the CF and discrete nature of defects, the set and reset states of the memory device generally display statistical variability from cycle to cycle. For projecting cell downscaling and designing improved programming operations, the variability as a function of the operation parameters, such as the maximum current in the set process and maximum voltage in the reset process, need to be evaluated and understood. This paper addresses set/reset variability, presenting statistical data for HfOx-based RRAM and introducing a physics-based Monte Carlo model for switching statistics. The model can predict the distribution of the set state as a function of the compliance (maximum) current during set and distribution of the reset state as a function of the stop (maximum) voltage during reset. Numerical modeling results are finally presented to provide additional insight into discrete fluctuation events. [ABSTRACT FROM AUTHOR]

A key concern for resistive-switching random access memory (RRAM) is the read noise, due to the structural, chemical, and electrical modifications taking place at the localized current path, or conductive filament (CF). Read noise typically appears as a random telegraph noise (RTN), where the current randomly fluctuates between ON and OFF levels. This paper addresses RTN in RRAM, providing physical interpretations and models for the dependence on the programming and read conditions. First, we explain the RTN dependence on the compliance current during set transition in terms of the size-dependent depletion of carriers within the CF. Then, we discuss the bias dependence of the RTN switching times and amplitude, which can be explained by Joule heating and Poole-Frenkel barrier modifications arising from the electrostatics of the RTN fluctuating center. [ABSTRACT FROM AUTHOR]

A highly transparent resistive random access memory with a configuration of multilayer graphene (MLG)/ Dy2O3 /indium tin oxide (ITO) structure is demonstrated in this paper. The fabricated device is transparent, with 80% transmittance at 550 nm. The MLG/ Dy2O3 /ITO device shows unipolar resistance switching with a low operation current (<100~\muA) , low operation voltage (<1~V) , low power consumption (<100~\muW) , high resistance ratio (>10^4) , fast switching speed (<60~ns) , reliable data retention, and promising cycle endurance properties (>200~cycles) , which makes a step toward the realization of low-power transparent electronics for next-generation nonvolatile memory application. The MLG/ Dy2O3 /ITO device exhibited typical filamentary-conduction-type resistive random access memory behavior and no forming process is required. High resistance state (HRS) increases with a reduced device area while low resistance state (LRS) is insensitive to the device sizes. Moreover, Raman spectra obtained in pristine state, HRS, and LRS indicate that the lower power consumption of MLG/ Dy2O3 /ITO device is attributable to the formation of oxygen graphene layers. [ABSTRACT FROM AUTHOR]

This paper presents for the first time an RF nonlinearity analysis of complex multidevice radio frequency microelectromechanical system (RF MEMS) circuits. The IIP3 of different RF MEMS multidevice tunable-circuit concepts including digital MEMS varactor banks, MEMS switched capacitor banks, distributed MEMS phase shifters, and MEMS tunable filters, is investigated. Closed-form analytical formulas for the IIP3 of MEMS multidevice circuit concepts are derived. A nonlinearity analysis, based on measured device parameters, is presented for exemplary circuits of the different concepts using a multidevice nonlinear electromechanical circuit model implemented in Agilent Advanced Design System. The results of the nonlinear electromechanical model are also compared with the calculated IIP3 using derived equations for the digital MEMS varactor bank and MEMS switched capacitor bank. The degradation of the overall circuit linearity with increasing number of device stages is also investigated, with the conclusion that the overall circuit IIP3 is reduced by half when doubling the number of stages, if proper design precautions are not taken. Design rules are presented so that the mechanical parameters and thus the IIP3 of the individual device stages can be optimized to achieve a higher overall IIP3 for the whole circuit. In addition, the nonlinearity of a novel MEMS tunable capacitor concept introduced by the authors, based on an MEMS actuator with discrete tuning steps, is discussed and the IIP3 is calculated using derived analytical formulas. [ABSTRACT FROM PUBLISHER]

Metal/NiO/Pt films with various electrodes were fabricated to investigate the effects of standard free energy (SFE) on NiO resistive switching devices. By selecting Ti, Ta, Ag, Cu, and Co as the top electrodes (TEs), we found that the switching voltage was inversely proportional to the SFE. The reason for this is attributed to the different thicknesses of the oxidized interface between TE and NiO. Since the thickness of the oxidized interface depends on the SFE, this paper provides an effective way to control and adjust the switching voltage. [ABSTRACT FROM PUBLISHER]

We demonstrate a metal sandwiched Al-doped zinc tin oxide (AZTO) thin-film device to exhibit a characteristic evolution process from Schottky junction diode to resistive-switching random access memory (RRAM) applications. The proposed TiN/Ti/AZTO/Pt device can initially show good rectifying characteristics and high forward-bias current for Schottky diodes. After applying with an electrically triggered forming process, the transition of electrical behavior occurs and evolves from the diode to RRAM characteristics. The RRAM device exhibits the coexistence of bipolar and unipolar resistive-switching modes through the positive-bias forming and reversed-bias forming process, respectively. In addition, the RRAM device with bipolar mode can perform the functionality of multilevel cell storage, while the one with unipolar mode shows stable resistive-switching performance. Furthermore, one-transistor and one-resistor (1T1R) architecture with an RRAM cell connected with a thin-film transistor (TFT) device is developed in this paper. The TFT device using AZTO film as an active channel layer performs good electrical characteristics for a driver in the 1T1R operation scheme. The integration of AZTO-based electronic devices has great potential for increasing the application diversity of metal oxide AZTO thin film as well as the flexibility of circuit design in the emerging optoelectronic technologies. [ABSTRACT FROM PUBLISHER]

In this paper, we show performance and reliability improvement of Ag-GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2\--30\-nm~GeS2) leads to a resistance ratio (ROFF/RON) higher than 10^6 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications. [ABSTRACT FROM AUTHOR]

This paper investigates and models the dc behavior of thin-film-based switching devices. The devices are based on sputtered vanadium dioxide thin films that transition from 200 k\Omega/\square at room temperature to 390 \Omega/\square at temperatures above 68^\circC, with the transition occurring over a narrow temperature range. The device resistance is characterized over temperature and under current- and voltage-sourced electrical bias. The finite-element model predicts the device's nonuniform switching behavior. Electrothermally heated devices show the same transition ratio and switching behavior as externally heated devices suggesting a purely electrothermal switching mechanism. [ABSTRACT FROM PUBLISHER]

Emerging nonvolatile memories based on resistive switching mechanisms pull intense research and development efforts from both academia and industry. Oxide-based resistive random access memories (OxRAM) gather noteworthy performances, such as fast WRITE/READ speed, low power, high endurance, and large integration density that outperform conventional flash memories. To fully explore new design concepts, such as distributed memory in logic or biomimetic architectures, robust OxRAM compact models must be developed and implemented into electrical simulators to assess performances at a circuit level. In this paper, we propose a physics-based compact model used in electrical simulator for bipolar OxRAM memories. After uncovering the theoretical background and the set of relevant physical parameters, this model is confronted to experimental electrical data. The excellent agreement with these data suggests that this model can be confidently implemented into circuit simulators for design purpose. [ABSTRACT FROM PUBLISHER]

This paper demonstrates the efficacy of phase-change (PC) vias in reconfiguring RF front-end circuits for multiband/multi-standard operation. Constructed using two series-connected (SC) GeTe vias, a PC switch can be reversibly transformed between a high R{OFF} state and a low R{ON} state within 1 \mus. Using such PC switches to switch the inductor in a resonator, two LC voltage-controlled oscillators (VCOs) based on: 1) a SC and 2) a coupling-controlled (CC) resonator are developed. Designed and fabricated in 0.13-\mum CMOS in conjunction with an in-house GeTe process, the VCOs can switch their operating frequency over widely separated bands. Wide tuning ranges of 2.89–4.23/(4.93–7.79) and 4.80–8.53/(5.28–10.20) GHz were achieved in the off/on state for the SC/(CC) VCOs. The measured phase noise over the entire tuning range was lower than -103.4 and -102.7~dBc/Hz, at a 1-MHz offset frequency, respectively. [ABSTRACT FROM AUTHOR]

The sub-threshold swing (S) defines the sharpness of ON-OFF switching of a field effect transistor (FET), with S=0 corresponding to abrupt switching characteristics. While thermodynamics dictate S\geq 60~mV/decade for classical FETs, a new class of switches which we call “Landau switches” e.g., suspended gate FET (SG-FET) and ferroelectric FET (FE-FET) use inherently unstable (negative capacitance) gate insulators to achieve abrupt switching. Unfortunately, S=0 switching in Landau switches is always achieved at the expense of an intrinsic hysteresis, making them unsuitable for low-power applications. The fundamental question therefore is: under what conditions, hysteresis-free abrupt switching can be achieved in a Landau switch? In this paper, we first provide an intuitive classification of all semiconductor FETs in terms of their energy landscapes and identify a two-well energy landscape as the characteristic feature of all Landau switches. We then use the SG-FET as an illustrative example to conclude that a flat energy landscape is essential for hysteresis-free abrupt switching. In contrast, a hysteresis-free smooth switching (S\leq 60~mV/decade) is less restrictive, and is obtained by stabilizing the unstable gate insulator in its negative capacitance regime. Our conclusions have broad implications for the analysis and design of ultralow power sub-60 mV/decade switches. [ABSTRACT FROM AUTHOR]

The programming speed in a phase change memory (PCM) relies on the kinetics of crystallization in the pulsed regime. To predict the programming speed and retention of a PCM, a careful understanding and modeling of crystallization in the phase change material is essential. In this paper, we study crystallization kinetics directly in PCM devices. From thermal annealing and pulsed-set experiments, we extract the temperature dependence of the crystallization in a wide temperature range between 170^\circC and the melting point (about 620^\circC). Our results indicate two markedly different activation energies below/above 300^\circC, thus providing evidence for a non-Arrhenius crystallization kinetics in PCM. [ABSTRACT FROM PUBLISHER]

In this paper, we optimize the stack of a 90-nm CMOS-friendly W\backslashAl2O3\backslashCu conductive-bridging random access memory cell integrated in the one-transistor/one-resistor configuration. We show that the excellent Cu buffering properties of a TiW layer inserted at the Al2O3\backslashCu interface make it possible, on one hand, to ensure cell integrity after back-end-of-line processing at 400^\circC and, on the other, to obtain excellent memory performances. After optimization of the Al2O3 layer thickness, the cell exhibits highly controlled set and reset operations, a large memory window, fast pulse programming (10 ns) at low voltage (<3~V), and low-current (10 \muA), and multilevel operation. Finally, 10^6 cycles of write endurance lifetime with up to a three-decade memory window is demonstrated, and state stability is assessed up to 125^\circC. [ABSTRACT FROM AUTHOR]

This paper presents a physical model for program and retention transients in ferroelectric (FE) and charge hybrid nonvolatile memory. A region-by-region statistical model for domain switching in polycrystalline FEs was incorporated with the tunneling current simulations to predict the memory window (\Delta VTH) evolution during program and retention operations. The simulations validated the two-step program mechanism experimentally observed in such memories: rapid initial domain switching on account of high fields in the FE layer followed by field enhancement in the tunneling dielectric which initiates electron injection into the storage nodes. Further, these simulations were shown to accurately account for individual \Delta VTH from the two additive memory mechanisms at all program times. The depolarization effect was shown to be dominant for \Delta VTH loss at short and moderate retention time scales (<100~s). This model was further used to provide realistic estimates in achieving dual speed program and the corresponding dual mode retention characteristics akin to a DRAM and flash hybrid operation. [ABSTRACT FROM AUTHOR]

The electron–hole bilayer tunnel field-effect transistor (EHBTFET) is an electronic switch that uses 2-D-2-D sub-band-to-sub-band tunneling (BTBT) between electron and hole inversion layers and shows significant subthermal swing over several decades of current due to the step-like 2-D density of states behavior. In this paper, EHBTFET has been simulated using a quantum mechanical model. The model results are compared against transactions on computer-aided design simulations and remarkable differences show the importance of quantum effects and dimensionality in this device. Ge EHBTFET with channel thickness of 10 nm results as a promising device for low supply voltage, subthreshold logic applications, with a super steep switching behavior featuring SSavg\sim 40~\rm mV/\rm dec up to VDD. Furthermore, it has been demonstrated that high on current levels (\sim40~\muA/\mum) can be achieved due to the transition from phonon-assisted BTBT to direct BTBT at higher biases. [ABSTRACT FROM AUTHOR]

In conventional integrated circuit technologies, a grounded metal guard ring (MGR) is widely used to mitigate the coupling effect between any pair of inductors. Full-wave electromagnetic (EM) simulation results indicate that the guard ring size can significantly affect the inductance value of a single-turn planar inductor. This paper proposes a switchable artificial grounded MGR technique that can not only serve as a guard ring but also change the inductance. Accordingly, an inductor, featuring switchable inductance and high quality factor, is developed for a 60-GHz millimeter-wave wide-frequency tuning range (wide-FTR) and low phase-noise voltage-controlled oscillator (VCO) in 90-nm bulk CMOS technology. The VCO testkey achieves a total tuning range of 9.43 GHz (17%). The measured phase noise levels are -92.2 and -119 dBc/Hz at 1- and 10-MHz offsets, respectively. The experimental results demonstrate that the proposed inductor topology offers the VCO an increase of 36% in the FTR and a competitive performance in phase noise, as contrasted with a conventional varactor-tuned VCO. This VCO achieves a record of -188 dBc/Hz for the \FOMT. [ABSTRACT FROM PUBLISHER]

Soft-switching techniques are very attractive and often mandatory requirements in medium-voltage and medium-frequency applications such as solid-state transformers. The effectiveness of these soft-switching techniques is tightly related to the dynamic behavior of the internal stored charge in the utilized semiconductor devices. For this reason, this paper analyzes the behavior of the internal charge dynamics in high-voltage (HV) semiconductors, giving a clear base to perform overall converter optimizations and to understand the previously proposed zero-current-switching techniques for insulated-gate bipolar-transistor (IGBT)-based resonant dual active bridges. From these previous approaches, the two main concepts that allow switching loss reduction in HV semiconductors are identified: 1) shaping of the conducted current in order to achieve a high recombination time in the previously conducting semiconductors; and 2) achieving zero-voltage-switching (ZVS) in the turning-on device. The means to implement these techniques in a triangular-current-mode dual-active-bridge converter, together with the benefits of the proposed approaches, are analyzed and experimentally verified with a 1.7-kV IGBT-based neutral-point-clamped (NPC) bridge. Additionally, the impact of the modified currents in the converter's performance is quantified in order to determine the benefits of the introduced concepts in the overall converter. [ABSTRACT FROM PUBLISHER]

The resistive random access memory (RRAM) crossbar array has been extensively studied as one of the most promising candidates for future high-density nonvolatile memory technology. However, some problems caused by circuit and device interaction, such as sneak leakage paths, result in limited array size and large power consumption, which degrade the array performance significantly. Thus, the analysis on circuit and device interaction issue is imperative. In this paper, a simulation method is developed to investigate the critical issues correlated with the interaction between devices and the circuit. The simulations show that a large off/on ratio of resistance states of RRAM is beneficial for large readout margin (i.e., array size). The existence of the selector connected in series with an RRAM device can eliminate the need for high Ron resistance, which is critical for the array consisted of only RRAM cells. The readout margin is more sensitive to the variation of Ron and is determined by the nonlinearity of the I–V characteristics of RRAM, whereas the nonlinear characteristics of the selector device are beneficial for a larger readout margin. An optimal design scheme for turn-on voltage and conductance of the selector is proposed based on the simulation. [ABSTRACT FROM PUBLISHER]

This paper describes the application of electrical circuit simulations in intelligent power module development for hybrid vehicles, electric vehicles, and fuel cell vehicles. The limitations of the conventional design and simulation systems are discussed, and efforts for overcoming these limitations are described. The introduction of a physics-based insulated-gate-bipolar-transistor model with a surface-potential MOSFET core into the design flow is described. Finally, future expectations for necessary simulation technology development are given. [ABSTRACT FROM PUBLISHER]

Resistive-switching random access memory (RRAM) devices utilizing a crossbar architecture represent a promising alternative for Flash replacement in high-density data storage applications. However, RRAM crossbar arrays require the adoption of diodelike select devices with high on–off -current ratio and with sufficient endurance. To avoid the use of select devices, one should develop passive arrays where the nonlinear characteristic of the RRAM device itself provides self-selection during read and write. This paper discusses the complementary switching (CS) in hafnium oxide RRAM, where the logic bit can be encoded in two high-resistance levels, thus being immune from leakage currents and related sneak-through effects in the crossbar array. The CS physical mechanism is described through simulation results by an ion-migration model for bipolar switching. Results from pulsed-regime characterization are shown, demonstrating that CS can be operated at least in the 10-ns time scale. The minimization of the reset current is finally discussed. [ABSTRACT FROM AUTHOR]

In this paper, we study the effect of highly doped n^+/p^+ Si as the bottom electrode on unipolar RRAM with Ni-electrode/\HfOx structure. With heavily doped p^+-Si as the bottom electrode, RRAM devices illustrate the coexistence of the bipolar and the unipolar resistive switching. Meanwhile, by substituting heavily doped n^+-Si, the switching behavior changes to that of the self-rectifying unipolar device. The asymmetry and rectifying reproducible behavior in a n^+-\Si/HfOx/\Ni device resulted from the Schottky barrier of defect states in the \SiOx/\HfOx junction and n^+ Si substrate, but this behavior is not seen for the p^+-Si bottom electrode case. With rectifying characteristics and high forward current density observed in the \Ni/HfOx/\n^{+}\Si device, the sneak current path in the conventional crossbar architecture was significantly suppressed. We believe that the proposed structure is a promising candidate for future crossbar-type RRAM applications. [ABSTRACT FROM AUTHOR]

In this paper, the resistive switching behavior of a single-component-polymer resistive memory device based on polychloro-para-xylylene (parylene-C) is comprehensively studied. With the excellent chemical stability and high process compatibility of parylene-C, an 8 \times 8 crossbar array with a sandwiched structure of parylene-C and active electrodes is fabricated, which can be integrated in the CMOS back-end process and shows great potentials for future transparent, low-cost, flexible, and high-density nonvolatile memory applications. This organic memory device exhibits excellent performance with a \10^7 on/ off current ratio, nanosecond set/reset speed, and low switching voltages, as well as good retention and cycling endurance behaviors. The switching mechanism is systematically investigated with the comparison between active electrodes (Al, Cu, or Ag) and an inert electrode (Pt), as well as the dependence on temperature and device area. [ABSTRACT FROM AUTHOR]

The amorphous phase of the chalcogenide material in phase-change memory (PCM) devices is sensitive to temperature-activated crystallization and structural relaxation (SR). The latter leads to a change of device/material properties, such as the mobility band gap, the resistance, and the threshold voltage VT for threshold switching. In this paper, we present a VT drift model based on physical descriptions of the electrical transport, the threshold switching, and the SR. We introduce an analytical formula describing the relation between the drift slopes of resistance and VT via the subthreshold slope STS of the I– V curve. A numerical model predicting the time evolution of VT for different programmed states in the PCM multilevel cell is finally presented and compared with experiments. [ABSTRACT FROM PUBLISHER]