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The primary requirement for multimedia applications is energy efficient design along with computational efficiency of portable devices. This work proposes an energy efficient MAC with error compensating novel approximate adder and approximate multiplier. The proposed approximate hierarchical adder (AXHA – N) has the advantage of zero carry propagation and consists of only two gate levels which deliver very high speed and very low energy consumption along with the near to zero mean error distances. The proposed approximate 4 - bit multiplier also has no carry propagation from Least Significant Bit (LSB) to Most Significant Bit (MSB), which leads to high speed with very low energy consumption and acceptable error profiles. Higher bit size multipliers can be built using the proposed modified recursive multiplication scheme. This work proposes three variants A X M A C 1 , A X M A C 2 , A X M A C 3 basing on one or both of adder and multiplier being approximate. The proposed A X M A C 3 with any k , has energy savings ranging from 40% to 60% for different A x L when compared to accurate with Mean Error Distance between − 358 and 4305. The MED for A X M A C 3 with k = 8 , A X L = 4 is only 0.7% of the maximum possible value with 60% energy savings. The MED for A X M A C 3 with k = 12 s , A X L = 4 is only 0.8% of the maximum possible value with 57% energy savings. Mean Relative Error Distance (MRED) and Normalised Mean Error Distance (NMED) are also evaluated and presented in the paper for wholesome evaluation of AXMAC. The (Energy savings, MRED, MED) tuple 8 − b i t MAC for design of Adams et al., (2019) with k = 8 is (26.9%, 0.1, − 15048), for proposed A X M A C 3 with similar configuration has (57%, 0.01, 3663). • This work proposes an energy-efficient unsigned MAC with self-error compensating novel approximate adder and approximate multiplier. • The proposed higher size multipliers (AXM - N) recursively using the proposed approximate 4 - bit multipliers by which a balance between error tuning and parallelism can be obtained. • The proposed approximate hierarchical adder has the advantage of zero carry propagation and consists of only two gate levels which deliver very high speed and very low energy consumption along with the near to zero mean error distances. • This work proposes three variants AXMAC1, AXMAC2, AXMAC3 basing on one or both of adder and multiplier being approximate. • The proposed AXM AC3 with any k, has energy savings ranging from 40% to 60% for different AxL when compared to accurate with MED between − 358 and 4305. The deviation i.e., MED for AXMAC3 with k = 8, AXL = 4 is only 0.7% of the maximum possible value for 60% energy savings. The deviation i.e., MED for AXMAC3 with k = 12, AXL = 4 is only 0.8% of the maximum possible value for 57% energy savings. [ABSTRACT FROM AUTHOR]

Internet of Things and growing popularity of connected devices are increasing the demand for wearables applications, which is driving the development of ultra-low power secure systems. Thus, having a system running at low voltage with low power consumption introduces the use of ambient energy harvesting. Besides, batteries have several limitations reducing their compatibility with wearables, including periodical need for recharge, limited life-time, heavy and large form factor and non-eco-friendly life-cycle. Therefore ambient energy harvesting technology gives a promising alternative for self-powered wearables. The integration of these solutions on the same silicon support is a real technological challenge. This paper proposes a multi-harvesting fully-integrated system architecture combining AC and DC sources. Based on a MATLAB/Simulink model, the proposed system allows the calibration of an optimal solution. It is designed and simulated in 40 nm CMOS process, demonstrating the use of an AC source as secondary input to start a harvesting system with very low DC source as main source. • Ambient energy harvesting technology gives a promising alternative for self-powered wearables. • Multi-harvesting fully-integrated system architecture combining AC and DC sources. • Energy harvesting system level modeling using MATLAB/Simulink. [ABSTRACT FROM AUTHOR]

Approximate Computing techniques are finding a central role in modern applications, by optimizing architectures to relax some computation but with a constrained inaccuracy. In many applications, the FFT algorithm is invariably applied and there is a need for approximate low energy hardware solutions to the FFT. The paper thus proposes an approximate, fixed-point, in-place, shared memory architecture for FFT. It is well observed that the energy at FFT I/Os is not strictly contiguous, hence the proposed FFT exploits this window to tune the error. The proposed FFT and its associated butterfly unit is constructed to efficiently incorporate approximate Toom–Cook multiplication. As said, a supporting function in error correction based on the sparsity patterns, is a feature of this design. The design synthesized at 32 n m shows on average, a 48.6% and 52.8% improvement in consumption of area and energy, respectively, with as less error as 0.1% with pruning. • Approximate Computing can exploit error resilience of the applications to reduce chip resources. • FFT is a fundamental block on chip and approximating FFT can accelerate many applications. • The proposed FFT is based on approximate Toom-Cook multiplication that has a reduced number of sub-multiplications. • Pre-computing the evaluations in Toom-Cook multiplication of the twiddle factors in the butterfly provides additional savings. • This design allows a secondary mode of operation in FFT to trade-off sparsity in the FFT outputs with the error in the final FFT sequence. [ABSTRACT FROM AUTHOR]

Nowadays, system-on-chip (SoC) integrates more processing cores and IPs with network-on-chip (NoC) for satisfying today's demands, including low power consumption and high performance, without affecting the elasticity and scalability. When the on-chip processing elements (PEs) are increased, burst traffic will be generated from memory and cache accesses. As a result, the packet transmission latency is increased, reducing the system's speed performance. This paper proposes a new hybrid Base delta Neighbourhood Indexing Sequence (BΔ-NIS) based compression method for compressing the network traffic. The previous solutions for data compression often contain incompressible packets for certain data patterns. The proposed method uses Neighbourhood Indexing Sequence (NIS) algorithm to determine the optimal codeword for uncompressible chunks of delta compression approach using zeros and ones based traversals. Because of the dynamic nature of BΔ-NIS, it is highly effective and compresses all chunks in the packets efficiently. Moreover, the concept of dynamic header flit extension is introduced in the proposed compression method, which provide unlimited scalability. The proposed BΔ-NIS algorithm is robust to packet losses and leads to significant power saving. The simulation results show that the proposed BΔ-NIS reduces the hardware overhead and overtakes the existing data compression techniques by attaining a mean compression ratio of 0.73. In addition, BΔ-NIS accomplishes 51% latency reduction compared to the baseline router (without any compression). It also minimizes the power consumption of the de/compression modules by 70.14% and 20.8% as compared to the NoΔ and FlitZip respectively. • To propose an effective data compression technique for on-chip communication network, which reduces the data traffic overhead, loss of data packet, delay, and energy consumption by enhancing the delta compression method using NIS. Due to reduced operations, the proposed BΔ-NIS compressor utilizes the router's bandwidth and links without consuming more power. • To reduce the network latency by exploiting the neighbourhood information on the BΔ-NIS compressor through the consideration of zero's and one's traversals. • To increase the compression ratio by identifying data patterns within a flit and an optimal codeword for uncompressible packets of the delta compression method. • To give high level of confidence in terms of compression ratio by storing the metadata of the proposed BΔ-NIS compressor in the unused portion of the header flit. [ABSTRACT FROM AUTHOR]

A new technology is much more required in this fast-growing communication world due to inability to bear the segments by the conventional wiring-based transmitting strategies and the coordinated dimensions of System on Chip (SoC). The new technology could manage the increasing enduring failures due to diminishing technology parameters. To solve the above problem, an advanced technical paradigm Network-on-Chip (NoC) was created to keep pace with the correspondence requests on this high demanding network frame. In this paper, we have dealt with Fault Tolerance Topology Design (FTTD) along with Corvus Seek Algorithm (CoSA) and Look Advanced Propinquity Enlightened Routing (LA-PER) that can tolerate the single continuous failures in joiners of NoC for specific applications. The proposed work generates fault-tolerant topology with two substitute paths between the transmitting Processing Elements (PEs) using proposed Routing Element architecture for the applications. The FTTD carefully selects the shortest substitute path with CoSA and LA-PER that led to energy reduction and minimal latency utilization. The aim of the method is to optimize the communication with less energy utilization and latency, tested with different multimedia applications against different topologies. The proposed method's outcomes exhibited the reduction in energy and latency an extent of 19.15% and 35.29%. • The proposed work generates fault-tolerant topology with two substitute paths between the transmitting Processing Elements (PEs) using proposed Routing Element architecture for the applications. • The Routing Element(RE) architecture using Look advanced Propinquity Enlightened Routing (LA-PER) for shortest path generation. • The proposed design of Fault Tolerance topology for ASNoC uses Corvus seek algorithm (CoSA) that is based on crow search algorithm. • The proposed algorithms run in Vivado 15.1 HLS and implemented in Zynq7000 series xc7z020clg484-1chip. [ABSTRACT FROM AUTHOR]

Networks on chips (NoCs) are a concept inspired by computer networks for constructing multiprocessor systems that can handle communication across processing cores. One of the most critical applications of NOC is efficient nonstop routing. Different routes exist in these networks to get from one node to another; thus, a function that can assist in determining the optimum route to the target should be available. This paper uses a new hybrid method called Sc ored R egional congestion aware and D ICA (ScRD) to select a better output channel and increase NOC performance. After applying the ScRD algorithm, the traffic packets are examined by an analyzer, which determines if the NoC traffic is local or non-local based on the number of hops. Therefore, if the traffic is local, a scoring mechanism will select a better output channel; otherwise, the best output channel will be chosen using DICA or RCA selection functions, depending on the system state and the introduced parameter. Finally, Nirgam simulation was used to test the suggested method under various traffic conditions and selection criteria. The simulation results demonstrated that the strategy outperformed delay time, throughput, and energy consumption alternatives. It reduced packet delay by 27.10% and increased throughput by 10%. When these two factors were considered, energy consumption dropped by 6.86%. Also, the synthesis results showed that the hardware cost of the proposed approach is 1.2% lower than the two basic methods. • It introduces a new output selection strategy called ScRD based on parameters that affect NoC performance. • It introduces a new method to reduce traffic based on the proposed approach of using a traffic analyzer, in which the type of traffic is determined, and then the best selection function related to the type of traffic is used. • It introduces a router architecture for energy consumption analysis, which checks energy consumption in standby mode for wormhole routers and virtual channels. Also, it provides a solution to reduce energy consumption. • It compares the simulation results with the RTL implementation. • Analyzes the hardware overhead for the proposed solution. [ABSTRACT FROM AUTHOR]

Deep neural networks (DNNs) are widely used in modern AI systems, and their dedicated accelerators have become a promising option for edge scenarios due to the energy efficiency and high performance. Since the DNN model requires significant storage and computation resources, various energy efficient DNN accelerators or algorithms have been proposed for edge devices. Many quantization algorithms for efficient DNN training have been proposed, where the weights in the DNN layers are quantified to small/zero values, therefore requiring much fewer effective bits, i.e., low-precision bits in both arithmetic and storage units. Such sparsity can be leveraged to remove non-effective bits and reduce the design cost, however at the cost of accuracy degradation, as some key operations still demand a higher precision. Therefore, in this paper, we propose a universal mixed-precision DNN accelerator architecture that can simultaneously support mixed-precision DNN arithmetic operations. A big–little core controller based on RISC-V is implemented to effectively control the datapath, and assign the arithmetic operations to full precision and low precision process units, respectively. Experimental results show that, with the proposed designs, we can save 16% chip area and 45.2% DRAM access compared with the state-of-the-art design. [Display omitted] • A mixed precision structure to process different effective bit-width weights separately. • An MCU contains two big–little RISC-V cores to control the accelerator and peripherals. • A fine-grain control flow to control the queuing operations with low hardware amount. [ABSTRACT FROM AUTHOR]

Data compression is essential to reduce high storage and communication costs for a wide range of systems and applications. Canonical Huffman coding plays a pivotal role for several compression standards. This paper presents bit-parallel static and dynamic canonical Huffman decoder implementations using an optimized lookup table approach on a fine-grain many-core processor array and an Intel FPGA. The decoder implementation results are compared with an Intel i7-4850HQ and a massively parallel Nvidia GT 750M GPU executing the corpus benchmarks: Calgary, Canterbury, Artificial, and Large. The many-core implementations achieve a scaled throughput per chip area that is 891× and 7× greater on average than the i7 and GT 750M respectively. Moreover, the many-core implementations result in a scaled energy efficiency (compressed bits decoded per energy) that is 149.5×, 3.9×, and 2.5× greater on average than the i7, GT 750M, and Intel FPGA respectively. In addition, the optimized lookup-table-based static canonical Huffman decoder on the Intel FPGA yields performance and energy efficiency improvements of 2.1× and 3.68× respectively on average compared to a dynamic canonical Huffman decoder at a 17% cost in compression ratio. • The optimized look-up table approach speeds up the canonical Huffman decoding. • Static decoder executes faster than the dynamic decoder at the cost of compression ratio. • Many-core array implementation outperforms GPU, CPU, and FPGA in terms of area and energy efficiency. [ABSTRACT FROM AUTHOR]

Network-on-Chip (NoC) is the state of the art on-chip interconnection network for packet based communication. NoCs can offer low packet latency, high bandwidth, high throughput with minimum area, better energy efficiency and fault tolerance. Routers are the basic building blocks of the NoCs. In this paper, we present the design of a Congestion Aware Router for NoC which is then implemented using Vivado HLS. The router is then used to develop a scalable NoC based on mesh topology. Using the NoC as a test bed we carry out simulations and estimate performance metrics like latency, waiting time and total packets handled for various configurations of NoC. Provisions to alter parameters like buffer depth, packet size, packet injection interval and traffic are also added. Further, we propose a simple mechanism for detecting congestion at the router. The congestion metric is then used to adapt the XY dimension order routing into a Congestion Aware minimal adaptive X/Y routing strategy with very low hardware overhead. The proposed routing method is compared against conventional XY DOR, GCA routing and RCS based routing algorithms for different parameter variations. The results show that the proposed routing method can reduce packet latency for different traffic patterns at medium packet injection rates. • A Vivado HLS implementation of NoC Simulator. • Performance metrics like latency, waiting time and total packets are estimated. • Effect of traffic pattern, size of the mesh and packet size is carried out. • Proposed routing algorithm has been compared with GCA and RCS algorithms. • HLS NoC simulator results are compared against state-of-the-art Booksim simulator. [ABSTRACT FROM AUTHOR]

Transistor threshold voltage (V t) scaling causes higher power consumption by increasing the subthreshold leakage and short-circuit currents in CMOS circuits. Leakage currents are significant contributors to the overall power consumption of digital systems-on-chip as threshold voltage, channel length, and gate oxide thickness are reduced with CMOS technology scaling. A new dual-pullup/dual-pulldown (DPU/DPD) repeater is proposed in this paper for higher energy efficiency in low-voltage and low-frequency applications. The standby mode leakage power consumption is reduced by 59.11% with the proposed clock tree as compared to the conventional 3 level H-tree operating with a power supply voltage of 1.0V in a 45 nm CMOS technology. The short-circuit currents are suppressed by selectively employing high-V t transistors in the repeaters. The clock network with the proposed buffer lowers the active mode energy consumption by up to 24.91% as compared to a conventional clock tree under equal silicon area constraint. Post layout results reveal that the statistical spread of clock skew in the DPU/DPD H-tree is also 20.60% lower than the conventional H-tree network. • A novel dual-pullup/dual-pulldown (DPU/DPD) repeater is presented for low leakage and high frequency clock distribution. • The minimum operating voltage of a clock tree is determined for achieving the lowest total energy consumption while satisfying the clock frequency and signal transition time (10% of clock cycle time) requirements at the leaves. • The influences of leakage currents on the total energy consumption of the clock trees designed with three different repeaters (conventional CMOS inverter, previously published SPLIT-IO, and the new DPU/DPD) are benchmarked at various supply voltages and frequencies. • The leakage power reduction provided with the DPU/DPD buffers is evaluated. • The impact of process parameter fluctuations on the clock skew of the novel clock distribution network is also characterized in this paper. [ABSTRACT FROM AUTHOR]

As the number of transistors on a chip surface increases, power consumption becomes more and more a serious concern. A promising solution to bridge the gap between resource-constrained gadgets and computation-intensive applications could be the approximate computing paradigm. This paper presents four efficient approximate full adder cells based on dynamic logic and carbon nanotube field-effect transistors (CNFETs). To the best of our knowledge, dynamic logic has never been deployed in the design of approximate full adders before. Comprehensive simulations and analyses are conducted to study the efficacy of the new circuits. Simulation results indicate remarkable improvements compared to state-of-the-art circuits. For instance, at 0.9 V power supply, our final proposed design improves the power-delay-area product (PDAP) metric by at least 63% compared to its peers. Moreover, the applicability of the proposed adders in the image sharpening application is examined by measuring peak signal-to-noise ratio (PSNR) and structural similarity index measure (SSIM) using the MATLAB tool. The proposed designs have also a reasonable performance in this regard. • Deploying dynamic logic (DL) in the design of approximate full adders for the first time. • Designing ultra-low area and energy consumption full adder structures. • Applying the proposed adders in the image processing application. [ABSTRACT FROM AUTHOR]

Computer-based machine learning algorithms that produce impressive performance results are computationally demanding and thus subject to high energy consumption during training and testing. Therefore, compact neuro-inspired devices are required to achieve efficiency in hardware resource consumption for the smooth implementation of neural network applications that require low energy and area. In this paper, learning characteristics and performances of the nanoscale titanium dioxide (TiO 2) based synaptic device have been analyzed by implementing it in the hardware-based neural network for digit classification. Our model is experimentally validated by using 32-nm CMOS technology and the results demonstrate that the model provides high computational ability with better accuracy and efficiency in resource consumption with low energy and less area. The proposed model exhibits 20% energy gain and 16.82% accuracy improvement and 18% less total latency compared to the state-of-the-art Ag : Si synaptic device-based neural network. Furthermore, when compared to the software-based (i.e., computer-based) implementation of neural networks, our TiO 2 -based model not only achieved an impressive accuracy rate of 90.01% on the MNIST dataset but also did so with reduced energy consumption. Consequently, our model, characterized by a low hardware implementation cost, emerges as a promising neuro-inspired hardware solution for various neural network applications. The proposed model has further demonstrated outstanding performance in experiments involving both the MNIST and Fisher's Iris datasets. On the latter dataset, the model exhibited notable precision (94.5%), recall (91.5%), and an impressive F1-score (92.9%), accompanied by a commendable accuracy rate of 93.04%. • TiO 2 -based synaptic devices offer high computational ability and efficiency with low energy. • Proposed hardware neural network with TiO 2 -based synaptic device and backpropagation. • The model provides 20% energy gain, 16.82% accuracy improvement, 18% less latency vs. Ag:Si. • TiO 2 -based model consumes less energy vs. software-based neural networks. [ABSTRACT FROM AUTHOR]

All modern low power system on a chip (SoC) architectures are equipped with an in-built power management system. Every new system is expected to have more features and lower power consumption, resulting in a continuous demand to improve energy efficiency. To cope up with the ever increasing demand, an active power-aware management verification architecture is necessary to minimize the power consumption. Power reduction techniques include clock-gating, power-gating, multi-voltage, and voltage-frequency scaling. The proposed verification architecture utilizes the Unified Power Format (UPF) 2.1 libraries to achieve early design verification at the Electronic System-Level (ESL) of abstraction. The proposed testbench can verify several designs of different power management schemes. The presented work offers a reduction in power states, CPU time and simulation time as compared to existing techniques. The interactive formal and simulation-based verification methods are used in this paper to remove the simulation artifacts during functional and power co-simulation. Additionally, this paper incorporates functional correctness and power-aware checks for different modules of Design Under Verification (DUV) at Transaction-Level Modeling (TLM). The proposed verification architecture supports active power management, TLM stimulus-based functional verification, automated register abstraction layer verification and automated coverage and power checks. The testbench architecture attains the following objectives of power-aware management and functional verification Intent: • Simulations of power-aware management unified power format (UPF) architecture using electronic system level (ESL) abstraction for early verification. Visualization of failure, isolation or retention. Automatic power checks for power management errors. • Addition of transaction-level modeling based stimulus generation in testbench for functional verification of design with assertion based self-checking mechanism. • Automated register abstraction layer implementation on testbench for register power-aware verification. • Collection of power states, transition coverage and functional coverage with automated coverage and power checks. • Implementation of real-time automation for valid scenario generation in minimum execution time. [ABSTRACT FROM AUTHOR]

Energy efficiency has emerged as one of the most essential design parameters in contemporary computing system design. Approximate computing is a new computing paradigm to achieve energy efficiency by trading-off energy/area/latency improvements with accuracy for error-resilient applications. This paper proposes R econfigurable E nergy-efficient A pproximate D ivider (READ) that achieves several energy–quality configurable modes using fixed restoring array divider architecture. Conventional approximate binary dividers require various divider hardware configurations to achieve distinct energy–quality trade-off points, which decreases the hardware flexibility, especially for modern embedded systems. READ accomplishes energy efficiency while meeting the dynamically varying accuracy requirements of the targeted application. READ uses reconfigurable subtractor cells that can work in either accurate or approximate mode using a subtractor cell controller logic. The paper also introduces the design of overflow detector using minimal hardware resources. A comprehensive accuracy and hardware evaluation on CMOS 45-nm technology node are performed for the proposed dividers as well as other state-of-the- art divider designs. Compared to the accurate 16 ∕ 8 divider design, the proposed divider shows an improvement of 49% in terms of energy efficiency and is 1.26x faster, while introducing minimal errors. The proposed divider design is demonstrated for its efficacy in image processing tasks and shows nominal effect on the output quality. • A fixed restoring array based approximate divider is proposed and presented with detailed error and circuit analysis for CMOS-45 nm technology node. • The approximate divider presented is reconfigurable in runtime which enables accuracy configurability by varying the design parameter. • Reconfigurable half and full subtractor cells are designed and proposed which achieves dual mode of operation — accurate and exact with energy savings. • Overflow detector circuit for divider design is proposed and presented which is scalable and hardware efficient. • The approximate divider designs are evaluated for image processing applications and found to be satisfactory in terms of Quality of Services (QoS). [ABSTRACT FROM AUTHOR]

In this paper, a low-complex chip to extract the Mel Frequency Cepstral Coefficient for a speech recognition system is presented. The architecture can operate in a continuous-flow manner to process streaming or the stored speech signal at high speed. The frame-overlap Hamming window, DFT and Mel-filter bank computations are deeply integrated to share memory buffers and avoid bit-reversal circuit to reduce area and latency. Moreover, normalised energy consumption and area delay product are reduced by 32%, and speed is increased by 5.2 times compared to prior works. Further, the fixed-point word-length is optimised to minimise the area without affecting the accuracy. • The paper focuses on the design of ASIC chip for the extraction of Mel Frequency Cepstral Coefficient from the speech input. • The MFCC chip process streaming or stored speech signal at high speed in continuous flow manner with a little area overhead. • The area and latency are reduced by integrating frame-overlap Hamming window, DFT and Mel Filter banks to share hardware. • The proposed architecture process a single frame with almost 5.2 times lesser clock cycles compared to other prior systems. • The reduction of area and computation cycles results in 32% reduction of area-delay product and normalized energy consumption. [ABSTRACT FROM AUTHOR]

This paper presents the Step-by-Step Design of memory hierarchy for heterogeneously-integrated SCM/NAND flash storage. The heterogeneously-integrated storages utilize multiple types of non-volatile memories such as storage class memories (SCMs) and NAND flash memories. SCMs are further classified to memory-type and storage-type. NAND flash memories are also characterized by the number of stored bits per cell. These non-volatile memories show complex trade-off of various latency, power, capacity and cost. What's worse, in NAND flash, garbage collection seriously degrades the performance. Thus, the intelligent mix & match of these memories is required, depending on each workload. For various storage applications, this paper shows that optimal SCM/NAND flash hierarchies are determined by considering system performance, energy consumption, endurance, and cost for each workload. The recommended non-volatile memory combinations with SCMs and NAND flash memories are proposed for representative 7 storage application workloads with diverse characteristics. The proposed Step-by-Step Design is the useful solution for the heterogeneously-integrated storage with multiple types of non-volatile memories and for various applications. [ABSTRACT FROM AUTHOR]

In this paper, we discuss the implementation strategies of an explicit matrix inversion technique based on the recursive Gram matrix inversion update (RGMIU) algorithm. These strategies are explicitly chosen to optimize the design for high throughput dictated by the enhanced mobile broad band (eMBB) use case and by the low latency imposed by the ultra-reliable low-latency communications (URLLCs) use case. The RGMIU algorithm is recently proposed to implement the zero forcing (ZF) problem encountered in massive multiple-input multiple-output (MIMO) detection task. We therefore compare and analyse the performance in terms of symbol error rate (SER) against popular implicit and explicit methods such as optimized coordinate descent (OCD), Gauss-Seidel (GS) and Neumann series expansion (NSE) algorithms. To determine the optimal word length, a fixed-point analysis shows that 16 bits are enough to reach a floating-point precision. We, thereafter, use Vivado High-Level Synthesis tools and optimization directives to implement the RGMIU algorithm based on three strategies to infer key insights and design trade-offs from the resource's utilization, latency, throughput and energy efficiency. • Implementation strategies of an explicit matrix inversion technique. • Design optimization for enhanced mobile and ultrareliable low-latency use cases. • Recursive Gram matrix inversion update algorithm. • High-Level Synthesis tools and optimization directives for FPGA implementation. • Strategies to infer key insights and design trade-offs. [ABSTRACT FROM AUTHOR]

In a typical embedded CPU, large on-chip storage is critical to meet high performance requirements. However, the fast increasing size of the on-chip storage based on traditional SRAM cells makes the area cost and energy consumption unsustainable for future embedded applications. Replacing SRAM with DRAM on the CPU's chip is generally considered not worthwhile because DRAM is not compatible with the common CMOS logic and requires additional processing steps beyond what is required for CMOS. However a special DRAM technology, Gain-Cell embedded-DRAM (GC-eDRAM) [1–3] is logic compatible and retains some of the good properties of DRAM (small and low power). In this paper we evaluate the performance of a novel hybrid cache memory where the data array, generally populated with SRAM cells, is replaced with GC-eDRAM cells while the tag array continues to use SRAM cells. Our evaluation of this cache demonstrates that, compared to the conventional SRAM-based designs, our novel architecture exhibits comparable performance with less energy consumption and smaller silicon area, enabling the sustainable on-chip storage scaling for future embedded CPUs. • This work exploits the latest advances in Gain-Cell technology and analyzes its potentials in low Power On-Chip memory implementation. • To our knowledge, this is the first proposal of SRAM and Gain-Cell eDRAM hybrid architecture in first level data (L1D) cache and L2 cache (SRAM tag array and GC-eDRAM data array). • We analyze tradeoffs in performance, area and power of our proposed hybrid architecture in comparison to conventional SRAM baseline. [ABSTRACT FROM AUTHOR]

In this paper, we propose some SQuare-RooT (SQRT) Carry SeLect Adder (CSLA) architectures including a high-speed design, a design with the lowest area compared to previous CSLAs, and two hybrid designs. The first proposed architecture is an optimized design of the Binary to Excess-1 Converter (BEC)-based CSLA by employing a new fast and merged add-one and multiplexing circuit. This architecture in addition to attaining much lower area, delay and energy consumption compared to the BEC CSLA, requires almost the same area compared to the best existing CSLA i.e. IRredundant Carry Generation and Selection scheme (IRCGS CSLA) while providing a higher speed. The second proposed CSLA as the lowest-area design is the area-optimized architecture of IRCGS CSLA that exploits a new logic optimization while maintaining its speed. This scheme makes use of a multiplexer-based logic to reduce the number of gates and to achieve a more compact design. In addition, two hybrid CSLAs are proposed by exploiting the benefits of both proposed CSLA architectures. Experimental results show that the hybrid CSLAs lead to lowest area-delay product and energy-delay product among all the proposed and previous designs in a wide range of 8-bit to 128-bit adder size. In fact, 10–48% reduction in area-delay product and 8–65% reduction in energy-delay product are achieved compared to previous designs. Moreover, the hybrid CSLAs outperform the best existing design with respect to all three parameters of area, delay and energy. • New carry select adder (CSLA) architectures are proposed based on previous designs, with better design parameters. • The first is an add-one based CSLA with a fast architecture and the second is a design with the lowest area among all CSLAs. • Two other CSLAs called hybrid designs are proposed based on the combination of two first designs to obtain more enhancements. • Proposed hybrid CSLAs require lower area, delay, energy and energy-delay product compared to all previous design. [ABSTRACT FROM AUTHOR]

Traditional dynamic energy management methods optimize the energy usage in wireless sensor nodes adjusting their behavior to the operating conditions. However, this comes at the cost of losing the predictability in the operation of the sensor nodes. This loss of predictability is particularly problematic for the battery life, as it determines when the nodes need to be serviced. In this paper, we propose an energy and relevance-aware monitoring method, which leverages the principles of self-awareness to address this challenge. On one hand, the relevance-aware behavior optimizes how the monitoring efforts are allocated to maximize the monitoring accuracy; while on the other hand, the power-aware behavior adjusts the overall energy consumption of the node to achieve the target battery life. The proposed method is able to balance both behaviors so as to achieve the target battery life, at the same time is able to exploit variations in the collected data to maximize the monitoring accuracy. Furthermore, the proposed method coordinates two different adaptive schemes, a dynamic sampling period scheme, and a dual prediction scheme, to adjust the behavior of the sensor node. The evaluation results show that the proposed method consistently meets its battery lifetime goal, even when the operating conditions are artificially changed, and is able to improve the mean square error of the collected signal by up to 20% with respect to the same method with the relevance-aware behavior disabled, and of up to 16% with respect the same algorithm with just the adaptive sampling period or the dual prediction scheme enabled. Consequently showing the ability of the proposed method of making appropriate decisions to balance the competing interest of its two behaviors and coordinate the two adaptive schemes to improve their performance. • The monitoring method complies with energy goals while improving monitoring accuracy. • The adaptive actions combine an adaptive sampling rate and a dual prediction scheme. • The dual prediction scheme is altered to operate with a fixed transmission rate. • The proposed monitoring method is evaluated using three different data sources. [ABSTRACT FROM AUTHOR]

The need for reconfigurable lightweight cryptographic processors with low power consumption for securing the Internet of Things (IoT) with adaptive functionalities is getting attracted due to security properties, such as data fidelity, provenance, and privacy concerns. This paper presents RECO-ASCON, a reconfigurable security processor that supports both cryptographic Hash and Hasha ASCON algorithms. The proposed design is implemented in Chisel hardware construction language, an open-source hardware library. It has been evaluated in various hardware platforms such as FPGAs, embedded systems and ASICs with various technology nodes and design flows. In the PYNQ-Z1 board, RECO-ASCON can be mapped to five processors in total with a Micro-Blaze soft-core processor for streaming data to all of them while running at 200 MHz without producing any timing violations. Moreover, mapping the proposed RECO-ASCON processor on the Nexsys4-DDR Xilinx Kit (ARTIX-7 chip) would cost ∼ two times fewer resources and run 1.25 × faster than the existing implementation of just one of the ASCON hash functions on the same family of the chip. We implement the proposed processor in 28 nm industry technology with commercial design flow, it achieves a maximum frequency of 1.12 GHz while achieving highest energy efficiency compared to the state-of-the-art implementations. The total area is only 9170. 82 um 2 in 28 nm. To further evaluate the design, we also implement it with all open-source design tools and process technology libraries in 45 nm, it achieves 1 GHz maximum frequency and consumes only 18225 um 2 in 45 nm. Overall, the proposed reconfigurable processor is compact and more energy efficient, making it a perfect candidate to be deployed in wide range of IoT systems. • RECO-ASCON is a reconfigurable processor that supports multiple hashing modes. • The design is implemented in Chisel and has been evaluated in various platforms. • RECO-ASCON achieves better energy efficiency and the highest maximum frequency. • The design has been evaluated with both commercial and open-source EDA tools. [ABSTRACT FROM AUTHOR]

Many modern compute-intensive applications require arithmetic results (usually multiplication) to be represented as analog signals. Using digital multipliers followed by digital-to-analog conversion (DAC) results in high energy and performance costs. This is because digital multipliers have costly carry propagation, and DAC circuits add associated conversion costs. Another concern, especially for arithmetic on the edge, is the need for nonvolatile operands in the face of power uncertainty. To deal with this, nonvolatile memory technologies have been combined with in-memory computing. This paper proposes a mixed-signal multiplier which directly generates an analog product based on two digital input operands. Fundamental to the design are transistor-memristor cells, organized in a crossbar structure. Using analog resistive partial product accumulation in the crossbar, the approximate multiplier eliminates the need for carry propagation and an explicit DAC. It also provides asymmetric nonvolatility making memristor writing a rare event, extending the application significance of the method. The design is shown to be functionally correct up to 4-bit, and achieves 8 × to over 300 × speedup, competitive peak-power and orders of magnitude energy reduction, compared with existing full-digital memristor-based multipliers and low-power multiplication DAC solutions. • This work analyses the precision of a memristor crossbar multiplier. • This work provides a parametric design strategy for the memristors. • This work investigates the memristor writing operation behaviour in 1T1M and 1TxM. • This work studies the memristor writing operation for multiple design requirements. • This work evaluates proposed design linearity for modelling circuit current output. • This work validates the design method of the proposed multiplier. • This work demonstrates the proposed multiplier's advantages in energy and speed. [ABSTRACT FROM AUTHOR]

This paper outlines an innovative and creative algorithm known as Discrete Antlion Trapping Mechanism (DATM). It imitates the hunting mechanism of antlions in nature. The proposed DATM is incorporated in Network on Chip (NoC) which is a replacement to standard transmission technique along with the Reliable Reconfigurable Real-Time Operating System (R3TOS) for intertask communications. Though there are many designing issues, mapping the applications to NoC is an unmanageable and challenging problem. The DATM algorithm optimizes the above problem to reduce the energy consumption and transmission charge. The DATM method follows a systematic approach to analyze the scenario similar to other topology generating algorithms. Experimental results implemented in different applications showed that the proposed mechanism saved energy consumption on an average of 16.14% and 25.15% reduction in the transmission charge compared to other topologies. • A novel DATM is proposed for topology generation of NoC for Reliable Reconfigurable Real-Time Operating System (R3TOS). • NoC in R3TOS provides a highly productive inter task communications. • DATM is inspired by the hunting behavior of antlion and its targets to generate custom topology. • Prime master acts as an important tract for achieving the best results. • Utilization of energy and transmission charge reduced effectively by implementing DATM for topology generation of APNoC. [ABSTRACT FROM AUTHOR]

This paper investigates the power-clock generation using Step Charging Circuits (SCC). In particular, the impact of the adiabatic load on the energy dissipation of the 4-phase Power-Clock Generator (PCG) and on the overall adiabatic system is investigated. The adiabatic implementations are compared with their conventional CMOS counterparts based on energy dissipation, the number of transistors and operation time. The simulation results show that the area (number of transistors) influences the energy dissipation of SCC. Operation time affects the energy dissipation of the controller and degrades the energy benefits obtained in the energy dissipation of SCC and adiabatic core. Lastly, the impact of a number of steps on the energy efficiency of the 4-phase PCG is investigated. We compare the energy efficiency of the 4-phase PCG using 2-step, 3-step and 4-step charging circuit with the energy efficiency of the existing 4-phase PCG with and without resonant inductors. • Discovered the impact of the adiabatic load on the energy dissipation of the controller and the Power Clock Generator (PCG). • Solved an unexplored problem of the impact of the number of steps in the Step Charging Circuit on energy efficiency and the energy gain. • Impact of frequency on the performance of the 4-phase PCG using n-step charging circuits is demonstrated. • The energy efficiency of the 4-phase PCG using n-step charging circuits is higher compared to the PCG with and without resonant based-PCG. [ABSTRACT FROM AUTHOR]

With the emergence of various battery operated technologies in different computing domains and the challenge of heating in such technologies, the issue of energy dissipation has become more critical than ever before. In such systems, energy constraints in one hand, and heat generation, on the other hand, necessitates the employment of energy efficient technologies in the fabrication of digital circuits. One possible solution for mitigating the energy dissipation in digital circuits is the use of adiabatic families in the process of designing computing devices. Adiabatic circuits are designed mainly based on the principles of thermodynamics and provide a paradigm shift in the design of digital systems. Nevertheless, their impact on the reliability of digital circuits due to susceptibility to soft errors has not been explored comprehensively. In this paper, we first try to survey some existing adiabatic logic families. Then we attempt to evaluate their reliability by validating their functionality under the effect of soft errors. Our evaluations which were conducted on a set of SPICE simulations have shown that amongst SCRL, 2LAL, RERL, PFAL, 2N2N2P and ECRL families the ECRL family is able to tolerate more than 90% of the injected transient faults and the applications with a high demand of reliability can use this family of adiabatic circuits. Furthermore, we will propose some suggestions for establishing reliable computations through adiabatic circuits. • Reliability evaluation of adiabatic circuits challenges some of the previous designs. • The design paradigms of adiabatic circuits vary with conventional CMOS circuits. • Frequency scaling impacts on energy loss and reliability in adiabatic circuits. • Adiabatic circuits have hardware redundancy and are capable to tolerate faults. [ABSTRACT FROM AUTHOR]

This paper explores non-volatile cache memories implemented by spin-transfer torque magnetic random access memories (STT-MRAMs) based on state-of-the-art perpendicular magnetic tunnel junctions (MTJs) and FinFETs. The use of double-barrier MTJs with two reference layers (DMTJs) is benchmarked against solutions relying on single-barrier MTJs (SMTJs) at different technology nodes (from 28-nm down to 20-nm). Our study is carried out through a cross-layer simulation platform, starting from the device- up to the system-level. Our results point out that, thanks to the reduced switching currents, DMTJ-based STT-MRAMs allow decreasing write access time of about 63% as compared to their SMTJ-based counterparts. This is achieved while assuring reduced energy consumption under both write (−42%) and read (−28%) accesses, lower area occupancy (−40%) and smaller leakage power (−25%), at the only cost of worsened read access time. This makes DMTJ-based STT-MRAM a promising candidate to replace conventional semiconductor-based cache memory for the next-generation of low-power microprocessors with on-chip non-volatility. • STT-MRAMs for cache applications based on p-MTJ and FinFET devices are investigated. • DMTJ-based STT-MRAMs are benchmarked against their SMTJ-based counterparts. • Our study is performed by a cross-layer simulation platform, from the device- up to the system-level. • DMTJ-based STT-MRAMs prove to be credible candidates for replacing SRAM-based caches in low-power applications. [ABSTRACT FROM AUTHOR]

Since first proposed in JSSC [1], phase-switching modulation has been proved to be a viable transmission scheme. In this paper, we explored the maximum data-rate of phase-switching modulation and proposed a modified quadrature oscillator with a self-bias circuit to isolate the disturbance in power supply and ground. Dividers and filter are also optimized to minimize parasitic resistor and capacitor. The prototype is fabricated in a 0.18 μm CMOS process, with an active chip area of about 0.13 mm × 0.35 mm. The total power consumption of the modulator is only 2 mW with an energy efficiency of 80 pJ/Bit. This modulator has been successfully embedded in a direct-up conversion transmitter for medical application. • We present the system design of a phase-switching modulator with maximized data rate. • We proposed a modified quadrature oscillator with a self-bias circuit to isolate the disturbance in power supply and ground. • We investigated the designs for divider and filter to explore its design space and achieve optimal performance. [ABSTRACT FROM AUTHOR]

Network-on-chip (NoC) is the most promising design paradigm for the interconnect architecture of a multiprocessor system-on-chip (MPSoC). On the downside, a NoC has a significant impact on the overall energy consumption of the system. NoC simulators are highly relevant for design space exploration even at an early stage. Since links in NoC consume up to 50% of the energy, a realistic energy consumption of links in NoC simulators is important. This work presents a simulation environment which implements a technique to precisely estimate the data dependent link energy consumption in NoCs with virtual channels for the first time. Our model works at a high level of abstraction, making it feasible to estimate the energy requirements at an early design stage. Additionally, it enables the fast evaluation and early exploration of low-power coding techniques. The presented model is applicable for 2D and 3D NoCs. A case study for an image processing application shows that the current link model leads to an underestimate of the link energy consumption by up to a factor of four. In contrast, the technique presented in this paper estimates the energy quantities precisely with an error below 1% compared to results obtained by precise, but computational extensive, bit-level simulation. • We present the first high-level model to estimate link energy for Networks-on-Chip with virtual channels at high accuracy. • Our high-level model has an error below 1% compared to precise, but computational expensive, bit-level simulations. • We contribute a Network-on-Chip simulator to provide detailed energy and performance evaluation at an early design stage. • We (re-)analyze codings in Networks-on-Chip with virtual channels as current models underestimate energy by a factor four. [ABSTRACT FROM AUTHOR]

This paper presents a novel technique named the Shrinking Circles to enhance the performance of optimization algorithms embedded in automated sizing tools of analog ICs. This technique creates a balance between the exploration and exploitation capabilities when the optimization algorithm is converging to a possible optimum point. With the help of the shrinking circles concept, we upgrade a hybridization version of Gravitational Search Algorithm with Particle Swarm Optimization (Advanced GSA_PSO). Accordingly, a developed tool for the automation of analog ICs sizing is proposed. The performance of this tool is evaluated by two cases: minimizing the power consumption of a two-stage CMOS op-amp and simultaneous minimizing the circuit area and power consumption of a folded-cascode op-amp. In this paper, the corners analysis is also incorporated into the proposed circuit sizing tool based on a straightforward procedure by which this tool not only can obtain the solutions being robust against process, voltage, and temperature (PVT) variations, but also it alleviates the computational burden. Comparisons with available methods show that the proposed tool performs much better in terms of efficiency. [ABSTRACT FROM AUTHOR]

Medical implant devices have found widespread application in recent years. The Super-Regenerative Receiver has been one preferred architecture due to its power advantage over other architectures. We present a detailed analysis of the circuits and their equivalent models to be used in system level design of a Super-Regenerative Receiver in this paper. The design procedure is also demonstrated with a receiver design example. Designs were carried out in UMC 180 nm process with a center frequency of 416 MHz for MedRadio band. Errors between the simulation results of the proposed model and actual circuits are less than 1.6% for LNA characteristics and 7% for receiver output amplitude. 10 Mbps data rate was achieved with 432 pJ/bit energy consumption over 1.8 V power supply. The study is concluded with the simulation results of the circuits and the equivalent models. • Analysis of blocks of super-regenerative receiver is carried out. • Lumped element models of super-regenerative receiver blocks are proposed. • Results of analytic solutions as well as simulation results of models and circuits were presented. • As a benchmarking case, a super-regenerative receiver is designed and the design procedure is explained in detail. [ABSTRACT FROM AUTHOR]

Abstract In this paper, a double-precision carry-save adder (CSA)-based array multiplier is designed using the Dual Mode Logic (DML) approach in a commercial 65-nm low-power CMOS technology. DML typically allows on-the-fly controllable switching at the gate level between static and dynamic operation modes. The proposed multiplier exploits this unique ability of DML to efficiently trade performance and energy consumption when considering on-demand double-precision (8 × 8-bit or 16 × 16-bit) operations. This occurs in the DML multiplier working in a mixed operation mode, i.e., by employing the static and dynamic mode for lower and higher precision operations, respectively. In fact, the use of the dynamic mode for higher precision operations ensures higher performance as compared to the standard CMOS circuit (16% gain on average) at the cost of higher energy consumption. Such energy penalty is counterbalanced at lower precision operations where the static mode is enabled in the DML circuit. Overall, the adoption of the mixed operation mode in the proposed DML multiplier proves to be beneficial to achieve a better performance/energy trade-off with respect to the standard CMOS implementation and to the case when using either the static or the dynamic mode for both operations at the two different precisions. When compared to its CMOS counterpart, our DML design operating in the mixed mode exhibits an average improvement of 15% in terms of energy-delay product (EDP) under wide-range supply voltage scaling. Such benefit is maintained over process-voltage-temperature (PVT) variations. Highlights • A double-precision (8 × 8-bit or 16 × 16-bit) multiplier is designed using the Dual Mode Logic (DML) in a 65-nm CMOS technology. • This multiplier works in a mixed operation mode by switching between static and dynamic mode according to the different precision. • Such mixed mode allows boosting the gain in energy-delay product (EDP) of the DML circuit with respect to its CMOS counterpart. • When compared to the CMOS circuit, our DML design working in the mixed mode exhibits an average gain of 15% in terms of EDP. • Such benefit is maintained over a wide range of process-voltage-temperature (PVT) variations. [ABSTRACT FROM AUTHOR]

This paper presents a clock and data recovery (CDR) topology that can adjust the power consumption with its input bit-rate. Current-mode structures are utilized to control the power consumption. The system is comprised of a phase detector, a charge pump, a second-order filter, a voltage-to-current converter, a bias controller, and a current controlled oscillator. In order to attain an ultra-low power profile, subthreshold source-coupled logic (STSCL) is used to implement the system blocks. A modified version of low-voltage current-mirror is proposed and utilized to improve the thermal stability of the CDR structure. The proposed current mirror improves the oscillator frequency variation more than 20 times. The CDR is simulated in 90 nm standard CMOS process with VDD = 1 V. It can recover clock frequencies between 1 MHz and 25 MHz. The corresponding power consumption is between 195 nW and 450 nW, and the measured deterministic-jitter is less than 100 ns. [ABSTRACT FROM AUTHOR]

In this paper, we propose a parallel and reconfigurable hardware to generate harmonic music. The generated music is composed by melodic intervals determined from the combination of cellular automata in accordance to the standard protocol, which is called the Musical Instrument Digital Interface (MIDI) protocol. The hardware architecture is implemented in Field-Programmable Gate Array (FPGA), providing an alternative efficient yet autonomous tool for the study and research related to the field of random music. The architecture utilizes four types of cellular automata, depending on four neighborhood models in cellular automata. Thus, 16 possible combinations of cellular automata models are allowed. The applicability potential of the architecture is maximized as the configuration data, which influences the generated music final product, is done almost entirely by the user, with no virtual limit of the number of possible melodic combinations to be generated by the hardware. Thus, the portable engineered equipment can come handy in many real-world applications, such as neurology. In order to emphasize the usage versatility of the proposed design, the music composed thereby is provided in MIDI, and includes all notes and musical instruments known internationally. In order to validate the effectiveness as well as efficiency of the proposed design, we present several results regarding hardware design requirements in terms of area, operation frequency and power consumption as well as those regarding the generated melody's characteristics. The results are very promising. [ABSTRACT FROM AUTHOR]

TCAM (ternary content addressable memory) is a special memory type that can compare input search data with stored data, and return location (sometime, the associated content) of matched data. TCAM is widely used in microprocessor designs as well as communication chip, e.g., IP-routing. Following technology advances of emerging nonvolatile memories (eNVM), applying eNVM to TCAM designs becomes attractive to achieve high density and low standby power. In this paper, we examined the applications of three promising eNVM technologies, i.e., magnetic tunneling junction (MTJ), memristor, and ferroelectric memory field effect transistor (FeFET), in the design of nonvolatile TCAM cells. All these technologies can achieve close-to-zero standby power though each of them has very different pros and cons. [ABSTRACT FROM AUTHOR]

Ultra-low power operation in power-limited portable devices (e.g. cell phone and smartcard) is paramount. Existing conventional CMOS consume high energy. The adiabatic logic technique has the potential of rendering energy efficient operation. In this paper, a multi-phase quasi-adiabatic implementation of 16-bit Cyclic Redundancy Check (CRC) is proposed, compliant with the ISO/IEC-14443 standard for contactless smart cards. In terms of a number of CRC bits, the design is scalable and all generator polynomials and initial load values can be accommodated. The CRC design is used as a vehicle to evaluate a range of adiabatic logic styles and power-clock strategies. The effects of voltage scaling and variations in Process-Voltage-Temperature (PVT) are also investigated providing an insight into the robustness of adiabatic logic styles. PFAL and IECRL designs using a 4-phase power-clock are shown to be both the most energy-efficient and robust designs. [ABSTRACT FROM AUTHOR]

An ultra-high current efficiency current recycling folded cascode amplifier is presented in this paper. To improve the current efficiency of conventional recycling folded cascode amplifier, it utilizes adaptive biasing class-AB input stage and local common-mode feedback techniques, leading to a boost in gain-bandwidth and slew rate. Both conventional and proposed recycling folded cascode amplifiers are designed on CSMC 180 nm process. Simulation results demonstrate that the proposed current recycling amplifier achieves 3.2 times the gain-bandwidth and 7.7 times the slew rate that of traditional counterpart with only 25% additional power consumption. [ABSTRACT FROM AUTHOR]

In this paper, a new 10T SRAM bit-cell working in the near-threshold region with differential read and write operations is proposed. The cell structure comprises six main body transistors having connections similar to commercial 6T SRAM cell to improve write performance and has a separate read buffer on each side of cell to improve read performance. Efficacy of the proposed bit-cell is tested in 20 nm tri-gated FinFET technology with the help of HSPICE simulations in near-V T and super-V T operating regions. Performance characteristics of the proposed bit-cell are compared with other recently reported 10T and 8T differential sensing bit-cells, along with the commercial 6T cell. The proposed bit-cell achieves 6.57%, 33.33% and 51.64% higher RSNM as compared to 10T P-P-N, 8T SRAM-NEW and 6T bit-cells, respectively, in near-V T operating region. The read delay, write delay and static power consumption of the proposed bit-cell are comparable with that of 6T bit-cell in both operating regions. The overall electrical quality of SRAM circuit with the proposed bit cell is enhanced up to 8.192, 1.13 and 2.39 times compared to that of the 10T P-P-N, 8T SRAM-NEW and 6T bit-cells, respectively, in near-V T operating region. The proposed bit-cell can operate with a 38.8%, 30% and 5.54% lower V DD as compared with 6T, 8T SRAM-NEW and 10T P-P-N bit-cells, respectively, under equal read data stability conditions. Influence of process variation on bit-cell stability is studied through 10,000 Monte Carlo simulations. The study shows that the proposed bit-cell meets the required six sigma value (6σ) for all operations even at V DD =0.5 V. Variations in the bit-cell performance metrics for temperature rise from −40 °C to 100 °C are also studied. [ABSTRACT FROM AUTHOR]

Recently, the large size data, power and real-time processing abilities are major issues in Digital Signal Processing/multimedia applications which require an adaptable architecture. The tool used for computing data decorrelation in the image processing applications refers Discrete Tchebichef Transform (DTT) which offers better performance than the DCT due to its bitstream coding capabilities. This paper proposes a novel model of Discrete Tchebichef Transform (DTT) architecture with Register Pre-allocation based Folded Architecture (RPFA) for image compression. Through the cross-connection of folded architecture, the number of register usage is reduced. A Partial Cross Split Vedic Multiplier (PCSVM) method is introduced in the proposed DTT architecture. This multiplier design involves the cross function of the Vedic multiplier with the split pattern of multiplication binary stream. The optimal design of DTT architecture yields a minimum amount of FlipFlop (FF) counts, a latency and power consumption. The proposed PCSVM achieves higher Peak Signal to Noise Ratio (PSNR), better Structural Similarity Index (SSIM), lower delay, area, power consumption, Power-Delay Product (PDP), Mean Square Error (MSE) than the existing multiplier architectures. The proposed RPF-DTT architecture achieves a significant reduction in the resource consumption than the exact and approximate DTT architectures. [ABSTRACT FROM AUTHOR]

This paper presents a simple implementation method of pipelined asynchronous circuits, suitable for commercial field programmable gate arrays (FPGAs). Contrary to other existing asynchronous design techniques, the presented method does not require the application of additional user actions such as constraining or building hard macros. As a design example, an architecture of the asynchronous PicoBlaze compatible microcontroller and 12-bit pipelined fast array multiplier have been considered. The developed synchronous and asynchronous versions of the microcontroller as well as fast array multiplier have been implemented and tested using Xilinx FPGAs, and then compared in terms of the area requirement, power consumption and performance. [ABSTRACT FROM AUTHOR]

Conventional data-aware structure SRAMs consume unnecessary dynamic power during the read phase due to the read-half-select issue. In this paper, a 9T-based read-half-select disturb-free SRAM architecture with the cross-point data-aware write strategy is proposed. Based on the proposed write-half-select and read-half-select disturb-free strategy, our 9T bitcell structure improves the read and write SNM by 2.5X and 2.4X compared to traditional bitcells. Furthermore, the proposed strategy and 9T bitcell structure can reduce the read power dissipation on bitline of the SRAM array by 5.14X compared with traditional SRAMs. Based on the proposed architecture, a 16Kb SRAM is fabricated in a 130 nm CMOS which is fully functional from 1.2 V down to 0.33 V. The minimal energy per cycle is 11.8pJ at 0.35 V. The power consumption at 0.33 V is 2.5 µW with 175 kHz. The proposed SRAM has 1.5X and 4.2X less total power and leakage power than other works. [ABSTRACT FROM AUTHOR]

In an orthogonal frequency division multiplexing (OFDM) based wireless systems, Fast Fourier Transform (FFT) is a critical block as it occupies large area and consumes more power. In this paper, we present an area-efficient and low power 16-bit word-width 64-point radix-2 2 and radix-2 3 pipelined FFT architectures for an OFDM-based IEEE 802.11a wireless LAN baseband. The designs are derived from radix-2 k algorithm and adopt a Single-Path Delay Feedback (SDF) architecture for hardware implementation. To eliminate the complex multipliers and read-only memory (ROM) which is used for internal storage of twiddle factor coefficients, the proposed 64-point FFT employs a Canonical Signed Digit (CSD) complex constant multiplier using adders, multiplexers and shifters. The complex constant multiplier (CCM) is modified using common sub-expression sharing block that reduces the area of the design. The proposed radix-2 2 and radix-2 3 pipelined FFT architectures are modeled and implemented using TSMC 180 nm CMOS technology with a supply voltage of 1.8 V. The implementation results show that the proposed architectures significantly reduces the hardware cost and power consumption in comparison to existing 64-point FFT architectures. [ABSTRACT FROM AUTHOR]

In this paper, we present a double-operating-mode adder which may be employed either in low-power (LP) or high-performance (HP) operating mode. The adder has a hybrid structure based on a c arry- l ookahead and c arry- p ropagate structures and hence is called CL-CPA. The selection between the two operating modes is performed through a mode selection bit during the operational period. The hybrid structure of the adder provides the feature of selecting the operating mode depending on the application deadlines and system available energy resources. The adder structure is realized by modifying the carry look-ahead tree (CLT) structure and then combining it with a carry propagate adder (CPA). During the LP mode, only the CPA structure is utilized while the CLT is deactivated through the power gating scheme. On the other hand, during the HP mode, the CLT structure is activated and the adder performs with its highest speed and power consumption using both CLT and CPA structures. The efficacy of the proposed hybrid adder is assessed by comparing its speed, power, energy, and area parameters with those of the other conventional adders obtained using HSPICE simulations for a 45-nm CMOS technology in a wide range of supply voltages. The results revel switching from the LP to HP operating mode leads to about 5.4X decrease, 2.5X increase, and 2.1X decrease in the delay, power, and energy of the 64-bit CL-CPA, respectively, averaged over the supply voltages. Also, the proposed hybrid adder provides flexibility on speed and power with an acceptable area usage for applications where both high speed and low power adders are required. [ABSTRACT FROM AUTHOR]

In this paper we propose a cross-layer accelerated self-healing (CLASH) system which “repairs” its wearout issues in a physical sense through accelerated and active recovery, by which wearout can be reversed while actively applying several accelerated self-healing techniques, such as high temperature and negative voltages. Different from previous solutions of coping with wearout issues (e.g. BTI) by “tolerating”, “slowing down” or “compensating”, which still leave the irreversible (permanent) wearout component unchecked, the proposed solution is able to fully avoid the irreversible wearout through periodic rejuvenation, and this is inspired by the explored frequency dependent behaviors of wearout and (accelerated and active) recovery based on measurements on FPGAs. We demonstrate a case where the chip can always be brought back to the fresh status by employing a pattern of 31-h regular operation (under room temperature and nominal voltage) followed by a 1-h accelerated self-healing (under high temperature and negative voltage). The proposed system integrates the notions of accelerated self-healing across multiple layers of the system stack. At the circuit level, a negative voltage generator and heating elements are designed and implemented; at the architecture level, the core can be allocated in a way such that the dark silicon or redundant resources can be healed by active elements; at the system level, right balance of stress and accelerated/active recovery can be employed by the system scheduler to fully mitigate the wearout; various wearout sensors act as the media between different layers. Overall, these techniques work together to guarantee that the whole system performs for more of the time at higher levels of performance and power efficiency by fully taking advantage of the extra opportunities enabled by the accelerated self-healing. [ABSTRACT FROM AUTHOR]

Simulation of power girds has become increasingly computationally expensive. In this paper, we propose a Model Order Reduction (MOR) method for power grids by extending the existing Aggregating based MOR (AMOR) method. In the proposed method, besides resistors and capacitors, current sources are also aggregated to improve MOR efficiency. Moreover, pre-partition and parallelization techniques are employed to decrease reduction time. Numerical results demonstrate that compared to original circuits, the scale of power grids is greatly reduced without much loss of accuracy. The reduced-order models are especially useful in the multiple simulations of different working modes or different environment corners. [ABSTRACT FROM AUTHOR]

In recent years, the major focus of VLSI design has shifted from high-speed to low-power consumption. While standard CMOS-based digital design provides substantial flexibility during pre-silicon design phases, the characteristics of the gates are set by fabrication variations and environmental conditions and cannot easily be changed at runtime. The recently proposed Dual Mode Logic (DML) family provides a novel approach to provide this capability by introducing two configurable operating modes, static and dynamic, that enable fine-grained control of the power-performance tradeoff of a logic path. However, the introduction of a new topology requires the development of both a design methodology and techniques for integration in a robust design automation flow. Standard synthesis tools do not support dynamic gates, and in particular, dual-characteristic gates. Therefore, until now, DML has been limited to small, custom-made blocks and components. In this paper, we present a novel approach for the integration of DML into standard electronic design automation tools, as part of the standard digital design flow. The development of this approach and the accompanying design methodology enables DML to be used in larger designs, such as state-of-the-art, high-speed and/or low-power SoCs. We demonstrate the employment of the proposed approach in order to benefit from DML properties, and reduce the power consumption, while simultaneously improving the operating frequency of a number of test designs. [ABSTRACT FROM AUTHOR]

In this paper, a noise transfer function (NTF) enhanced incremental sigma-delta (ΣΔ) modulator is presented. It employs a charge redistribution successive approximation register (SAR) analog-to-digital converter (ADC) in an error-feedback scheme to achieve an extra noise-shaping order. Using a multi-bit SAR quantizer not only improves the stability and power consumption but also facilitates the realization of both the adder situated in front of the quantizer and the whole error-feedback loop. As a design example, a multiplexed 2nd-order modulator based on the proposed architecture is simulated in TSMC 90 nm CMOS technology using Spectre with a 1 V single power supply. The simulation results show a signal-to-noise and distortion ratio (SNDR) of 85.3 dB within a signal bandwidth of 20 kHz (1 kHz/channel) at 5 MHz sampling frequency. The power consumption for each channel is 8.6 µW. [ABSTRACT FROM AUTHOR]

This paper presents a design for a mixed-signal pulse width modulator (MSPWM) integrated circuit that targets the digital control of high-frequency switched-mode DC–DC power supplies (SMPS). Previous designs consider digital pulse width modulators (DPWM) implementations that encounter important design issues, such as power consumption, non-linearity, layout dependency, trimming capability and temperature dependency. This work presents effective solutions, suitable for large-scale production of ICs, since it combines high-precision, high-linearity and temperature-independent standard analog circuits, which are commonly offered by the semiconductor industry, with the simplicity and reuse of digital PID compensation as input. The 8-bit prototype designed for a 0.18-μm CMOS process operates at switching frequency of 2 MHz, draws only 96.25 μA from a 1.8 V supply and takes 0.029 mm 2 , including the non-overlapping control logic of SMPS power devices. [ABSTRACT FROM AUTHOR]

This paper proposes new models of GPU energy consumption from the perspectives of hardware architects and graphics programmers by performing an architecture-independent analysis of the classical graphics rendering pipeline which is still in widespread use today. The detailed analysis includes graphics rendering workload, memory bandwidth and energy consumption . Although the models are derived from classical 3D pipeline, they are extensible to programmable pipelines. There are many factors that affect the performance and energy consumption of 3D graphics rendering, such as the number of textures, vertex sharing, level of details, and rendering algorithms. The proposed models are validated by our simulation study and used to guide our 3D graphics hardware design and 3D graphics programming in order to optimize performance and energy consumption of our GPU prototypes which have been successfully fabricated in SMIC 0.13 μm CMOS technology. [ABSTRACT FROM AUTHOR]

This paper presents a methodology to estimate the dissipation of energy in hardware, at any level of abstraction, with Powersim. Powersim is a C++ class library aimed to the calculation of energy dissipation of hardware described in SystemC. To this end C++ operators are monitored and a different energy model is used for each data type. Energy models are functions of operator inputs, constant parameters and variables, like supply voltage. The main advantage of this approach is that energy estimation does not require any change in the source code describing the hardware. As application examples, the computational complexity of a JPEG encoder, implemented in a FPGA, and a FIR filter, implemented in a microcontroller, are presented. [ABSTRACT FROM AUTHOR]

With ever increasing demand for lower power consumption, lower cost, and higher performance, designing analog circuits to meet design specifications has become an increasing challenging task, Analog circuit designers must, on one hand, have intimate knowledge about the underlining silicon process technology׳s capability to achieve the desired specifications. They must, on the other hand, understand the impact of tweaking circuits to satisfy a given specification on all circuit performance parameters. Analog designers have traditionally learned to tackle design problems with numerous circuit simulations using accurate circuit simulators such as SPICE, and have increasingly relied on trial-and-error approaches to reach a converging point. However, the increased complexity with each generation of silicon technology and high dimensionality of searching for solutions, even for some simple analog circuits, have made the trial-and-error approach extremely inefficient, causing long design cycles and often missed deadlines. Novel rapid and accurate circuit evaluation methods that are tightly integrated with circuit search and optimization methods are needed to aid design productivity. Furthermore, the current design environment with fully distributed licensing and supporting structures is cumbersome at best to allow efficient and up-to-date support for design engineers. With increasing support and licensing costs, fewer and fewer design centers can afford it. Cloud-based software as a service (SaaS) model provides new opportunities for CAD applications. It enables immediate software delivery and update to customers at very low cost. SaaS tools benefit from fast feedback and sharing channels between users and developers and run on hardware resources tailored and provided for them by the software vendor. On the downside, web-based tools are expected to perform in a very short turn-around schedule and be always responsive. This paper presents a list of innovations that come together to a new class of analog design tools: 1). Lookup table-based approach (LUT) to model complex transistor behavior provides both the necessary accuracy and speed essential for repeated circuit evaluations. 2). The proposed system architecture tight integrate the novel LUT approach with novel system level functions to allow further significantly better accuracy/speed tradeoff and faster design convergence with designer׳s intent. 3). Incorporating use inputs at key junctures of the design process allows the tool to better capture designer׳s intent and improve design convergence. 4). The combination of high accuracy and faster evaluation time make it possible to incorporate SaaS features, such as short solution space navigation steps and crowdsourcing, into the tool. This allows sharing of server-side resources between many users. Instead of fully automating a signoff circuit optimization process, the proposed tool provides effective aid to analog circuit designers with a dash-board control of many important circuit parameters with several orders faster in computation time than SPICE simulations. [ABSTRACT FROM AUTHOR]