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International audience; Forward AC stress and relaxation have been performed on GaN-on-Si Schottky diodes to study the shift of diode characteristics such as threshold voltage. Influence of frequency and length of first anode field plate are studied. PBTI measurement performed on HEMTs with gate similar to the first anode field plate rules out the degradation of the dielectric under the anode field plate and tends to prove that Schottky contact itself could be the cause of forward stress degradation.

A critical process aspect of the bipolar device is the oxide isolation between the emitter and the extrinsic base. Indeed, it is a well known fact that the emitter–base junction degradation is mainly due to interface states generation underneath oxide spacer. This study demonstrates the large impact of the inside spacer process in fully-self aligned high speed HBT on its reliability. Several types of electrical stress have been investigated and the stress-induced degradation compared for nitride and a-Si (amorphous silicon) spacers. Aging results coupled with noise measurements and TCAD simulations allowed to explain the different observed behaviors, finally concluding on the significantly higher reliability performances of devices processed with a-Si spacers.

Positive voltage instabilities are studied for Nmos transistors with hafnium-based high-κ gate stacks. Using an optimized dedicated fast measurement setup, dynamic transient measurements of drain current are performed over more than ten decades of time. The two main phenomena involved, a reversible one known as hysteresis and a nonreversible one known as PBTI are clearly experimentally separated and studied in detail. A physical model is presented, explaining the dynamic behaviour and leading to precise traps physical characteristics and profiles inside the HfO2 layer. PBTI defects in HfO2 are shown to be of a different nature than hysteresis traps. A turn-around effect is evidenced for PBTI above which physical mechanisms seem to change; it has important implications on lifetime determination methodology. Finally, HfSiON experiments are presented for both hysteresis and PBTI and they show that this material is much less critical than HfO2.

In this work we report an experimental observation of the current dependence on the defect generation probability driving to breakdown. We propose the MVHR model (multi-vibrational hydrogen release) based on the multi-vibrational excitation of the Si–H bond stretching mode. By this way we explain the power-law dependence of charge and time to breakdown and highlight its limit on PMOS inversion.

Tantalum oxide (Ta 2 O 5 ) is widely used for MIM (Metal-Insulator-Metal) capacitor owing of its high dielectric constant. This work examines current–voltage and capacitance–voltage characteristics in the 5 K–300 K temperature range. Working at low temperature was chosen in order to freeze trapping mechanisms of the MIM capacitor. The curvature of C – V characteristics radically changes from 5 K to 300 K. The capacitance variation under voltage at 50 K and below can be investigated using the Langevin theory. From this model the permanent dipole moment and the number of dipoles have been extracted. From Poole–Frenkel identification curves, activation energy around 0.20 eV and a dielectric constant of 26 were found for positive polarisation. However, conduction mechanisms cannot be reduced to strick Poole–Frenkel modelling.

In this work we present an experimental evidence of a current dependence of the defect generation probability driving to breakdown. Based on this observation we explain the power law dependence of the charge and the time to breakdown and show its limit on pmos inversion.

In this paper, n-channel MOSFET’s with oxides 1.2, 1.5 and 1.8 nm thick are studied. In such devices the trap assisted tunnelling (TAT) current required to fit the gate current vs. gate voltage, I g ( V g ), characteristics is thought to flow through Si–SiO 2 interface traps. After stress, it becomes a stress induced leakage current (SILC) which should allow to obtain interface trap density variations with stress. The TAT mechanism is discussed. Then, the Si–SiO 2 interface trap densities extracted using the SILC and charge pumping (CP) are compared. Much larger trap creation rates are viewed by the SILC with regard to CP, questioning the occurrence of the SILC through interface traps. To answer this question the interaction between SILC and CP measurements is investigated.

Using constant voltage stresses carried out in the inversion regime on nMOS transistors, poly-Si gated to poly-SiGe gated devices are compared. It is shown that charge (and time) to breakdown is significantly increased by the use of silicon–germanium alloy as a gate material. The result is discussed from the anode hole injection and the hydrogen release mechanisms point of view by estimating the expected modifications of each defect generation probability. It is concluded that even in the absence of (minority/majority) hole carrier density at the anode/oxide interface, the hole distribution is likely to impact the breakdown mechanisms.

A brief overview of recent issues concerning the low frequency (LF) noise in modern CMOS devices is given. The approaches such as the carrier number and the Hooge mobility fluctuations used for the analysis of the noise sources are presented and illustrated through experimental results obtained on advanced CMOS generations. The use of the LF noise measurements as a characterization tool of large area MOS devices is also discussed. The main physical features of random telegraph signals (RTSs) observed in small area MOS transistors are reviewed. The impact of scaling on the LF noise and RTS fluctuations in CMOS silicon devices is also addressed. Experimental results obtained on 0.18 μm CMOS technologies are used to predicting the trends for the noise figure of foregoing CMOS technologies e.g. 0.1 μm and beyond. The formulation of the thermal noise underlying the LF fluctuations in MOSFETs is recalled for completeness.

This work presents the low frequency noise and the electric performances in terms of output/transfer characteristics, threshold voltage, and short channel effect in both NMOS and PMOS transistors for 0.1 μm technologies. For the last one there are two architectures based either on a surface mode of operation (surface channel) or on a buried one (buried channel) featuring either a P+ or a N+ polysilicon gate material. The impact of the channel length on the noise characteristics as well as on the output/transfer characteristics is studied. We find that the 1/f noise can be interpreted in terms of carrier number fluctuations for both N and P channel MOSFETs for surface and buried mode of operation. The oxide trap density Nt is therefore evaluated, demonstrating an overall good oxide quality.

In this paper, a comprehensive description of the ultrathin oxide failure evolution is presented. For sub-25 A, Hard BD is no longer hard. A complete description of the novel failure manifestation (progressive breakdown) is done. Associated wear-out is modelled and a physical mechanism is proposed. Finally, the relevance of the failure definition is discussed. It is a crucial point, to adopt a rigorous methodology for reliability prediction. It is concluded that, in the case of progressive breakdown, noise occurrence must be considered as the relevant time to failure.

This paper presents a review of models for direct tunnelling with a view to identifying suitable models for inclusion in a circuit simulator. For thin oxides, the critical quantities required for the derivation of tunnel current are the transparency of the barrier, the oxide field and the supply of carriers for tunnelling. This paper reviews different approaches to the incorporation of these quantities in analytical models. A new model for direct tunnelling, which includes quantum effects in a format suitable for circuit simulation, is outlined. Recent developments in MOSFET models, which include gate current, are briefly discussed.

In this study, body effect influence on oxide degradation is analyzed. It is found that the negative bias polarization on the n-well of a p-channel MOS transistor may induce a significant reduction of the oxide lifetime as well as an increase of stress-induced leakage current (SILC). Such a result is demonstrated to confirm the key role of hot holes on SILC and breakdown phenomena. Moreover, even if the hot hole generated at the anode are probably at the origin of SILC and can be interpreted as a catalyst of breakdown, it is undoubtedly shown that both phenomena are not directly correlated: SILC at breakdown can not be ascribed to a critical density of defect at failure.

In this paper, low-frequency noise (LFN) in N- and P-channel dynamic-threshold (DT) MOSFETs on Unibond substrate (SOI) is thoroughly investigated and, especially, an improved formulation of classical McWhorter’s noise model is proposed. In order to confirm our approach, an experimental comparison between body tied and DTMOS on SOI substrate has been achieved in terms of LFN behaviour. Furthermore, two different types of DTMOS transistors have been used: with and without current limiter. The LFN in DTMOS is analysed in ohmic and saturation regimes and the impact of the use of a current limiter (clamping transistor) is thoroughly analysed. An explanation based on floating body effect inducing excess noise is also proposed.

We show that low frequency noise (LFN) in SiGe-base heterojunction bipolar transistors and SiGe-channel pMOSFETs may be made significantly lower than that in their all-Si counterparts and indicate how this can be done. Optimization of LFN in SiGe channel pMOSFETs follows from a calculation involving a novel analytical model, which accounts for both static and LFN characteristics of SiGe-channel devices.

In this study, wet and dry oxidation processes for 3.5 nm ultrathin dielectrics are compared in terms of oxide and device reliability. It is demonstrated that a wet oxidation enables to strongly improve the oxide lifetime. On the contrary, the device reliability has been found to be slightly affected by the process choice. Finally, these results associated with charge pumping and stress induced leakage current measurements indicate that the bulk oxide, more than the Si/SiO2 interface, is affected by the growth process ambience (wet or dry oxidation).

This paper reports the Capacitance–Voltage (C–V) characterization of gate oxide in the 20 A thickness range, dealing especially with quantum and polysilicon effects. In the first part, the basis of Poisson–Schrodinger modeling is summarized. The extraction procedure of doping level, flat band voltage, threshold voltage, and oxide thickness is presented. A simple method to extract the polysilicon doping level and to correct for polysilicon effect on C(V) curves is proposed. These parameter extraction procedures are illustrated by experimental data obtained on both NMOS and PMOS transistors.

Stress Induced Leakage Current (SILC) has been recognized as a topic of concern in flash memory reliability. It is a veritable failure mechanism, occurring long before oxide breakdown and, hence, limiting oxide lifetime. The physical origin and mechanisms of SILC have not yet been clearly understood and several open points to discussion remain. In this work the electrical characteristics of SILC have been studied and an empirical reliability model for ultra-thin gate oxide has been proposed. Moreover, ionizing radiation effects in leakage current generation have been analyzed and compared to electrical SILC.

A study of the electric field and temperature dependence of the breakdown and quasi-breakdown phenomena is presented for 3.5 nm ultra-thin SiO2 gate oxides. Using a methodology based on the competing mecanism concept between breakdown and quasi-breakdown processes, quasi-breakdown activation energy as well as acceleration factor are determined. It is demonstrated on these 3.5nm gate oxides that the quasi-breakdown temperature activation energy is almost temperature independent on the contrary to the breakdown one. Moreover, it has been shown that the temperature dependence of the breakdown acceleration factor and the electric field dependence of the temperature activation energy cannot be explained by a pure “E” and “1E” models, but can be interpreted by the “E” model if at least two types of molecular defect states are considered.

A thorough characterization of stress-induced leakage currents (SILCs) for a IOnm-thick oxide, by using the floating-gate technique, is presented. The obtained current is modeled by a volume-limited conduction mechanism. Experimental and model suggest that SILC conduction mechanism is the same in thin as well as in thick oxides.

A new model for the oxide thickness dependence of the SILC generation has been proposed on the basis of defects created by anode hole injection. This model which has been validated on oxides with thickness down to ≈3nm, allows the explanation of the bell-shaped behavior of the SILC variation with oxide thickness and predicts a strong reduction of the SILC intensity for ultra thin oxides operated in the direct tunneling regime.

The understanding of the transport mechanism at the origin of the leakage currents in thin oxides is crucial to make reliable data retention predictions. In this work we demonstrate that elastic resonant trap assisted tunnelling well describes the SILC (Stress Induced Leakage Current) for oxide thicknesses between 4 and 7.5 nm when an appropriate trap profile is used. Moreover our approach gives a qualitative description of the temperature dependence of the SILC, exhibiting similar field dependent activation energy. Finally we showed that the SILC measured in the substrate current could also be modeled using a trap assisted tunnelling model, demonstrating that this approach is consistent with the main experimental characteristics of the SILC.

This paper describes the various methods used for the assessment of the breakdown and wear out properties of thin oxides currently employed in CMOS and EEPROM technologies. Standard procedures for breakdown and wear out testing are given in conjunction with the associated test structures required for their accomplishment.

Stress-induced leakage current (SILC) has been recognized as a topic of concern in flash memory reliability. It is a reliable failure mechanism, occurring long before oxide breakdown and, hence, limiting oxide lifetime [1] . The physical origin and mechanisms of SILC have not yet been clearly understood and several points open to discussion remain. In this work the role of oxide hole fluence in producing the SILC is discussed. An universal power law of SILC generation kinetics is proposed versus the hole fluence throughout the oxide. The experimental results are theoretically validated by modeling the measured quantum-yield by the contributions of both anode hole injection and electron valence band injection mechanisms.

The annealing properties of the stress induced leakage current (SILC) for 55 and 65 Athick oxides are investigated. It is demonstrated that the SILC is a fully reversible degradation process and that its generation kinetics are nearly unchanged after successive stressing/annealing cycles. The activation energy and diffusion coefficient of the annealing process has been extracted and shown to be independent of oxide thickness. Moreover the annealing kinetics are quantitatively simulated using a drift-diffusion model with the experimentally extracted parameters.

Interpoly stacked-dielectric conduction mechanisms are investigated. Extensive Si3N4 and SiO2 single-layer transport analysis leads to a clear multi-layer dielectric understanding. An improved carrier-separation model is proposed for a 35 A-thick SiO2 and applied to ONO results. NO electrical behavior is satisfactorily modelled under both gate polarities.

This paper focuses on the stress-induced leakage current (SILC) phenomenon in 5 nm thin oxides. The statistical investigation of SILC is emphasized and it is shown that this phenomenon can be directly linked to the intrinsic properties of the SiO 2 material. Moreover, it will be pointed out that the experimentally validated SILC build-up empirical model presents some limitations when using this model for extrapolation purposes at very low injected charges and/or low current/voltage levels.

A thorough SILC characterization by using MOSFET induced substrate current is for the first time developed. Based on obtained results, it is argued that a model consisting in a electrode-limited conduction, as the Fowler-Nordheim emission, cannot explains thin-oxide SILC results, while a bulk-limited trap-assisted transport well fits experimental data.

The reversibility of charge buildup and SILC generation in thin oxides subjected to successive stress/anneal cycles is investigated. It is demonstrated that in thin oxides both electron trapping and SILC are nearly fully reversible degradation processes having a generation kinetics almost unchanged after several stressing/annealing cycles. The annealing kinetics of the SILC is likely associated to the out diffusion of charged defects (possibly trapped holes or H+) whose characteristics (diffusivity, activation energy) are independent of the oxide thickness. Moreover correlation between electron trapping and SILC generation has been studied.

We propose in this paper a new hot carrier degradation law for a reliable MOSFET lifetime prediction. We show that the proposed exponential function can describe all kind of curve concavity (saturating or non-saturating shapes) and can fit very well with the experimental data for the whole duration of the stress. Finally, it gives a more accurate lifetime value as compared to previous modelings because it accounts for the concavity of the saturating degradation law.

Investigation on the stress induced leakage current shows that the SILC degradation rate follows a pure power law with the injection dose which is almost independent of gate bias polarity and stress current intensity. Moreover, it has also been found that the SILC is invariant with the device area, substrate type but could depend on the gate material in the case of P+ polysilicon due to boron-induced defects in the bulk of the oxide.

Hot carrier degradation of 1 f noise characteristics of bipolar junction transistors is found to be substantially reduced by arsenic surface compensation of the base region, in agreement with former reports on the improvement in reliability of such devices, inferred from their static characteristics studies.

The characterization of LF noise and RTS fluctuations in 0.18μm CMOS devices is presented. It is found that the 1 f noise results from carrier number fluctuations for both N and P MOS devices. The slow oxide trap density deduced from the noise data lies around 1017/eV/cm3 in agreement with state-of-the-art gate oxides. Drain current RTS amplitude as large as 5–10% have been observed, being somewhat larger than for 0.35μm CMOS technology but comparable to those obtained in 0.25μm CMOS devices.

A new method for the extraction of the oxide charge density and distribution centroid based on the exploitation of the Fowler plot derivative characteristics is proposed. The comparison with the DiMaria method confirms the overall consistency of the new approach. The presence of negative charge within the oxide is shown to be responsible for an increase in the apparent Fowler barrier height after uniform gate stress.

A study of the electric field dependence of the TDDB activation energy is presented for 12 nm down to 4.7 nm thin oxides. It is shown that the TDDB activation energy depends linearly on the stress electric field and that this behavior depends strongly on the oxide thickness. Moreover, a relationship between the TDDB activation energy attenuation per WV/cm and the oxide thickness has been found. As will be demonstrated, these results are of great importance for the rigorous estimation of the oxide lifetime of both present and future technologies.

The reliability issues of tunnel MOS capacitors after Fowler-Nordheim stress are deeply investigated. The techniques currently available for estimating the degradation of the devices are reviewed. Several tunnel oxide technologies are compared with respect to the reliability performance. Besides, the impact of the tunnel oxide technology on the reliability performance of FLOTOX EEPROM cells is discussed extensively. Finally, novel quantitative physical models which correlate the quality of the tunnel oxide technology with the reliability aspects of FLOTOX EEPROM cells are presented.

The reliability issues of Offset Drain Transistors (ODT's) after different modes of static electrical stress (high voltage uniform gate stress, high voltage drain stress and hot carrier stress) are presented. Besides, the evolution of the macroscopic electrical parameters of these devices after high voltage uniform gate stress, has been attributed quantitatively to the evolution of the bulk gate oxide trapping characteristics and the variation of the Si/SiO 2 interface state charge. Furthermore, qualification of these devices for application in non-volatile memory arrays as bit select transistor has been conducted.