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Abstract: Focused ion beam (FIB) and nano-probing were applied for failure analysis of three-dimensional stacked circuits with copper through-silicon-vias between the stacked chips. The failure analysis was done after high temperature storage and thermal cycling tests. Passive voltage contrast in FIB allowed to pinpoint the open sites. FIB cross-sections showed the presence of opens at the bottom of the copper vias. The failure cause was suspected to be an interlayer particle, which was confirmed by optical profilometry. Nano-probing was used on another sample to pinpoint the failure location through the measurement of the local resistance within the daisy chains. The failure was traced out to be related with surface contamination. [Copyright &y& Elsevier]

Polycrystalline silicon (pc-Si) thin-films with a grain size in the range of 0.1–100 μm grown on top of inexpensive substrates are economical materials for semiconductor devices such as transistors and solar cells and attract much attention nowadays. For pc-Si, grain size enlargement is thought to be an important parameter to improve material quality and therefore device performance. Aluminum-induced crystallization (AIC) of amorphous Si in combination with epitaxial growth allows achieving large-grained pc-Si layers on nonsilicon substrates. In this work, we made pc-Si layers with variable grain sizes by changing the crystallization temperature of the AIC process in order to see if larger grains indeed result in better solar cells. Solar cells based on these layers show a performance independent of the grain size. Defect etching and electron beam induced current (EBIC) measurements showed the presence of a high density of electrically active intragrain defects. We therefore consider them as the reason for the grain size independent device performance. Besides dislocations and stacking faults, also Σ3 boundaries were electrically active as shown by combining electron backscattered diffraction with EBIC measurements. The electrical activity of the defects is probably triggered by impurity decoration. Plasma hydrogenation changed the electrical behavior of the defects, as seen by photoluminescence, but the defects were not completely passivated as shown by EBIC measurements. In order to reveal the origin of the defects, cross section transmission electron microscopy measurements were done showing that the intragrain defects are already present in the AIC seed layer and get copied into the epitaxial layer during epitaxial growth. The same types of intragrain defects were found in layers made on different substrates (alumina ceramic, glass ceramic, and oxidized silicon wafer) from which we conclude that intragrain defects are not related to the relatively rough alumina ceramic substrates often used in combination with high temperature epitaxy. Further improvement of the material quality, and hence device performance, is therefore not simply achieved by increasing the grain size, but the intragrain quality of the material also needs to be taken into account. For pc-Si layers based on AIC and epitaxial growth, the seed layer has a crucial impact on the intragrain defect formation. [ABSTRACT FROM AUTHOR]

In this work, we present a systematic study of the effect of the stoichiometry of BaTiO3 (BTO) films grown on the Ge(001) substrate by molecular-beam-epitaxy using different characterization methods relying on beam diffraction, including reflection high-energy electron diffraction (RHEED), X-ray diffraction (XRD), and selected-area electron diffraction in transmission electron microscopy. Surprisingly, over a wide range of [Ba]/[Ti] ratios, as measured by the Rutherford backscattering spectrometry, all the BTO layers exhibit the same epitaxial relationship h100iBTO(001)// 〈110〉Ge(001) with the substrate, describing a 45° lattice rotation of the BTO lattice with respect to the Ge lattice. However, varying the [Ba]/[Ti] ratio does change the diffraction behavior. From RHEED patterns, we can derive that excessive [Ba] and [Ti] generate twinning planes and a rougher surface in the non-stoichiometric BTO layers. XRD allows us to follow the evolution of the lattice constants as a function of the [Ba]/[Ti] ratio, providing an option for tuning the tetragonality of the BTO layer. In addition, we found that the intensity ratio of the 3 lowest-order Bragg peaks I(001)/ I(002), I(101)/I(002), and I(111)/I(002) derived from ω-2θ scans characteristically depend on the BTO stoichiometry. To explain the relation between observed diffraction patterns and the stoichiometry of the BTO films, we propose a model based on diffraction theory explaining how excess [Ba] or [Ti] in the layer influences the diffraction response. [ABSTRACT FROM AUTHOR]

Abstract: We propose an empirical law correlating the average number of walls and the average diameter in a population of multi-wall carbon nanotubes grown by catalytic chemical vapor deposition. The relationship and its dispersion are derived from the statistical analysis of a database of TEM images of nanotubes collected from more than 60 publications in literature and from our group in the last years. Considering the nanotubes were grown from independent sources in a variety of conditions and tools, it has general validity. The relationship may find applicability in a wide range of fields as it provides a simple model to quickly estimate the number of walls most likely present in a population of nanotubes from only the measure of their average diameter. [Copyright &y& Elsevier]

The tunneling current through an atomic force microscopy (AFM) tip is used to evaluate the effective electrical contact area, which exists between tip and sample in contact-AFM electrical measurements. A simple procedure for the evaluation of the effective electrical contact area is described using conductive atomic force microscopy (C-AFM) in combination with a thin dielectric. We characterize the electrical contact area for coated metal and doped-diamond tips operated at low force (<200 nN) in contact mode. In both cases, we observe that only a small fraction (<10 nm2) of the physical contact (~100 nm2) is effectively contributing to the transport phenomena. Assuming this reduced area is confined to the central area of the physical contact, these results explain the sub-10 nm electrical resolution observed in C-AFM measurements. [ABSTRACT FROM AUTHOR]

Band-to-band tunneling parameters of strained indirect bandgap materials are not well-known, hampering the reliability of performance predictions of tunneling devices based on these materials. The nonlocal band-to-band tunneling model for compressively strained SiGe is calibrated based on a comparison of strained SiGe p-i-n tunneling diode measurements and doping-profile-based diode simulations. Dopant and Ge profiles of the diodes are determined by secondary ion mass spectrometry and capacitance-voltage measurements. Theoretical parameters of the band-to-band tunneling model are calculated based on strain-dependent properties such as bandgap, phonon energy, deformation-potential-based electron-phonon coupling, and hole effective masses of strained SiGe. The latter is determined with a 6-band k.p model. The calibration indicates an underestimation of the theoretical electron-phonon coupling with nearly an order of magnitude. Prospects of compressively strained SiGe tunneling transistors are made by simulations with the calibrated model. [ABSTRACT FROM AUTHOR]

Following an extensive investigation of various monolayer transition metal dichalcogenides (MX2), research interest has expanded to include multilayer systems. In bilayer MX2, the stacking order strongly impacts the local band structure as it dictates the local confinement and symmetry. Determination of stacking order in multilayer MX2 domains usually relies on prior knowledge of in-plane orientations of constituent layers. This is only feasible in case of growth resulting in well-defined triangular domains and not useful in-case of closed layers with hexagonal or irregularly shaped islands. Stacking order can be discerned in the reciprocal space by measuring changes in diffraction peak intensities. Advances in detector technology allow fast acquisition of high-quality four-dimensional datasets which can later be processed to extract useful information such as thickness, orientation, twist and strain. Here, we use 4D scanning transmission electron microscopy combined with multislice diffraction simulations to unravel stacking order in epitaxially grown bilayer MoS2. Machine learning based data segmentation is employed to obtain useful statistics on grain orientation of monolayer and stacking in bilayer MoS2. [ABSTRACT FROM AUTHOR]

We report on the performance of the quantum confined Stark effect (QCSE) in ultra-thin (~350 nm) Ge/SiGe quantum well stacks grown on Si. We demonstrate an absorption contrast $\Delta \alpha /\alpha $ of 2.1 at 1 Vpp swing in QCSE stacks grown on ultra-thin (100 nm) strain relaxed GeSi buffer layers on 300 mm Si wafers. Such ultra-thin QCSE stacks will enable future integration of highly efficient QCSE electro-absorption modulators with low optical coupling loss to passive Si waveguides in a sub-micron silicon photonics platform. [ABSTRACT FROM AUTHOR]

Atomic layer deposition (ALD) is used in applications where inorganic material layers with uniform thickness down to the nanometer range are required. For such thicknesses, the growth mode, defining how the material is arranged on the surface during the growth, is of critical importance. In this work, the growth mode of the zirconium tetrachloride/water and the trimethyl aluminum/water ALD process on hydrogen-terminated silicon was investigated by combining information on the total amount of material deposited with information on the surface fraction of the material. The total amount of material deposited was measured by Rutherford backscattering, x-ray fluorescence, and inductively coupled plasma–optical emission spectroscopy, and the surface fractions by low-energy ion scattering. Growth mode modeling was made assuming two-dimensional growth or random deposition (RD), with a “shower model” of RD recently developed for ALD. Experimental surface fractions of the ALD-grown zirconium oxide and aluminum oxide films were lower than the surface fractions calculated assuming RD, suggesting the occurrence of island growth. Island growth was confirmed with transmission electron microscopy (TEM) measurements, from which the island size and number of islands per unit surface area could also be estimated. The conclusion of island growth for the aluminum oxide deposition on hydrogen-terminated silicon contradicts earlier observations. In this work, physical aluminum oxide islands were observed in TEM after 15 ALD reaction cycles. Earlier, thicker aluminum oxide layers have been analyzed, where islands have not been observed because they have already coalesced to form a continuous film. The unreactivity of hydrogen-terminated silicon surface towards the ALD reactants, except for reactive defect areas, is proposed as the origin of island growth. Consequently, island growth can be regarded as “undesired surface-selective ALD.” [ABSTRACT FROM AUTHOR]

Abstract In the manufacturing of multi-Vt FinFET transistors, the gate material deposited in the nano-spaces left by the removed dummy gate must be etched back in mask-defined wafer areas. Etch conformality is a necessary condition for the control of under-etch at the boundary between areas defined by masking. We studied the feasibility of TiN etching by APM (ammonia peroxide mixture, also known as SC1) in nano-confined volumes representative of FinFET transistors of the 7 nm node and below, namely nanotrenches with 1-D confinement and nanoholes with 2-D confinement. TiN etching was characterized for rate and conformality using different electron microscopy techniques. Etching in closed nanotrenches was conformal, starting and progressing all along the 2-D seam, with a rate that was 38% higher compared to a planar film. Etching in closed nanoholes proved also to be conformal and faster than planar films, but with a delay to open the 1-D seam that seemed to depend strongly on small variations in the hole diameter. However, holes between the fins at the bottom of the removed dummy gate, are not circular and do present 2-D seams that should lend themselves for an easier start of conformal etching as compared to the circular nanoholes used in this study. Finally, to explain the higher etch rate observed in nano-confined features, concentrations of ions in nanoholes were calculated taking the overlap of electrostatic double layers (EDL) into account. With negatively charged TiN walls, as measured by streaming potential on planar films, ammonium was the dominant ion in nanoholes. As no chemical reaction proposed in the literature for TiN etching matched with this finding, we proposed that the formation of ammine complexes, dissolving the formed Ti oxide, was the rate-determining step. Graphical abstract Unlabelled Image Highlights • Etching of TiN in closed nanotrenches was conformal and 38% faster compared to planar films. • Etching in closed nanoholes was also conformal and faster compared to planar films, but with some delay to open the seam. • Ti-ammine complex formation suggested as the rate determining reaction in sub-10-nm features to satisfy EDL overlap model. [ABSTRACT FROM AUTHOR]

We report the electrical properties of 60° dislocations originating from the +1.2% lattice mismatch between an unintentionally doped, 315 nm thick Ge0.922Sn0.078 layer (58% relaxed) and the underlying Ge substrate, using deep level transient spectroscopy. The 60° dislocations are found to be split into Shockley partials, binding a stacking fault. The dislocations exhibit a band-like distribution of electronic states in the bandgap, with the highest occupied defect state at ∼EV + 0.15 eV, indicating no interaction with point defects in the dislocation's strain field. A small capture cross-section of 1.5 × 10−19 cm2 with a capture barrier of 60 meV is observed, indicating a donor-like nature of the defect-states. Thus, these dislocation-states are not the source of unintentional p-type doping in the Ge0.922Sn0.078 layer. Importantly, we show that the resolved 60° dislocation-states act as a source of leakage current by thermally generating minority electrons via the Shockley-Read-Hall mechanism. [ABSTRACT FROM AUTHOR]

Several applications of two-dimensional (2D) semiconducting transition metal dichalcogenides (TMDs) in nanoelectronic devices require the deposition of ultrathin pinhole free high-κ dielectric films on 2D TMDs. However, deposition of nm-thin high-κ dielectric films on 2D TMDs remains challenging due to the inert TMD surface. Here, we demonstrate that the surface of a synthetic polycrystalline 2D MoS2 film is functionalized with SiO2 to enable the atomic layer deposition (ALD) of thin and continuous Al2O3 and HfO2 layers. The origins of nucleation, the growth mode, and layer coalescence process have been investigated by complementary physical characterization techniques, which can determine the chemical bonds, absolute amount, and surface coverage of the deposited material. SiO2 is prepared by oxidizing physical vapor deposited Si in air. The surface hydrophilicity of MoS2 significantly increases after SiO2functionalization owing to the presence of surface hydroxyl groups. SiO2 layers with a Si content of only 1.5 x 1015 atoms/cm² enable the deposition of continuous 2 nm thin Al2O3 and HfO2 layers on MoS2 at 300 °C. This fast layer closure can be achieved despite the sub-nm thickness and discontinuity of the SiO2 nucleation layer. On the basis of the experimental results, we propose a nucleation mechanism that explains this fast layer closure. Nucleation of Al2O3 and HfO2 occurs on the SiO2 islands, and fast layer closure is achieved by the lateral growth starting from the many nm-spaced SiO2 islands. Finally, the dielectric properties of Al2O3 on the functionalized MoS2 are confirmed in a top-gated capacitor that shows a leakage current of 3.8 x 10-6 A/cm² at a 3.4 nm equivalent oxide thickness. To conclude, fast nucleation and layer closure in ALD can be achieved even for a sub-nm thin, discontinuous nucleation layer. We propose that this insight can also be applied to other ALD processes, materials, or applications where thin and fully continuous layers are required. [ABSTRACT FROM AUTHOR]

The process characteristics, the surface chemistry, and the resulting film properties of Ru deposited by atomic layer deposition from (ethylbenzyl)(1-ethyl-1,4-cyclohexadienyl)Ru(0) (EBECHRu) and O2 are discussed. The surface chemistry was characterized by both combustion reactions as well as EBECHRu surface reactions by ligand release. The process behavior on TiN starting surfaces at 325 °C was strongly influenced by Ti(O,N)x segregation on the growing Ru surface with consequences for both the growth per cycle as well as the film properties. For optimized process conditions, the films showed high purity with low C and O concentrations of the order of 1020 at./cm3. Higher deposition temperature led to strong (001) fiber texture of the films on SiO2 starting surfaces. Annealing in forming gas improved the crystallinity and led to resistivity values as low as 11 μΩcm for Ru films with a thickness of 10 nm. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) transition metal dichalcogenides are potential low dissipative semiconductor materials for nanoelectronic devices. Such applications require the deposition of these materials in their crystalline form and with controlled number of monolayers on large area substrates, preferably using deposition temperatures compatible with temperature sensitive structures. This paper presents a low temperature plasma-enhanced atomic layer deposition (PEALD) process for 2D WS2 based on a ternary reaction cycle consisting of consecutive WF6, H2 plasma, and H2S reactions. Strongly textured, nanocrystalline WS2 is grown at 300 °C. The composition and crystallinity of these layers depends on the PEALD process conditions, as understood by a model for the redox chemistry of this process. The H2 plasma is essential for the deposition of WS2 as it enables the reduction of -W6+Fx surface species. Nevertheless, the impact of subsurface reduction reactions needs to be minimized to obtain WS2 with well-controlled composition (S/W ratio of 2). [ABSTRACT FROM AUTHOR]

The epitaxial growth of Si layers on Si substrates in the presence of O atoms is generally considered a challenge, as O atoms degrade the epitaxial quality by generating defects. Here, we investigate the growth mechanisms for Si epitaxy on O atomic layers (ALs) with different O-contents and structures. O ALs are deposited by ozone (O 3 ) or oxygen (O 2 ) exposure on H-terminated Si at 50 °C and 300 °C respectively. Epitaxial Si is deposited by chemical vapor deposition using silane (SiH 4 ) at 500 °C. After O 3 exposure, the O atoms are uniformly distributed in Si-Si dimer/back bonds. This O layer still allows epitaxial seeding of Si. The epitaxial quality is enhanced by lowering the surface distortions due to O atoms and by decreasing the arrival rate of SiH 4 reactants, allowing more time for surface diffusion. After O 2 exposure, the O atoms are present in the form of SiO x clusters. Regions of hydrogen-terminated Si remain present between the SiO x clusters. The epitaxial seeding of Si in these structures is realized on H-Si regions, and an epitaxial layer grows by a lateral overgrowth mechanism. A breakdown in the epitaxial ordering occurs at a critical Si thickness, presumably by accumulation of surface roughness. [ABSTRACT FROM AUTHOR]

Filamentary-based oxide resistive memory is considered as a disruptive technology for nonvolatile data storage and reconfigurable logic. Currently accepted models explain the resistive switching in these devices through the presence/absence of a conductive filament (CF) that is described as a reversible nanosized valence-change in an oxide material. During device operation, the CF cycles billion of times at subnanosecond speed, using few tens of microamperes as operating current and thus determines the whole device's performance. Despite its importance, the CF observation is hampered by the small filament size and its minimal compositional difference with the surrounding material. Here we show an experimental solution to this problem and provide the three-dimensional (3D) characterization of the CF in a scaled device. For this purpose we have recently developed a tomography technique which combines the high spatial resolution of scanning probe microscopy with subnanometer precision in material removal, leading to a true 3D-probing metrology concept. We locate and characterize in three-dimensions the nanometric volume of the conductive filament in state-of-the-art bipolar oxide-based devices. Our measurements demonstrate that the switching occurs through the formation of a single conductive filament. The filaments exhibit sizes below 10 nm and present a constriction near the oxygen-inert electrode. Finally, different atomic-size contacts are observed as a function of the programming current, providing evidence for the filament's nature as a defects modulated quantum contact. [ABSTRACT FROM AUTHOR]

Incorporation of source–drain stressors (S/D) for FinFETs to boost the channel mobility is a promising scaling approach. Typically SiGe:B S/D stressors are used for p FinFETs and Si:C:P S/D stressors for n FinFETs. The deposition of such Si:C:P S/D stressors requires a low thermal budget to freeze the C in substitutional sites and also to avoid problems associated with surface reflow of Si fins. In this work, we report the material properties of Si:C and Si:C:P epitaxial layers grown by chemical vapor deposition, in terms of their defectivity and C incorporation as a function of different process conditions. The undoped Si:C layers were found to be defect free for total C contents below 1%. Above this concentration defects were incorporated and the defect density increased with increasing C content. Abrupt epitaxial breakdown occurred beyond a total C content of 2.3% resulting in amorphous layers. P doping of Si:C layers brought down the resistivity and also thicker Si:C:P films underwent epitaxial breakdown. Additionally, the use of nitrogen instead of hydrogen as carrier gas resulted in an increase of the growth rate and substitutional C incorporation both by a factor of two, while the surface defect density reduced. [ABSTRACT FROM AUTHOR]

The effective bandgap is a crucial design parameter of heterojunction tunneling field-effect transistors. In this letter, we demonstrate a method to measure the effective bandgap directly from the band-to-band tunneling current of a heterojunction Esaki diode, of which we only require knowledge of the electrostatic potential profile. The method is based on a characteristic exponentially increasing current with forward bias, caused by sharp energy filtering at cryogenic temperature. We apply this method experimentally to a n+In0.53Ga0.47As/pGaAs0.5Sb0.5 Esaki diode and define requirements to apply it to other heterojunctions. [ABSTRACT FROM AUTHOR]

Vertical InAs nanowires (NWs) grown on a Si substrate are promising building-blocks for next generation vertical gate-all-around transistor fabrication. We investigate the initial stage of InAs NW selective area epitaxy (SAE) on a patterned Si (111) substrate with a focus on the interfacial structures. The direct epitaxy of InAs NWs on a clean Si (111) surface is found to be challenging. The yield of vertical InAs NWs is low, as the SAE is accompanied by high proportions of empty holes, inclined NWs, and irregular blocks. In contrast, it is improved when the NW contains gallium, and the yield of vertical InxGa1-xAs NWs increased with higher Ga content. Meanwhile, unintentional Ga surface contamination on a patterned Si substrate induces high yield vertical InAs NW SAE, which is attributed to a GaAs-like seeding layer formed at the InAs/Si interface. The role of Ga played in the III-V NW nucleation on Si is further discussed. It stabilizes the B-polarity on a non-polar Si (111) surface and enhances the nucleation. Therefore, gallium incorporation on a Si surface is identified as an important enabler for vertical InAs NW growth. A new method for high yield (>99%) vertical InAs NW SAE on Si using an InGaAs nucleation layer is proposed based on this study. [ABSTRACT FROM AUTHOR]

TCAD finite-element process simulations have been performed on Ge-channel n and pMOSFETs with embedded source/drain stressors or a strained Ge channel on a relaxed SiGe strain relaxed buffer (SRB), respectively, and compared with nanobeam diffraction strain measurements. While there is overall a good agreement between the simulated and experimental strain profiles, some deviations may occur, due to the presence of extended defects in the strain relaxed Ge buffer layers. This highlights the importance of selection of a strain-free reference in the relaxed Ge or SiGe SRB. [ABSTRACT FROM AUTHOR]

In order to integrate k = 2.0 p-OSG dielectric materials into the next generation of interconnects, the porous material has to be sealed against metal barrier precursor. For this purpose, the combination of pore stuffing and SAMs was engineered on patterned structures to achieve sealing with minimal plasma damage. First a pore stuffing (P4) approach was implemented to mitigate the plasma damage and to confine the reaction sites to the top surface. Then self-assembled monolayers (SAMs) were deposited from 11-cyanoundecyltrichlorosilane (CNSAM) or (3-aminopropyl)-trimethoxysilane (APTMS) precursor, followed by TiN metal barrier deposition via plasma enhanced-atomic layer deposition (PE-ALD). Pore sealing efficiencies and k value of these samples were benchmarked against standard back end of line (BEOL) CF 4 plasma. [ABSTRACT FROM AUTHOR]

In this work, we observe the switching mechanisms in non-filamentary resistive switching (RS) devices, investigated through a nanosized conductive tip used as a movable (virtual) top-electrode. The correlation between different conductive states of vacancy-modulated conductive oxide (VMCO) cells and the conductive domains in thin TiO 2 is provided. We observe the appearance of uniformly distributed conductive spots whose conductance can be reversibly modulated using a scanning biased conductive tip. Although TiO 2 has been often used as a material system for filamentary RS, these results clearly demonstrate the non-filamentary switching nature of valence change memory (VCM) cells. This supports their strong potentials in the area of applications where aggressive scaling and low-current operation is required. [ABSTRACT FROM AUTHOR]

The basic unit of information infilamentary-based resistive switchingmemories is physically stored in a conductive filament. Therefore,the overall performance of the device is indissolubly related to theproperties of such filament. In this Letter, we report for the firsttime on the three-dimensional (3D) observation of the shape of theconductive filament. The observation of the filament is done in ananoscale conductive-bridging device, which is programmed under realoperative conditions. To obtain the 3D-information we developed adedicated tomography technique based on conductive atomic force microscopy.The shape and size of the conductive filament are obtained in three-dimensionswith nanometric resolution. The observed filament presents a conicalshape with the narrow part close to the inert-electrode. On the basisof this shape, we conclude that the dynamic filament-growth is limitedby the cation transport. In addition, we demonstrate the role of theprogramming current, which clearly influences the physical-volumeof the induced conductive filaments. [ABSTRACT FROM AUTHOR]

V-defects can be very detrimental to the functionality of GaN based light emitting diodes (LEDs) and high power transistors grown on 200 mm Si (111) substrates. This work focuses on reducing these detrimental defects in the GaN/AlGaN/AlN stacks grown in a Veeco Turbodisc Maxbright MOCVD system. The origins of V-defects in GaN/AlGaN/AlN material were studied by cross-sectional transmission electron microscope (TEM) and high angle annular dark field scanning transmission electron microscopy (HAADF-STEM). It was found that V-defects were associated with inversion domain boundary (IDB) like defects, which started from the interface between the AlN nucleation layers and the Si (111) substrates. These IDB-like defects were terminated by generating V-defects in the upper layers. Encouraging the 2-D GaN growth mode helped to close these V-defects in the GaN layers, but relaxed the built-in compressive stress faster and resulted in excessive wafer bow. Optimizing the V/III ratio during the AlN nucleation step improved AlN crystal quality and surface morphology, and close V-defects in GaN without degrading wafers stress condition. [ABSTRACT FROM AUTHOR]

Abstract: We report on the synthesis of Cu3Ge films by exposing Cu films to germane (GeH4). The process window was established by investigating the influence of the GeH4 partial pressure, the soak temperature, and the soak time on Cu films of different thickness. It is shown that short exposures of germane led to Cu-rich germanides, while an excessive GeH4 supply resulted in a Cu3Ge/Ge mixed phase. The germanidation reaction was found to be selective and required the prior removal of the native Cu oxide by in situ plasma cleaning. X-ray diffraction and transmission electron microscopy showed that the Cu3Ge films were crystalline as deposited in the orthorhombic phase and were textured. The films were homogenous in composition. Thin films consisted of Cu3Ge islands connected by a thin wetting layer. Fully continuous layers were however found for larger film thicknesses. The continuity of the Cu3Ge film was also found to be influenced by the pseudosubstrate: the films were more continuous on TaN/Ta than on SiO2. The electric properties of the Cu3Ge films on both TaN/Ta and SiO2 pseudosubstrates are presented and compared. [Copyright &y& Elsevier]

A combined deep-level transient spectroscopy (DLTS) and electron spin resonance (ESR) study is performed to identify the electrically active defects at the AlN/Si (111) interface. It is shown that the density of deep-level states not only depends on the thermal budget of the epitaxial deposition but also on the strain built up during growth and upon cooling to room temperature (RT). At the same time, diffusion of Si into the 200 nm thick AlN layer produces a thin crystalline Si3N4 interfacial layer, identified by transmission electron microscopy (TEM). This gives rise to so-called dangling bond Pb centres at the Si3N4/Si (111) interface. In addition, a strong evolution of the electrically active defect clusters in the silicon substrate close to the interface has been observed both in DLTS and ESR. [ABSTRACT FROM AUTHOR]

Abstract: In this paper we present a procedure and software allowing to predict and understand device performance by incorporating two dimensional (2D)-carrier profiles obtained from high vacuum scanning spreading resistance microscopy (HV-SSRM) into a device simulator. We demonstrate the incorporation of quantified SSRM 2D-carrier profiles obtained on p-MOSFETs into a device simulator. The simulated electrical characteristics (based on the measured 2D-carrier profiles) of the device show nice agreement with the experimentally obtained device results, whereas calculations based on process simulations with available advanced calibration showed significant discrepancies. With this approach the difficult and time consuming calibration step of the process simulation can be circumvented and device results can be interpreted directly based on the details of the real 2D-carrier profiles. [Copyright &y& Elsevier]

Abstract: The Implant-Free Quantum Well Field-Effect Transistor (FET) offers enhanced scalability in a planar architecture through the integration of heterostructures. The Implant-Free architecture fully utilizes the band offsets between different materials, whereby charge carriers are effectively confined to a thin channel layer. This prevents sub-surface source/drain leakage observed in classical bulk Metal-Oxide-Semiconductor FETs at small gate lengths. An investigation of the VT-tuning capabilities of this technology reveals sensitivity to both well doping and bulk voltage. [Copyright &y& Elsevier]

Graphene and carbon nanotubes (CNTs) are both carbon-based materials with remarkable optical and electronic properties which, among others, may find applications as transparent electrodes or as interconnects in microchips, respectively. This work reports on the formation of a hybrid structure composed of a graphitic carbon layer on top of vertical CNT in a single deposition process. The mechanism of deposition is explained according to the thickness of catalyst used and the atypical growth conditions. Key factors dictating the hybrid growth are the film thickness and the time dynamic through which the catalyst film dewets and transforms into nanoparticles. The results support the similarities between chemical vapor deposition processes for graphene, graphite, and CNT. [ABSTRACT FROM AUTHOR]

Abstract: Scaling air-gap interconnects to 70nm pitch is demonstrated for the first time by combining air-gap technology (SiO2 etch-back and non-conformal CVD) and the double patterning approach. A capacitance reduction of 45% was measured on the air-gaps compared to the SiO2 reference. The reliability performance of the air-gaps was then evaluated and it was found that the structures exceeded 10years lifetime at 2MV/cm, almost matching the performance of SiO2 interconnects. Air-gaps could therefore make a promising low-RC solution for future technology nodes. [Copyright &y& Elsevier]

Abstract: Downscaling of the metal–insulator–metal capacitor (MIMCAP) for Dynamic Random Access Memory (DRAM) requires the introduction of high permittivity dielectrics. MIMCAP structures formed with RuO2/Ru as bottom electrode, rutile TiO2 as dielectric and TiN as top electrode are described. Ozone (O3) is needed as oxidant in the TiO2 atomic layer deposition (ALD) process in order to obtain the rutile phase (permittivity>80), while anatase TiO2 (permittivity ∼40) is obtained with H2O. As O3 etches the ruthenium substrate, an ultra-thin interlayer of TiO2 was first grown with H2O, followed by the thick TiO2 layer deposited with O3. In order to minimize the content of anatase in the TiO2 layer, responsible for a reduced dielectric constant, we investigate the effect of scaling down the thickness of the protective H2O based inter-layer on the equivalent oxide thickness (EOT) and leakage current density (J g). The four times reduction in thickness without affecting the integrity of the ruthenium substrate resulted in a significant decrease of both EOT and J g. [Copyright &y& Elsevier]

Abstract: A powerful method to study carbon nanotubes (CNTs) grown in patterned substrates for potential interconnects applications is transmission electron microscopy (TEM). However, high-quality TEM samples are necessary for such a study. Here, TEM specimen preparation by focused ion beam (FIB) has been used to obtain lamellae of patterned samples containing CNTs grown inside contact holes. A dual-cap Pt protection layer and an extensive 5kV cleaning procedure are applied in order to preserve the CNTs and avoid deterioration during milling. TEM results show that the inner shell structure of the carbon nanotubes has been preserved, which proves that focused ion beam is a useful technique to prepare TEM samples of CNT interconnects. [Copyright &y& Elsevier]

The reaction of a Ti (8 nm) capped Co film (15 nm) with a Si[sub 3]N[sub 4] layer (150 nm) is studied after rapid thermal annealing at 660 °C for 120 s in a N[sub 2] ambient. X-ray photoelectron spectroscopy, transmission electron microscopy, electron energy-loss spectroscopy, and Auger electron spectroscopy are used to study the reaction products. Combining the results of the different analyses yields a layer stack consisting of: TiO[sub 2]/TiO/unreacted Co/(Ti,Co)[sub 2]N/Co[sub 2]Si, followed by amorphous Si[sub 3]N[sub 4]. The reaction mechanisms are discussed. Conclusions concerning the risk for degradation of nitride spacers in advanced devices are drawn. © 2000 American Institute of Physics. [ABSTRACT FROM AUTHOR]

The ability to develop ferroelectric materials using binary oxides is critical to enable novel low-power, high-density non-volatile memory and fast switching logic. The discovery of ferroelectricity in hafnia-based thin films, has focused the hopes of the community on this class of materials to overcome the existing problems of perovskite-based integrated ferroelectrics. However, both the control of ferroelectricity in doped-HfO2 and the direct characterization at the nanoscale of ferroelectric phenomena, are increasingly difficult to achieve. The main limitations are imposed by the inherent intertwining of ferroelectric and dielectric properties, the role of strain, interfaces and electric field-mediated phase, and polarization changes. In this work, using Si-doped HfO2 as a material system, we performed a correlative study with four scanning probe techniques for the local sensing of intrinsic ferroelectricity on the oxide surface. Putting each technique in perspective, we demonstrated that different origins of spatially resolved contrast can be obtained, thus highlighting possible crosstalk not originated by a genuine ferroelectric response. By leveraging the strength of each method, we showed how intrinsic processes in ultrathin dielectrics, i.e., electronic leakage, existence and generation of energy states, charge trapping (de-trapping) phenomena, and electrochemical effects, can influence the sensed response. We then proceeded to initiate hysteresis loops by means of tip-induced spectroscopic cycling (i.e., "wake-up"), thus observing the onset of oxide degradation processes associated with this step. Finally, direct piezoelectric effects were studied using the high pressure resulting from the probe's confinement, noticing the absence of a net time-invariant piezo-generated charge. Our results are critical in providing a general framework of interpretation for multiple nanoscale processes impacting ferroelectricity in doped-hafnia and strategies for sensing it. [ABSTRACT FROM AUTHOR]

Dark-field holography, a new transmission electron microscopy technique for mapping strain distributions at the nanoscale, is used to characterize strained-silicon n-type transistors with a channel width of 65 nm. The strain in the channel region, which enhances electron mobilities, is engineered by recessed Si0.99C0.01 source and drain stressors. The strain distribution is measured across an array of five transistors over a total area of 1.6 μm wide. The longitudinal tensile strain reaches a maximum of 0.58%±0.02% under the gate oxide. Theoretical strain maps obtained by finite element method agree well with the experimental results. [ABSTRACT FROM AUTHOR]

The density of hafnium oxide films grown by atomic layer deposition for high-κ gate dielectric applications was investigated for films with thickness in the nanometer range. The density, measured by combining the film thickness from transmission electron microscopy with the amount of hafnium deposited from Rutherford backscattering, decreased with decreasing film thickness. The dielectric constant of hafnium oxide remained constant with decreasing film thickness, however. The main reason for the decrease in the measured density seemed not to be a decrease in the inherent material density. Instead, the relative importance of interface roughness in the density measurement increased with decreasing film thickness. [ABSTRACT FROM AUTHOR]