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This work addresses the origin of the transient body potential variation in silicon on insulator (SOI) with deposited metal contacts, under back-gate bias sweep from accumulation to inversion. The phenomenon arises from the difficulty to inject carriers into the silicon film due to the Schottky contact between the metal and the low p-type doped silicon. The Schottky diode current is controlled by the back-gate voltage, which fixes the potential at the bottom of the low-doped film. When the back-gate voltage drives the silicon film towards inversion, the limited current from the Schottky contact induces a deficit of minority carriers in the film and brings the body potential in an out-of-equilibrium regime. This phenomenon will be reproduced with numerical modelling based on Poisson and continuity equations, including the quasi-Fermi potential. The transient character and its dependence on the Schottky barrier height will be evidenced. A simple and effective combination of the classic Schottky current equation and inversion current calculated from the Lambert function, as in fully depleted (FD)-SOI MOSFETs, confirms the origin of the effect.

In this article, threshold-voltage VTH instabilities under positive gate voltage stress VGStress in GaN-on-Si devices are thoroughly investigated. Measurement-stress-measurement pBTI technique using ultrafast VG ramp was applied in this study. PBTI transients performed at different VGStress and several temperatures highlight the influence of two trap populations, one being related to Al2O3 gate oxide defects and the other one to CN acceptors in GaN lattice. Both trap populations are located close to the Al2O3/GaN interface and lead to VTH instabilities via two different underlying mechanisms simulated by TCAD. PBTI transients obtained under several dc and ac stress conditions have also been modeled using capture emission time (CET) maps and allowed the identification of the two trap populations. Analysis of the temperature-dependent CET maps gives an activation energy of 0.8–0.9 eV related to CN traps and an energy range between 0.7 and 1.5 eV ascribed to Al2O3 defects above the GaN conduction band energy. This study provides a better understanding of the underlying physical mechanisms, leading to BTI degradation in GaN-HEMT technologies.

We target the parameter extraction from ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics and modeling of organic thin-film transistors (OTFTs) from 150 K up to 350 K (in two different manufacturing technologies). We also analyze the temperature dependence of the extracted parameters. For that purpose, we used a unified model and parameter extraction method at different temperatures adapted to OTFTs. We validated our model by comparison with experimental ${I}$ – ${V}$ characteristics in both the linear and saturation regimes and ${C}$ – ${V}$ characteristics at different frequencies.

International audience; This work presents the performance and low-frequency noise (LFN) of 22-nm fully-depleted silicon-on-insulator (FDSOI) CMOS technology. The experimental measurements and the analysis are performed as a function of temperature for the first time, focusing on cryogenic applications, down to 4.2 K. The back bias impact on device performance is evaluated. The results reveal that the threshold voltage tuning is found to be temperature independent, allowing extra drain current improvement. This is particularly interesting for short channel devices, whose drain current gain with temperature lowering is expected to be smaller in comparison with long channel MOSFETs. LFN is characterized by means of time-domain current sampling measurements. Moderate and strong inversion regimes are investigated. The carrier number with correlated mobility fluctuations model can well describe the 1/f noise behavior down to 4.2 K. The physical origin behind the drain current noise-to-signal power augmentation with temperature lowering could be mainly attributed to the normalized transconductance improvement.

International audience; The wide range of cryogenic applications, such as spatial, high performance computing or high-energy physics, has boosted the investigation of CMOS technology performance down to cryogenic temperatures. In particular, the readout electronics of quantum computers operating at low temperature requires larger bandwidth than spatial applications, so that advanced CMOS node has to be considered. FDSOI technology appears as a valuable solution for co-integration between qubits and consistent engineering of control and read-out. However, there is still lack of reports on literature concerning advanced CMOS nodes behavior at deep cryogenic operation, from devices electrostatics to mismatch and self-heating, all requested for the development of robust design tools. For these reasons, this chapter presents a review of electrical characterization and modeling results recently obtained on ultra-thin film FDSOI MOSFETs down to 4.2 K.

In this paper, the flicker noise properties of bottom-gate ESL structured amorphous InGaZnO (a-IGZO) thin-film transistors (TFTs) from two different technologies have been studied and modeled. Model development is carried out by adapting the Unified Model parameter Extraction Method (UMEM), developed for parameter extraction and compact modeling of TFT devices, and the unified 1/f noise model. Furthermore, comparative study of device figures of merits is performed to point out the device performance enhancements that the different fabrication technologies have brought about. It is found out that both devices have low deep state density, whereas the second device demonstrated higher performance in terms of carrier mobility and subthreshold slope. Both the DC and noise models are validated by matching them against experimental data obtained in different regimes of device operation.

International audience; A new protocol based on Y-function is used for accurate statistical extraction of electrical parameters of High Electron Mobility Transistor (HEMT) devices for GaN technology. This protocol presented here is used for extraction of relevant electrical parameters such as oxide capacitance, threshold voltage, effective mobilities and access resistance. This study has been verified over a large range of channel lengths for two normally-off HEMT GaN wafers having different levels of access resistances.

FD-SOI five-gate (5G) qubit MOS devices are electrically characterized in linear regime down to deep cryogenic temperatures. The Lambert-W function is successfully used for the modelling of such 5G MOS devices from subthreshold regime to strong inversion. Its applicability is demonstrated down to 20 K. The 5G device is modeled as a series of five independent transistors: the "active" one, that directly controls the current, and the "external" ones, that act as access resistances. The Lambert-W function enables to accurately determine the inversion charge and the active channel resistance from weak to strong inversion. This approach allows reconstructing the drain current characteristic avoiding the evaluation of the mobility attenuation factors. The main device parameters are extracted versus temperature. Finally, the role of different scattering mechanisms has been investigated, underlying the impact of neutral defects for the gates in proximity of source and drain.

Junctionless transistors (JLTs) have promising advantages such as structural simplicity without p-n-junctions and bulk conduction-based operation for the realization of advanced complementary metal oxide semiconductor (CMOS) technologies. Here the channel-length dependence on the operation of JLTs with substrate biasing ( ${V}_{\text {gb}}$ ) was investigated in detail. Parasitic series resistance ( ${R}_{\text {sd}}$ ) noticeably decreased as ${V}_{\text {gb}}$ increased. In addition, transconductance ( ${g}_{\text {m}}$ ), its derivative ( dg m/ dV gf), and ON-drain current ( ${I}_{ \mathrm{\scriptscriptstyle ON}}$ ) in a short-channel JLT were significantly affected by the ${V}_{\text {gb}}$ -modulated ${R}_{\text {sd}}$ with charge coupling effects. This work provides important information for better understanding and true estimation of intrinsic JLT performance, for practical applications based on polycrystalline Si, III–V semiconductors, and transition metal dichalcogenides (TMDs) nano-materials as well as advanced logic devices.

International audience; The applicability of the Lambert-W function-based parameter extraction methodology is demonstrated for 28nm FDSOI MOSFETs down to deep cryogenic temperatures (4.2K). The Lambert-W function enables to accurately model the inversion charge and drain current MOSFET characteristics from weak to strong inversion, while using the classical mobility law down to liquid helium temperature. The main MOSFET parameters were extracted versus temperature and gate length, showing the temperature independence of short channel effects and the strong mobility degradation at short channel length due to increased neutral defect scattering.

In this paper we present an analytical experimental study regarding the extraction and analysis of 28 nm FD-SOI MOSFET parameters, from room temperature down to 25 K, and from micro- to nanometer gate lengths. It is shown that the FD-SOI device behavior with temperature can reliably be described by the already established theory of physics for deep cryogenic conditions: Boltzmann statistics and phonon scattering mechanisms are the two main factors that define the device electrical behavior. Moreover, we also demonstrate the advantage of the Y-function as a parameter extraction method, across different channel lengths, and a wide temperature range. We demonstrate the dependence of threshold voltage, sub-threshold swing, low-field mobility and source-drain series resistance on temperature, and how this may be affected by the gate length decrease.

We target the analysis and modeling of the I-V characteristics in organic thin film transistors (OTFTs) and IGZO TFTs from 150K to 350K, as well as the temperature dependences of the extracted parameters. Our compact model reproduces very well the I-V characteristics within that range of temperatures for both types of devices.

This paper discusses the impact of both contact and channel resistance on capacitance and conductance characteristics measured with pseudo-MOSFET method by analyzing the impedance and admittance in frequency domain. We clarify the mechanisms affecting the ac response of pseudo-MOSFET structure for SOI wafer with thin SOI film by using simple series and parallel circuits composed of resistance and capacitance. Our measurement results show the gate bias range where the influence of the contact resistance becomes dominant in measurements with single and multiple probes. The degradation of the capacitance measured at high frequency is also analyzed by constructing an equivalent circuit, which detach the influence of the contact and channel resistances quantitatively. The necessity to carefully account for the influence of the contact resistance in pseudo-MOS method is clarified.

International audience; A new concept of differential effective mobility is proposed. It characterizes the effective mobility of an increment of drain current resulting from a small increase of inversion charge in MOSFET channel. It allows us to show that the effective mobility can be described by a local electric field approach and not entirely by an effective electric field model.

A comprehensive Kubo-Greenwood modelling of FDSOI MOS devices is carried out down to deep cryogenic temperatures. It is found that a single set of mobility parameters is only needed to fit the device characteristics versus temperature for long channel devices. Instead, in short channels, the neutral scattering mobility component µN is found to decrease at small gate length due to the increased presence of neutral defects close to source/drain ends whatever the temperature.

International audience; New analytical expressions for the subthreshold swing in FDSOI structures operated in both front gate and bottom gate modes are developed. These new equations (9)-(10) provide an accurate description of the subthreshold swing SW as a function of the main FDSOI stack parameters (film thickness, front gate thickness, back gate oxide thickness) and front/back interface trap density. They can be very useful for architecture design as well as electrical characterization of FDSOI devices operated either in front gate or free top surface bottom gate configurations.

This work presents a new method, called “pinch to detect”, for the characterization of Random Telegraph Noise (RTN) in nanometer length Tri-Gate Nanowire MOSFETs, allowing for the maximum number of active RTN traps to be detected. We demonstrate that the channel pinch-off effect, which takes place in saturation region, can actually be exploited for the modulation of RTN amplitudes and kinetics, and therefore disable (or enable) the appearance of RTN signals which are present (or not) in linear region, where the channel is uniform. It is shown that by combining the measurements for three different channel configurations, i.e. uniform, pinched-off near the drain and pinched-off near the source, the total number of detectable RTN traps can be maximized. This conclusion is also supported by noise spectral analysis and TCAD simulations. Furthermore, it is demonstrated through how going to longer channels with no short-channel effects does not make this effect disappear, but just limit it to traps in the pinched-off region.

Under several circumstances, a nanowire transistor with a square cross-section behaves as a circular. Taking the Gate-All-Around junctionless transistor as a primary example, we investigate the transition of the conductive region from square to circle-like. In this case, the metamorphosis is accentuated by smaller size, lower doping, and higher gate voltage. After defining the geometrical criterion for square-to-circle shift, simulation results are used to document the main consequences. This transition occurs naturally in nanowires thinner than 50 nm. The results are rather universal, and supportive evidence is gathered from inversion-mode Gate-All-Around (GAA) MOSFETs as well as from thermal diffusion process.

International audience; This paper presents an electrical characterization and a compact modeling of FD-SOI fourgate qubit MOS devices, carried out at room temperature and in linear regime. The main figures ofmerit are extracted from average drain current curves using Y – function method. Poisson solver-based simulations are performed to interpret the experimental data, in particular the influence among gates and the effective channel length modulation. Furthermore, a drain current matching analysis between gates is conducted, and the main variability parameters are extracted. Our results, despite the unconventional device engineering, show a variability performance comparable to the state-of-the-art 28nm FD-SOI technology. Finally, a Lambert function based model is developed to validate both the electrical and statistical characterization. It is assumed, according to the experimental data, that the four gate device can be modeled as the series of four identical and independent transistors. Including the contribution of source and drain access resistance it has been possible to reproduce the device behavior at high external gates voltages.

In this study, we investigate the difference between I D (V G ) and C(V G ) pBTI shifts on GaN-on-Si E-mode MOS-channel HEMTs, under various gate voltage stresses (V GStress ) and temperatures (T). A new experimental setup using ultra-fast and simultaneous I D (V G ) and C(V G ) measurements enables to monitor the threshold voltage V TH drift through two metrics, $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$ . Experimental pBTI results depict a difference between $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ and $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$ , such as $\mathrm{\Delta}\mathrm{V}_{\text{THI}} . TCAD simulations support that ID(V G ) shift ( $\mathrm{\Delta}\mathrm{V}_{\text{THI}}$ ) is related to charge trapping in Al 2 O 3 gate oxide defects at the gate corners regions while C(V G ) shift ( $\mathrm{\Delta}\mathrm{V}_{\text{THC}}$ ) is mainly ascribed to the gate bottom, due to the presence of a back-barrier layer in the epitaxy. These previous results enable to deduce that the Al 2 O 3 defects density is more important at the gate corners than at the gate bottom.

We review recent compact modeling solutions for Organic and Amorphous Oxide TFTs (OTFTs and AOS TFTs, respectively), which were developed, under the framework of the EU-funded project DOMINO, to address issues specifically connected to the physics of these devices. In particular, using different approaches, analytical equations were formulated to model the Density of States (DOS), different transport mechanisms, trapping/de-trapping, drain current, stress, capacitances, frequency dispersion and noise. The final TFT models were, after implementation in Verilog-A, validated by means of the design and simulation of test circuits.

In this work, a continuous and symmetric trans-capacitance compact model for triple-gate junctionless MOSFETs is presented, valid in all regions of operation. Initially, the expressions of the gate, drain and source total charges are analytically derived based on a continuous and symmetric drain current compact model already developed. Then, the intrinsic capacitances are calculated via the differentiation of the terminal charges, verified against TCAD simulation data. The AC symmetry tests of the trans-capacitance compact model are thoroughly investigated.

This article presents a new methodology for the extraction of low-frequency noise (LFN) or random telegraph noise (RTN) parameters, such as the gate oxide interface trap density, ${N}_{\text {t}}$ , and the mobility fluctuations factor, $\Omega $ , without the influence of the source/drain series resistance, ${R}_{\text {sd}}$ . The method utilizes the ${Y}$ -function—which is immune to any first-order degradation, including the series resistance—as well as the intrinsic mobility degradation factors $\theta _{ {1,0}}$ and $\theta _{{2}}$ . The proposed extraction technique is first demonstrated through numerical calculations and then applied on experimental results of n-channel short length FinFETs. It is shown that if the ${R}_{\text {sd}}$ impact is not accounted for, the extracted LFN parameters through the classic carrier number fluctuations (CNF) with correlated mobility fluctuations (CMF) model can lead to significant extraction errors. This mainly concerns the correlated mobility factor $\Omega $ , which may be strongly underestimated, but also the extraction of the trap density ${N}_{\text {t}}$ .

In this article, we have studied the drain current and transconductance of nMOS fully depleted silicon-on-insulator (FDSOI) transistors operating at low temperature (typically < 20 K) when back gate is forward biased. Humps appear in the current, leading to oscillations of the transconductance with gate voltage, owing to mobility discontinuity due to intersubband scattering, in relation with the 2-D subband structure. The conditions for which these specific features appear in thin-film silicon-on-insulator (SOI) devices have been analyzed, by varying the temperature, drain voltage, silicon channel thickness, and gate length.

A novel technique is presented for a direct evaluation of oxide breakdown under AC stress at high frequencies up to 500MHz. It relies on a RF setup, which combines a high speed pulse generator, transition converters and $50\Omega $ termination probes, to deliver to the device a digital AC signal without overshoot and distortion. The method leads to similar results than a complex on-chip solution while offering more simplicity and flexibility. Time Dependent Dielectric Breakdown (TDDB) in 28nm Fully Depleted Silicon On Insulator (FDSOI) transistors is then characterized under DC and AC stress at various frequencies. It follows a power law with frequency TDDB $\alpha \text{F}^{\mathbf {a}}$ with a ≈0.3, allowing an extended lifetime to circuits operating at GHz frequency.

A comprehensive analysis of the MOSFET subthreshold swing for a 2D subband with exponential band tail of states is first proposed. Then, a compact analytical expression for the subthreshold swing as a function of temperature is derived, well accounting for both its cryogenic temperature saturation and classical higher temperature increase. Moreover, a generalized subthreshold swing calculation applicable to the situation where the MOSFET drain current should be evaluated from the conductivity function within the Kubo-Greenwood formalism is developed.

28 nm FD-SOI technology is electrically characterized aiming at cryogenic applications. Electrostatics and transport are evaluated and compared while lowering temperature from 300 K down to 4.2 K. FD-SOI versatility is shown over a wide temperature range of operation, as the back gate tuning efficiency is preserved at low temperatures. Insights on back gate bias behavior at room and low temperatures are obtained and the electrostatic coupling between front and back channels can be successfully modelled by using 1D Poisson-Schrodinger calculation from 300 K down to 4.2 K.

Junctionless transistors (JLTs) are one of attractive candidates for further scaling down thanks to their promising advantages based on a structural simplicity without PN junctions, and their physical operation is quite different from traditional inversion-mode (IM) transistors. In this paper, we investigated the subthreshold operation of tri-gate JLTs with various effective width (Weff) and compared to that of IM transistors. The on current to off current ratio (Ion/Ioff) and subthreshold swing (SS) of JLTs were varied dramatically as changing Weff. In addition, a better immunity against short channel effects (SCEs) of JLTs was proven. Physical operation mechanism on the subthreshold regime was also discussed in detail with considering distribution of mobile charge carriers, maximum depletion width, full-depletion mode, bulk neutral and surface accumulation conduction.

This paper investigates the local variability in nanoscale triple-gate junctionless FinFETs utilizing an analytical symmetric and continuous compact model combined with Monte Carlo simulations. Initially, the device parameters are extracted from the experimental transfer characteristics, such as threshold voltage, ideality factor, low-field mobility, source-drain series resistance, channel length modulation factor and mobility degradation factor. Then, statistical analysis is performed to calculate the mean values and standard deviations of the differences of the aforementioned parameters for the local pairs and large number of devices with reference to the mean value of all dies. Monte Carlo simulations allow the compact model to reproduce successfully the drain current local variability. Most important process parameters have been considered and assessed as variability sources, by using the error propagation formula and exploiting the proposed drain current compact model. Successful application to experimental data, revealed the extent of the variabilities in most important process parameters of the devices (sources of variability).

Variability of28nm FD-SOI transistors is evaluated for the first time down to ultra low temperatures (UL T), at T= 1 00mK. High performance is achieved at UL T for short channel transistors, with $\mathrm{I}_{\mathrm{ON}} > 1\mathrm{mA}\mu \mathrm{m}$ and $\mathrm{I}_{\mathrm{OFF}}$ below the equipment accuracy $(\mathrm{V}_{\mathrm{TH}})$ and current gain factor $(\beta)$ variabilities. Besides that, we demonstrated that the increase of $\mathrm{V}_{\mathrm{TH}}$ and $\beta$ variabilities at low temperature remains reasonably low in comparison to RT values and other CMOS technologies, so that it should not be detrimental to circuit operation in this range of temperatures.

We investigated the performances of GaN junctionless fin-shaped field-effect transistors (FinFETs) with two different types of gate structures; overlapped- and partially covered-gate. DC, low-frequency noise (LFN), and pulsed I-V characterization measurements were performed and analyzed together in order to identify the conduction mechanism and examine both the interface and buffer traps in the devices. The fabricated GaN junctionless device with overlapped-gate structure exhibits improved DC and noise performance compared to the device with partially covered-gate, even though its gate length is much larger. The LFN behavior was found to be dominated by carrier number fluctuations (CNF). At off-state, the device with partially covered-gate exhibits generation-recombination (g-r) noise on top of 1/ ${f}$ noise. This superposition is correlated with the severe current collapse revealed by pulsed I-V measurements. In contrast, the device with overlapped-gate shows clear 1/ ${f}$ behavior without g-r noise.

Mismatch performance of 28 nm FDSOI technology is electrically characterized at low temperatures using integrated on-chip addressing for a matrix of transistors. The first statistical results ever published on FDSOI variability at 4.2 K provide valuable information for future compact transistor modeling in cryogenic circuit design. Slight increase of the threshold voltage mismatch is observed at low temperature. Nevertheless, the suppression of fluctuations in the random distribution of dopants for the fully-depleted transistor channel leads to a smaller threshold voltage variability for FDSOI at 4.2 K compared to advanced Bulk technology at room temperature.

International audience; In this paper we demonstrate for the first time how the series resistance of an advanced CMOS device, such as the FinFET, can lead to an incorrect extraction of low-frequency noise parameters. In particular, the use of the carrier number fluctuations with correlated mobility fluctuations model is shown to be very sensitive to the transistor series resistance. We demonstrate how the classic fitting methods can lead to an underestimated value in the extraction of the mobility fluctuations factor Ω. Furthermore, we present an original method for suppressing this effect, by taking advantage of the series resistance immune Y-function.

The quality of interfaces between dielectrics and semiconductors has a tremendous impact on the performances of semiconductor devices. High-k dielectrics are omnipresent in the gate stack of advanced MOSFETs. They are also used as passivation layers for silicon in fields such as solar cells [1] or image sensors [2]. When referring to passivation, two mechanisms can be identified: chemical passivation (quantified by the interface state density, Dit) and electric-field passivation (quantified by fixed oxide charge density, Qox). An ideal characterization method for passivated silicon should give access to both chemical and field-effect relevant quantities (ideally being able to distinguish them) in a non-destructive way. Among the commonly used techniques, we can cite electrical methods based on current or capacitance monitoring of simple test devices [3], Corona characterization of semiconductors [4], carrier lifetime extraction [5] conducted through photoconductance or photoluminescence decay measurements, etc. The choice among these several options is based on criteria such as sensitivity, non-destructiveness, possibility of direct on-wafer probing without any additional device fabrication steps, ability to discriminate Dit and Qox, capability to provide a high spatial resolution. A recent technique which could meet all these criteria is the second harmonic generation (SHG) [6], provided that an appropriate calibration method is developed for Dit and Qox extraction. The SHG is a non-linear optics phenomenon: when a high intensity laser beam of wavelength λ reaches a sample, a second harmonic wave at λ/2 is generated by the sample. For centrosymmetric materials (such as silicon, SiO2, Al2O3, etc.) the SHG signal contains two parts: one related to the symmetry breaking inherently present at interfaces between two different materials, and another one produced by any “static” electric field in the sample [7]. Such field is present at the vicinity of dielectric-to-semiconductor interfaces due to charge trapping by various mechanisms. In other words, the magnitude of the generated SHG signal contains information on both Dit and Qox This technique has already been used for dielectric characterization with various modalities (SHG versus power, time, wavelength ...) [8], [9], [10]. The SHG proved very promising (sensitive, non-destructive, applied directly on-wafer, etc.); however its extensive use still needs a more general calibration methodology. Such a methodology requires not only SHG measurements, but also real Qox/Dit values extracted by classical electrical methods on the same samples and modeling to understand/anticipate the expected effect of these parameters on the SHG signal. In this paper, we’ll discuss all these issues based on a review of our recent advances on how to exploit SHG for dielectrics on semiconductor characterization. Acknowledgements This work was supported by Region Rhône Alpes (ARC6 program), the French National Research Agency within the framework of the OXYGENE project (ANR-17-CE05-0034) and French National Plan Nano2022, within the IPCEI Nanoelectronics for Europe program. [1] A. G. Aberle, "Surface passivation of crystalline silicon solar cells: a review," Progress in Photovoltaics: Research and Applications, vol. 8, pp. 473-487, 2000. [2] J. L. Regolini, D. Benoit, and P. Morin, "Passivation issues in active pixel CMOS image sensors," Microelectronics Reliability, vol. 47, pp. 739-742, 2007. [3] D. K. Schroder, Semiconductor Material and Device Chracterization, 3rd Edition ed. New Jersey: John Wiley & sons, 2006. [4] M. Wilson, J. Lagowski, L. Jastrzebski, A. Savtchouk, and V. Faifer, "COCOS (corona oxide characterization of semiconductor) non-contact metrology for gate dielectrics," AIP Conference Proceedings, vol. 550, pp. 220-225, 2001. [5] D. K. Schroder, "Carrier lifetimes in silicon," Electron Devices, IEEE Transactions on, vol. 44, pp. 160-170, 1997. [6] G. Lupke, "Characterization of semiconductor interfaces by second-harmonic generation," Surface Science Reports, vol. 35, pp. 75-161, 1999. [7] J. E. Sipe, D. J. Moss, and H. M. van Driel, "Phenomenological theory of optical second- and third-harmonic generation from cubic centrosymmetric crystals," Physical Review B, vol. 35, pp. 1129-1141, 1987. [8] J. Price, M. Lei, P. S. Lysaght, G. Bersuker, and M. C. Downer, "Charge trapping defects in Si/SiO2/Hf(1−x)SixO2 film stacks characterized by spectroscopic second-harmonic generation," Journal of Vacuum Science & Technology B, vol. 29, p. 04D101, 2011. [9] N. M. Terlinden, G. Dingemans, V. Vandalon, R. H. E. C. Bosch, and W. M. M. Kessels, "Influence of the SiO2 interlayer thickness on the density and polarity of charges in Si/SiO2/Al2O3 stacks as studied by optical second-harmonic generation," Journal of Applied Physics, vol. 115, p. 033708, 2014. [10] H. Park, J. Qi, Y. Xu, K. Varga, S. M. Weiss, B. R. Rogers, et al., "Boron induced charge traps near the interface of Si/SiO2 probed by second harmonic generation," Physica Status Solidi (b), vol. 247, pp. 1997-2001, 2010.

GaN-based materials are expected to show excellent immunity against short-channel effects because they have relatively lower permittivity and higher electron effective mass, compared to other materials such as Si, Ge, and In(Ga)As. To further reduce the short-channel effects, it is important to enhance the gate controllability of the device by utilizing a gate-all-around (GAA) structure. In this article, GaN vertical GAA nanowire MOSFETs with various diameters of 120, 75, and 45 nm have been fabricated. The device with a diameter of 120 nm shows a threshold voltage of 0.7 V, drain saturation voltage of 0.5 V, and subthreshold swing of 70 mV/decade, which would be suitable for low-voltage/power applications. However, the devices with smaller diameters of 75 and 45 nm show peculiar characteristics, such as a second rise of the drain current in output characteristics and a negative transconductance.

We target the device parameter analysis and drain current modelling for amorphous indium gallium zinc oxide (IGZO) thin film transistors from 210 to 370K. We study and discuss the temperature behaviour of physical IGZO TFT parameters from low to high temperatures. We demonstrated and explained that in IGZO TFTs, the characteristic temperature of the density of states (DOS) increases, with increasing temperature. Finally, using the extracted parameters, we validate our IGZO TFT drain current model at temperatures from 190K up to 370K.

In this article, we investigate the impact of the hot carrier (HC) aging on the performance of nanoscale n-channel triple-gate junctionless MOSFETs with channel length varying from 95 down to 25 nm. The devices were electrically stressed in the ON-state region of operation at fixed gate voltage ${V}_{g} = {1.8}$ V and drain bias ${V}_{d} = {1.8}$ V, with the stress time being a variable parameter. The device degradation was monitored through the relative change with stress time of the threshold voltage, subthreshold swing, linear drain current, low-field mobility, series resistance, and gate current. For relatively long-channel transistors ( ${L} = {95}$ nm), the threshold voltage and the subthreshold swing remain almost unchanged, whereas the ON-state drain current is degraded showing a good correlation with the series resistance degradation, caused by HC-induced damage in the drain region. For short-channel transistor ( ${L} = {45}$ nm), the HC-induced damage is extended in the channel region: interface traps are generated, exhibiting good correlation with both threshold voltage and low-field mobility degradations. For the very short-channel device ( ${L} = {25}$ nm), after long stress time, the HC-induced interface degradation is severe, causing a continuous increase of the ideality factor with increasing the gate voltage.

Poisson-Schrodinger (PS) simulations and an analytical charge model for a back biased FDSOI structure operated at deep cryogenic temperatures have been developed. PS simulations has been conducted down to 0K, where metallic statistics applies, by replacing the F0 Fermi integral by a Heaviside function. Considering, as a first approximation, two separated channels for front and back interface, a set of analytical equations has been established based on a single subband scheme within the Airy approach, providing a good description of surface potential, inversion charge and capacitance characteristics of FDSOI structures operated at very low temperature and for various back biases and silicon thicknesses. This analytical charge model is a first step towards a compact model of FDSOI MOSFET for circuit design at cryogenic condition.

Substrate-bias-affected unique electrical characteristics of junctionless transistors (JLTs) were investigated in detail. Bulk channel thickness of JLTs ( ${t}_{\mathrm {si\_{}eff}}$ ) was effectively modulated by back-gate bias ( ${V}_{\text {gb}}$ ). The variation in threshold voltage ( ${V}_{\text {th}}$ ) $\vphantom {^{\int }}$ and mobility degradation were observed in the reduced ${t}_{\mathrm {si\_{}eff}}$ , due to the negative ${V}_{\text {gb}}$ -induced depletion of free electrons. The ${V}_{\text {gb}}$ effect was also influenced significantly by the doping concentration in JLTs. In addition, numerical simulations verified those results and analytical equations explained well the experimental results.

In this chapter, we present the most important aspects of our recent research work concerning the low-frequency noise (LFN) characterization and modeling of Fully Depleted Silicon-on-Insulator (FDSOI) MOSFETs, as well as the development of circuit noise simulation methods. Before doing so, we make a brief introduction (Sect. 1) on the importance of LFN characterization and modeling, especially in sub-μm multi-interface devices such as the FDSOI MOSFETs.

A new differential method for accurate extraction of electrical parameters of high-electron mobility transistor (HEMT) devices for gallium nitride (GaN) technology is proposed. This method, presented here for the first time, is used to study the mobility degradation with gate length, allowing an analysis of the contribution of the gate edge region to the total metal–insulator semiconductor (MIS)-HEMT device conductance. First, an analytical model is proposed to account for the relative conduction of the edges and the main flat part of the channel HEMTs. Second, the differential method allows the split- CV mobility extraction of each part, allowing a precise analysis of the resistive contribution of each region of the HEMT devices. This study has been performed over a large range of channel lengths for two normally OFF HEMT GaN wafers having different recess depths.

Thorough investigations of the low-frequency noise (LFN) in a fully depleted silicon-on-insulator technology node have been accomplished, pointing out on the contribution of the buried oxide (BOX) and the Si-BOX interface to the total drain current noise level. A new analytical multilayer gate stack flat-band voltage fluctuation-based model has been established, and 2D numerical simulations have been carried out to identify the main noise sources and related parameters on which the LFN depends. The increase of the noise at strong inversion could be explained by the access resistance contribution to the 1/f noise. Therefore, considering uncorrelated noise sources in the channel and in the source/drain regions, the total low-frequency noise can simply be obtained by adding to the channel noise the contribution of the excess noise originating from the access region (Δr). Moreover, only two fit parameters are used in this work: the trap volumetric density in the BOX, and the 1/f access noise level originating from the access series resistance, which is assumed to be the same for the front and the back interfaces.

International audience; Unreliable mobility values, and particularly greatly overestimated values and severely distorted temperature dependences, have recently hampered the development of the organic transistor field. Given that organic field-effect transistors (OFETs) have been routinely used to evaluate the mobility, precise parameter extraction using the electrical properties of OFETs is thus of primary importance. This review examines the origins of the various mobilities that must be determined for OFET applications, the relevant extraction methods, and the data selection limitations, which help in avoiding conceptual errors during mobility extraction. For increased precision, the review also discusses device fabrication considerations, calibration of both the specific gate-dielectric capacitance and the threshold voltage, the contact effects, and the bias and temperature dependences, which must actually be handled with great care but have mostly been overlooked to date. This paper serves as a systematic overview of the OFET mobility extraction process to ensure high precision and will also aid in improving future research.