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In this paper, we demonstrate that the lateral band-to-band tunneling component of gate-induced drain leakage (GIDL) leads to the formation of a parasitic bipolar junction transistor (BJT) in the OFF-state (gate voltage = 0.0 V) of nanowire FETs (NW FETs). We discuss in detail the difference in the nature of GIDL, i.e., drain current dependence on the negative gate voltage ( V\text {GS} \le 0 V) for different NW FET configurations. Furthermore, we show that the parasitic BJT action is significant in NW junctionless accumulation mode FET (JAMFET) and NW MOSFET in the OFF-state and diminishes as the gate voltage becomes negative. Using calibrated 3-D simulations, we investigate the impact of scaling on the NW FETs and show that the enhanced band gap due to the quantum confinement effect facilitates the scaling of the NW FETs to the sub-5-nm regime. In addition, we propose the use of a lightly doped drain extension to increase the ON-state to OFF-state current ratio ( I {{\scriptscriptstyle {ON}}}/I {\scriptscriptstyle {OFF}}) of NW JAMFET and NW MOSFET. [ABSTRACT FROM AUTHOR]

In this paper, we propose a nanotube (NT) JLFET for significantly improved performance in the sub-10-nm regime. We show that the tunneling width at the channel-drain interface and the source-to-channel barrier height are considerably increased in the NT JLFET due to the presence of the core gate. Therefore, the lateral band-to-band-tunneling-induced parasitic bipolar junction transistor action is diminished in the off-state of NT JLFET, leading to a significantly high on-state to off-state current ratio of ~107 even for a channel length of 7 nm. Furthermore, we demonstrate that the spacer length and dielectric constant and the core gate diameter can be used as design parameters to further improve the performance of the NT JLFETs. Therefore, we also provide the necessary design guidelines for NT JLFETs. [ABSTRACT FROM PUBLISHER]

This paper reports a compact ambipolar model for homojunction strained-silicon (sSi) nanowire (NW) tunnel FETs (TFETs) capable of accurately describing both I – V and G – V characteristics in all regimes of operation, n- and p-ambipolarity, the superlinear onset of the output characteristics, and the temperature dependence. Experimental calibration on long channel (350 nm) complementary n- and p-type sSi NW TFETs has been performed to create the model, which is used to systematically benchmark the main analog figures of merit at device level: gm/{I}\text {d} , gm/gds , fT and fT/{I}d{V}d , and their temperature dependence from 25 °C to 125 °C. This allows for a direct comparison between 28-nm low-power Fully Depleted Silicon on Insulator (FD-SOI) CMOS node and 28-nm double-gate (DG) TFET. We demonstrate unique advantages of sSi DG TFET over CMOS, in terms of: 1) reduced temperature dependence of subthreshold swing; 2) higher transconductance per unit of current with peaks close to 40~\text V^-1 , for currents lower than 10 nA/ \mu \textm ; and 3) higher unity gain frequency per unit power for currents below 10 nA/ \mu \textm . [ABSTRACT FROM PUBLISHER]

Physical-model guided design on transistor test structures aiming for extracting backend metal charging design rules is demonstrated for the first time. Based on experimental data from a six-metal-layer technology, the demonstration shows such design methodology to be feasible. The methodology enables adequate design for the test structures from which a complete set of metal charging design rules can be extracted for a given process technology. This paper concludes that a significant reduction in the number of the required test structures and accordingly a large saving for test chip layout space during process development can be realized with the new design methodology. The number of the design-rule-extraction test structures could be reduced by a half for a six-metal-layer technology and by 77% for a thirteen-metal-layer layer technology, with a minimum number as low as four per transistor type, gate oxide thickness, and gate protection option if such methodology is adopted. The advantage inherited in the new methodology is delineated. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the carrier transport characteristics of the ultrascaled Si FinFETs. Traditional dc characterization technique is compared with the ultrafast pulsed IV method. Due to the severe self-heating effect introduced in the characterization process, the ballistic transport parameters extracted using dc method would show essential discrepancies from those in the real high-speed IC circuits. Therefore, an ultrafast pulsed IV measurement technique is proposed for accurate ballistic transport characterization. Furthermore, since the series resistance ( R{\textbf {SD}} ) of the Si FinFETs is temperature-dependent, a modified backscattering model is adopted to extract the ballistic transport parameters without the influence of the temperature-variant R{\textbf {SD}} . A ballisticity scaling model was established to predict the scalability of the ballistic transport parameters. It is found that very high ballisticity could be achieved for FinFETs with sub-10-nm technology nodes. [ABSTRACT FROM AUTHOR]

In this paper, we report the logic performance of CMOS circuits implemented with n- and p-channel junctionless (JL) FinFETs. A one-to-one comparison of the performance is made between such circuits and those implemented with n- and p-channel conventional inversion-mode (IM) FinFETs. The logic performance of a CMOS inverter is evaluated in terms of rise time and fall time for three different future technology nodes with the help of extensive 3-D device and mixed-mode circuit simulators. Frequency of oscillation of a three-stage ring oscillator (RO) is also obtained for such nodes. In spite of reduced ON-state current arising out of the higher channel doping and, hence, reduced carrier mobility in the JL devices, somewhat improved performance of the JL CMOS circuits over their IM counterparts are observed. For example, improvement of ~28% and ~10% in the rise time and fall time, respectively, for the inverter and ~12% in the frequency of oscillation of RO are observed for 10-nm technology node. Our investigations reveal reduced gate capacitance of the JL devices that in turn result in such improved performance of the JL CMOS circuits. Reduced gate capacitance also results in reduced dynamic power dissipation of JL CMOS circuits. [ABSTRACT FROM AUTHOR]

This paper presents a 3-D statistical simulation study of an n-channel Si step-FinFET due to work-function variability depending on grain orientation of metal gate. The statistical fluctuation induced by metal gate granularity on threshold-voltage ( \sigma VT ), ON current ( \sigma I \mathrm{\scriptscriptstyle ON} ), and OFF current ( \sigma I \mathrm{\scriptscriptstyle OFF} ) are estimated for a wide range of channel length and effective fin width for varying average grain size using Technology Computer Aided Design simulator. We investigated the effect of grain on magnitude of variability and also on shapes of various electrical parameters of distribution. The results indicate that \sigma VT decreases for increase in each dimension of the device. The value of \sigma I \mathrm{\scriptscriptstyle ON} , and \sigma I \mathrm{\scriptscriptstyle OFF} reduces as channel length increases. However, \sigma I \mathrm{\scriptscriptstyle ON} and \sigma I \mathrm{\scriptscriptstyle OFF} increase as fin width increases. The distribution of electrical parameters is near to normal for small grain size and becomes bimodal at large grain size. The proposed structure shows excellent behavior in terms of threshold-voltage ( VT ), subthreshold swing, and current ratio ( I \mathrm{\scriptscriptstyle ON}/I \mathrm{\scriptscriptstyle OFF} ) compared with conventional FinFET at high temperature. It is found that the hot carrier effect reduces with increased effective channel width. [ABSTRACT FROM AUTHOR]

In this paper, we present an accurate analytical potential model for the double-gate tunnel FETs (DG-TFETs) by solving Poisson’s equation with appropriate boundary conditions. Taking the mobile charge carriers in the channel and the depletion regions inside the source and drain into account, the model predicts the electrostatic potential of the homojunction device in all regions of the device operation more accurately, compared with the predictions of the previously reported models. The potential model is utilized for developing some models for important quantities in TFETs, such as lateral electric field, minimum tunneling length, and drain current. Owing to the physical and analytical nature of the developed models, one can pursue the influence of the transistor parameters on the electrical characteristics of DG-TFETs. To assess the accuracy of the proposed models, the results of the models are compared to those of the numerical simulations and found to be accurately predicting the simulation results for different device parameters. [ABSTRACT FROM AUTHOR]

In this paper, we give a physical insight into the diameter-dependent dominant leakage mechanisms in the nanowire junctionless (NWJL) FETs. Using calibrated 3-D simulations, we show that the off-state current in the NWJLFETs with nanowire diameter less than 10 nm is governed by the drain-induced barrier lowering and the consequent source-to-channel barrier height and barrier thinning, which controls the lateral band-to-band tunneling (L-BTBT)-induced parasitic bipolar junction transistor (BJT) action. Furthermore, the quantum confinement-induced bandgap enhancement is shown to lower the probability of L-BTBT, and hence acts as the dominant mechanism in reducing the off-state current of the NWJLFETs with sub-7 nm diameter. In addition, the hole accumulation due to L-BTBT induces a shielding effect, which results in an inefficient volume depletion, leading to a large off-state current in NWJLFETs with nanowire diameters >15 nm. Furthermore, the impact of gate sidewall spacer on the L-BTBT-induced parasitic BJT in NWJLFETs has also been investigated. [ABSTRACT FROM AUTHOR]

In this paper, we present a compact model for surface potential and drain current in transition metal dichalcogenide (TMD) channel material-based n-type and p-type FETs. The model considers 2-D density of states and Fermi–Dirac statistics along with drift-diffusion transport model and includes velocity saturation and trap state effects. The developed model has been implemented in Verilog-A and is applicable for symmetric double gate as well as top-gated TMD-on-insulator FETs. The presented model is extensively validated with simulation as well as experimental data for different TMD materials-based FETs and shows excellent agreement with both the simulation and the experimental data. We further validate the model at circuit level using experimental data of MoS2 FET-based inverter. [ABSTRACT FROM AUTHOR]

In this paper, we report anomalous behavior of transconductance ( gm ) in halo implanted MOSFET for linear and saturation regions across both gate and body biases. The gm characteristics undergo sharp change of slope in saturation which cannot be modeled by conventional compact models. The cause of such behavior is identified and explained using the TCAD simulations of source side halo, drain side halo (DH), both side halos, and uniformly doped transistors. An analytical model, based on the equivalent conductance of the halo device, is developed to understand the gm behavior. It is shown that the commonly used approach where only the DH region is considered in saturation, is insufficient to model the atypical gm behavior. The effect of oxide thickness ( T\text {ox} ) variation on gm is also studied, which demonstrates a deviation from the conventional gm behavior for halo implanted devices with thicker T\text {ox} . A computationally efficient SPICE model is proposed to model gm characteristics which shows excellent matching with the measured data. [ABSTRACT FROM PUBLISHER]

For the first time, a novel drain-extended tunnel FET (DeTFET) device is disclosed in this paper, while addressing the need for high-voltage/high-power devices for system-on-chip and automotive applications in beyond FinFET technology nodes. Operation of the proposed DeTFET device is presented with physics of band-to-band tunneling and associated carrier injection. Device’s intrinsic (dc/switching), analog, and RF performance is compared with the state-of-the-art drain-extended nMOS (DeNMOS) device. The proposed device for 11 V breakdown voltage offers $15\times $ better subthreshold slope, $8\times $ lower off-state leakage, $2\times $ higher ON current, and absence of channel length modulation and drain induced barrier lowering, while keeping $2.5\times $ lower threshold voltage. This results into significantly better ON resistance for a range of gate voltages, higher transconductance, orders of magnitude higher intrinsic transistor gain, and better RF characteristics, when compared with the DeNMOS device. Finally, device design guidelines are presented and scalability, without affecting breakdown voltage, of the proposed device is compared with the DeNMOS device. [ABSTRACT FROM PUBLISHER]

Amorphous ZnSnO ( a -ZnSnO) thin films were synthesized by a combustion solution method to fabricate thin-film phototransistors. The a -ZnSnO phototransistors are extremely sensitive to UV light, with evident photoelectric effect identified at various gate voltages. The UV sensitivity is rather high ( \sim 10^5 for the ratio of photocurrent to dark-current) at the off-state, while it is quite low ( \sim 10^1 ) at the on-state. The device behaviors can completely recover to the original state within 2000 s after switching off the UV light at both on- and off-states. We demonstrate that the UV behaviors of $a$ -ZnSnO phototransistors can be well controlled by gate voltages. This paper is expected to provide a fundamental knowledge of performances of amorphous oxide phototransistors for practical applications. [ABSTRACT FROM PUBLISHER]

An improved simulation scheme for investigating the performance of nanoscale FETs is developed in this paper. The total current of the MOSFET consists of two main components: thermionic current above the top of barrier of the channel calculated by ballistic approach and tunneling current computed by Wentzel–Kramer–Brillouoin approximation based on a full-complex-band structure. Furthermore, to get atomic-position-based potential profile in the nanoscale device, we self-consistently solve atomic charges and potentials in the real space along and transverse in the transport direction. The device performance calculated with this model shows excellent agreement with that obtained using non-equilibrium Green’s function solver (full quantum mechanism) but by using only one-tenth of the simulation resource. Moreover, special characteristics of insulating materials integrated with advanced device structures can also be incorporated in this Poisson solver. An example based on the negative capacitance MOSFET is examined with this model, and it shows significantly improved performance than conventional MOSFET. [ABSTRACT FROM PUBLISHER]

This paper presents an analytical model of drain current in a silicon tunnel FET with a circular gate (CG TFET). The method involves the bifurcation of the complete geometry into a rectangular gate conventional TFET, and the CG TFET itself based on the number of solvable regions of the CG TFET. The 2-D Poisson equation is solved on the regions of focus of each structure, and both the substructures are mathematically connected through conditions of continuity to arrive at the solution for the original geometry. The effect of the circular gate is considered by segregating the circular region into a number of rectangular segments, and solving the Poisson equation on each of them. The model takes into account the effect of drain on channel potential, bandgap narrowing, and quantum correction. The model is validated by comparing the results with outputs from a TCAD simulation tool. [ABSTRACT FROM PUBLISHER]

An optimization theory is developed for the balanced symmetric superjunction with the interface isolator layer (I-SJ) in this paper. The theory includes two parts: the electric field calculation by the Taylor series method; the design formulas by the minimum specific on-resistance R\mathrm{\scriptscriptstyle ON,\mathrm {min}} optimization. Based on the theory, a new I-SJ structure with a single cell is proposed, which shows the minimum $R_{{\mathrm{\scriptscriptstyle ON}}} among the superjunction (SJ) devices with the 1~\mu \textm shallow depths. R\mathrm{\scriptscriptstyle ON} of the new device is reduced by 53.5% compared with that of the conventional SJ lateral double diffused metal-oxide-semiconductor field effect transistor (LDMOS) and 67.6% with the conventional LDMOS under the same breakdown voltage VB of 658 V. [ABSTRACT FROM AUTHOR]

In this paper, we propose a double gate junctionless FET (DGJLFET) with an extended back gate (EBG) architecture for significantly improved performance in the sub-10-nm regime. Even for a channel length of 5 nm, we show using calibrated 2-D simulations that the EBG DGJLFET, when compared with the DGJLFET, exhibits: 1) an improved subthreshold swing; 2) a significantly low off-state leakage current; and 3) a considerably high I\mathrm{\scriptscriptstyle ON}/I{\mathrm{\scriptscriptstyle OFF}} ratio of \sim 10^8 . Furthermore, we demonstrate, for the first time, that the quantum confinement-induced bandgap widening diminishes the parasitic bipolar junction transistor (BJT) action and, therefore, facilitates the scaling of the conventional DGJLFETs to the sub-5-nm channel regime where the quantization effects are significant. Moreover, we also show, for the first time, that the DG junctionless accumulation mode FET suffers from an enhanced parasitic BJT action and, therefore, a significantly high off-state leakage current compared with the DGJLFET. In addition, we demonstrate that the loss of gate control for negative gate voltages in the DGJLFETs with larger silicon film doping ( ND \geq 2 \times 10^{19} cm ^-3 ) is due to a shielding effect initiated by the band-to-band tunneling. [ABSTRACT FROM AUTHOR]

GaSb/InAs heterojunction tunnel FETs are strong candidates in building future low-power ICs, as they could provide both steep subthreshold swing and large ON-state current ( I\mathrm{\scriptscriptstyle ON} ). However, at short-channel lengths, they suffer from large tunneling leakage originating from the small bandgap and small effective masses of the InAs channel. As proposed in this paper, this problem can be significantly mitigated by reducing the channel thickness, meanwhile retaining a thick source-channel tunnel junction, thus forming a design with a nonuniform body thickness. Because of the quantum confinement, the thin InAs channel offers a large bandgap and large effective masses, reducing the ambipolar and source-to-drain tunneling leakage at OFF-state. The thick GaSb/InAs tunnel junction, instead, offers a low tunnel barrier and small effective masses, allowing a large tunnel probability at ON-state. In addition, the confinement-induced band discontinuity enhances the tunnel electric field and creates a resonant state, further improving I\mathrm{\scriptscriptstyle ON} . Atomistic quantum transport simulations show that ballistic I\mathrm{\scriptscriptstyle ON}=284 A/m is obtained at 15-nm channel length, I\mathrm{\scriptscriptstyle OFF}=1\times 10^{-3} A/m, and V\mathrm{DD}=0.3 V, while with uniform body thickness, the largest achievable I\mathrm{\scriptscriptstyle ON} is only 25 A/m. Simulations also indicate that this design is scalable to sub-10-nm channel length. [ABSTRACT FROM AUTHOR]

In this paper, five projected tunnel FET (TFET) technologies are evaluated and compared with MOSFET and FinFET transistors for high-performance low-power objectives. The scope of this benchmarking exercise is broader than that of previous studies in that it seeks solutions to different identified limitations. The power and the energy of the technologies are evaluated and compared assuming given operating frequency targets. The results clearly show how the power/energy advantages of TFET devices are heavily dependent on required operating frequency, switching activity, and logic depth, suggesting that architectural aspects should be taken into account in benchmarking experiments. Two of the TFET technologies analyzed prove to be very promising for different operating frequency ranges and, therefore, for different application areas. [ABSTRACT FROM PUBLISHER]

In this paper, a junctionless FinFET (JLFinFET) having polycrystalline-silicon (poly-Si) channel has been optimally designed and characterized by stringent device simulation aiming 10-nm-and-beyond Si technology node. Replacing the silicon-on-insulator platform employed for realizing the JLFETs in most cases by bulk Si substrate featuring deposited oxide and poly-Si channel would warrant highly cost-effective process integration. Here, the high- $\kappa $ /metal-gate technology is also adopted to enhance the gate controllability, prevent the gate leakage current, and obtain appropriate gate work function. It is demonstrated from the device simulation results with higher accuracy and credibility by multiple models, particularly including the quantum-mechanical models in drift and diffusion conductions that the poly-Si JL FinFET has the strong potential for the 10-nm-and-beyond Si CMOS technology with little performance degradation in comparison with the JL FinFET with crystalline Si channel. [ABSTRACT FROM PUBLISHER]

In this paper, we show a validation of our compact model for negative capacitance FET (NCFET) presented in Part I. The model is thoroughly validated with the TCAD simulations with respect to ferroelectric thickness scaling and temperature effects. Interestingly, we find that an NCFET with PZT ferroelectric of a large thickness provides a negative output differential resistance in addition to an expected high ON current and a sub-60 mV/decade subthreshold swing. The model is also tested for the Gummel symmetry and its transient capabilities are highlighted through a ring oscillator circuit simulation. [ABSTRACT FROM PUBLISHER]

This part of the paper presents TCAD simulations of the InAs/Si lateral nanowire (NW) tunnel FET (TFET) with the same geometry as the fabricated device discussed in the first part. In addition to band-to-band tunneling, trap-assisted tunneling (TAT) at the InAs/Si and InAs/oxide interfaces was considered. A very good agreement is found between the simulation results and experimental transfer characteristics of different devices. The simulations confirm that the transfer characteristics in the subthreshold regime of the TFETs are entirely dominated by TAT. Due to the high concentration of generation centers at the InAs/Si interface, the current conduction in the subthreshold regime takes place in two steps: carrier generation by TAT at the InAs/Si interface followed by thermionic emission over the hole barrier. The latter is the limiting process, and hence dominant for the subthreshold swing (SS), preventing a value smaller than 60mV/decade. In addition, traps at the Si/oxide interface reduce the electrostatic coupling between the gate and the channel, which further degrades the SS. Predictive simulations with varying interface trap densities indicate that a subthermal SS would only be achievable for D\mathrm{ it} < 5\times 10^{11} cm ^-2 eV ^-1 at both InAs/Si and InAs/oxide interfaces. This confirms a recently found minimum requirement of D\mathrm{ it} < 1\times 10^{12} cm ^-2 eV ^-1 for vertical InAs/Si NW TFETs with larger diameters. [ABSTRACT FROM AUTHOR]

In this paper, the Pi-gate (PG) poly-Si junctionless (JL) and inversion mode (IM) FETs with a high aspect ratio (A.R. = channel thickness/channel width ~ 3.4) have been successfully fabricated and demonstrated by a method without using the costly lithography technique. This method has some advantages: 1) the thickness of channels can be controlled simply by thickness of poly-Si layer; 2) the shape of channels can be controlled effectively by rectangular silicon nitride (Si3N4) as hard masks; 3) the series resistance can be reduced by raised source/drain configurations; and 4) Si-compatible low thermal budget process. The PG poly-Si JL FETs show excellent electrical performance in terms of low gate overdrive voltage ( VG – V\mathrm{ TH} = 2 V), extremely near-ideal subthreshold swing (S.S.) ~68 mV/decade, steep average subthreshold swing (A.S.S.) ~ 73 mV/decade, smaller drain-induced barrier lowering ~9 mV/V, a higher ON/OFF current ratio \sim 1.1 \times 10^8 ( \textV\mathbf {D} = 1 V), and a better field-effect mobility ( \mu \mathrm{ FE}) \sim 35 (cm2/Vs) as compared with PG poly-Si IM FETs. Thus, these devices are very promising for future 3-D integrated circuits applications. [ABSTRACT FROM AUTHOR]

This paper provides an experimental proof that both the ON-current I\mathrm{\scriptscriptstyle ON} and the subthreshold swing SS of Si(Ge)-based tunneling FETs (TFETs) drastically benefit from device architectures promoting line tunneling aligned with the gate electrical field. A novel SiGe/Si heterostructure TFET is fabricated, making use of a selective and self-adjusted silicidation, thus enlarging the area for band-to-band-tunneling (BTBT) in a region directly underneath the gate. In addition, a counter-doped pocket within the SiGe layer at the source tunnel junction is introduced in order to sharpen the corresponding doping profile and, consequently, to shorten the resulting tunneling length. Experimental analysis of activation energies Ea identifies BTBT, dominating the drain current Id in the SiGe/Si heterostructure TFET over a wide region of the gate voltage Vg , thus reducing parasitic influence of Shockley–Read–Hall recombination and trap-assisted tunneling. Both a relatively high I\mathrm{\scriptscriptstyle ON} = 6.7\mu \text{A}/\mu \text{m} at a supply voltage V\mathrm{ DD} = 0.5 V and an average SS of about 80 mV/decade over four orders of magnitude of Id were achieved. [ABSTRACT FROM AUTHOR]

This paper reports a systematic methodology to enhance the performance of germanium p-type tunnel FETs (Ge-pTFETs) using a p+ pocket implant at the source end of the channel and an underlap region at the drain end. The numerical device simulation results show that an optimized drain-underlap region reduces the off-state leakage current ( I\mathrm{\scriptscriptstyle OFF}) of 50-nm Ge-pTFETs to about 3.27 pA/ \mu \textm without degrading the ON-current ( I\mathrm{\scriptscriptstyle ON}) , and a p+ pocket doping improves the ion of these devices to about 0.295 mA/ \mu \textm without compromising I\mathrm{\scriptscriptstyle OFF} . The analog and RF performances of the drain-underlapped Ge-pTFETs are investigated in terms of the drain current, transconductance, output resistance, intrinsic gain, cutoff frequency, and maximum frequency of oscillation for pocket-doping length varying from 0 to 6 nm. In addition, the influence of the pocket doping on the nonquasi-static performance is analyzed in terms of the gate–source and gate–drain capacitances, gate–drain resistance, and intrinsic delay time. Finally, the performance of the source-pocket drain-underlapped Ge-pTFETs in ICs is studied using a common source amplifier. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the nature of lateral band-to-band-tunneling (L-BTBT) component of gate-induced drain leakage (GIDL) in different nanowire junctionless FET (NWJLFET) configurations for the first time. Although the NW junctionless accumulation mode (JAM) FET has a larger ON-state current compared with the NWJLFETs, we demonstrate that the L-BTBT GIDL is larger in the NWJAMFET compared with the NWJLFET. Furthermore, we explore for the first time the application of a dual-material gate (DMG) in the NWJAMFET to suppress the L-BTBT GIDL. Using calibrated 3-D simulations, we show that the OFF-state current in the DMG NWJAMFET is reduced significantly by six orders of magnitude leading to a considerable ON-state to OFF-state current ratio ( $I/I_{{\mathrm{\scriptscriptstyle OFF}}})$ of \sim 10^{10} . Furthermore, the DMG NWJAMFET offers: 1) an enhanced ON-state current and 2) a significantly reduced OFF-state current compared with the NWJLFETs. Furthermore, we also demonstrate that the DMG NWJAMFET exhibits a higher transconductance than the single material gate NWJAMFET in the saturation region. In addition, we also show that there is a tradeoff between the off-state current and the intrinsic delay and the cut-off frequency in the DMG NWJAMFET. Therefore, we provide the design guidelines for appropriately choosing the work functions of the dual gates and the ratio of the length of the dual gates to the total gate length. [ABSTRACT FROM PUBLISHER]

Spintronics is the exploitation of both the degree of freedom of electron that is spin as well as the charge, which leads to tremendous development in the field of microelectronic applications. In this paper, bimetallic Co–Ni-based spin FET device is fabricated, and its magnetoresistance behavior has been studied. While, spin current as a function of thickness of Co–Ni-based concatenable spin switch has been studied. The results obtained for spin current using simulation and experimentation show good agreement. [ABSTRACT FROM PUBLISHER]

Bulk FinFET is the main technology option for sub-20-nm CMOS nodes. However, newly introduced process options in advanced bulk FinFET technologies can result in significant deterioration of intrinsic electrostatic discharge (ESD) performance. In this paper, the impact on ESD performance induced by the process options beyond 20-nm nodes is explored on the ESD protection diodes. [ABSTRACT FROM AUTHOR]

In this paper, we investigate a graphene nanoribbon FET (GNRFET) with locally embedded Stone–Wales (SW) defects near its drain contact. The simulation procedure is preformed via the self-consistent solution of the full 3-D Schrödinger and Poisson equations. Localized states induced by the SW defects are able to reduce ambipolar conduction and provide higher ON–OFF ratio and attenuated kink effect. Causing outgoing carriers decelerated in the channel, the use of such defected region in the GNRFET yields less vulnerability to hot-carrier degradation than its conventional counterpart. Our proposed structure also enhances the device transconductance, making it more appealing in high-frequency applications. [ABSTRACT FROM AUTHOR]

Several emerging devices have been proposed to continue the CMOS scaling. To assess scalability, device and circuit variability estimation is essential. Variability in static noise margin (SNM) in a 6T-SRAM cell is a key metric to assess the impact of device-level variability at the circuit level. This is usually enabled by SPICE simulations, which needs device compact models. However, the development of a SPICE model usually takes a significant amount of time (e.g., a few years). In this paper, we present a method to enable the evaluation of the SRAM cell SNM variability based on the ID – VG distribution at various V\mathrm{ DS} values of a device (obtained either experimentally or from TCAD), which can enable this assessment before the development of a SPICE model. Thus, it enhances the accuracy by being able to capture the effects of full ID – VG distribution rather than just VT distribution. The method is validated against HSPICE for a variety of SRAM parameters, such as Read, Hold, and Write SNM, write trip point, and read current ( I\mathrm{ READ} ) to show excellent accuracy. The method also shows a $30\times $ improvement in computational efficiency over mixed-mode TCAD-based stochastic SRAM simulation. A case study for the comparison of recently proposed low-variability EDFinFET with FinFET is presented using this method. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, we developed an analytical model for the surface potential of the double-gate p-n-p-n tunneling field-effect transistors (TFETs) considering the effect of localized charges at the Si-SiO2 interface near the source-channel junction. From the surface potential model, the minimum tunneling width is then evaluated and is used to extract the threshold voltage using the constant-current method. The model can be applied to study the effect of localized charges on the threshold voltage of the p-n-p-n TFETs as it captures the shift in the threshold voltage due to the change in the localized charge region length, localized charge density, and polarity. The accuracy of the proposed model is verified using 2-D Technology Computer-Aided Design simulations. [ABSTRACT FROM AUTHOR]

In this paper, we propose the use of a p+ core in the core–shell nanowire (CS NW) architecture to significantly reduce the gate induced drain leakage and therefore, increase the ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) in n-NW junctionless FETs (NWJLFETs). We show that the lateral band-to-band tunneling induced parasitic bipolar junction transistor action is diminished in the CSJLFET due to an enhanced tunneling width and a higher source to channel barrier height. Further, we also demonstrate that the p+ core helps to realize efficient volume depletion in NWJLFETs with large NW width. Using calibrated 3-D simulations, we show that the CSJLFET exhibits a significantly high ON-state to OFF-state current ratio ( $I_{{\mathrm{\scriptscriptstyle ON}}}/I_{{\mathrm{\scriptscriptstyle OFF}}}$ ) of \sim 10^{7} even for a channel length of 7 nm. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse ID – VG technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated. [ABSTRACT FROM AUTHOR]

A compact 2-D analytical model for electrical characteristics such as surface potential, drain current, and threshold voltage of double-gate tunnel FET (DG TFETs) with a SiO2/High- k stacked gate-oxide structure is proposed in this paper. Poisson’s equation has been solved using parabolic approximation method to model the channel potential. The band-to-band tunneling generation rate has been expressed as a function of channel electric field derived from the channel potential and then integrated analytically over the channel thickness to derive the drain current of the stacked-gate DG TFETs using the shortest tunneling path (Lt^{\min } ) concept. The effect of source/drain depletion regions has been included for the better accuracy of the proposed model. The maximum transconductance method has finally been used to extract the threshold voltage from the drain current of the device. The effects of various device parameters on the channel potential, drain current, and threshold voltage have been investigated. The model results have been compared with the simulation data obtained using the commercially available ATLAS 2-D device simulator from SILVACO for the validity of the proposed model. [ABSTRACT FROM PUBLISHER]

In this paper, we investigate the optimization of device layout and embedded source/drain (eS/D) shape profile for strain engineered 22-nm node Si and SiGe p-channel trigate field-effect transistors by finite-element method simulations. A nested trigate layout with dummy gates is found to retain the maximum channel stress for all three conduction planes. The tradeoff between achievable mobility enhancement and active device density for the nested trigate layout is also investigated in this paper. Next, the impact of the eS/D shape on the channel stress for all three conduction planes is studied, and the rounded eS/D shape is found to be the optimal shape contrary to the planar case with sigma-shaped eS/D. Finally, strained SiGe channel trigate transistors are investigated as a potential candidate for future technology nodes. The evolution of formation and relaxation of the average strain of the compressively strained SiGe channel is systematically studied as a function of fin formation, embedded S/D formation, and layout configuration. [ABSTRACT FROM PUBLISHER]

It is recognized that the conventional model for metal–ferroelectric–insulator–semiconductor field-effect transistors (MFIS-FETs) always neglects the history-dependent electric field effect of the ferroelectric layer. In this paper, an improved model combining the dipole switching theory with the silicon physics of metal–oxide–semiconductor structures and with Pao and Sah's double integral, respectively, is proposed to describe the capacitance–gate voltage (C –VG) characteristics of MFIS structures and the drain current–gate voltage (ID– VGS) and drain current–drain voltage ( ID–VDS) characteristics of MFIS-FETs. Close agreement between modeling and experimental results confirms the validity of the improved model. The influence of the gate voltage, \SiO2 layer thickness, and interface layer thickness on the C–VG, ID–VGS, and ID–VDS characteristics are simulated and discussed. The memory windows of C–VG and ID–VGS characteristics, as well as the ID –VDS characteristics, increase with increasing gate voltage. The thicker the \SiO2 or interface layer, the worse the transistor characteristics. This paper is expected to provide some guidance to the design and performance improvement of MFIS structure devices. In addition, the mathematical description can be easily combined with electronic design automation software for circuit simulation. [ABSTRACT FROM AUTHOR]

This paper presents the evaluation of the analog properties of nMOS junctionless (JL) multigate transistors, comparing their performance with those exhibited by inversion-mode (IM) trigate devices of similar dimensions. The study has been performed for devices operating in saturation as single-transistor amplifiers, and we have considered the dependence of the analog properties on fin width Wfin and temperature T. Furthermore, this paper aims at providing a physical insight into the analog parameters of JL transistors. For that, in addition to device characterization, 3-D device simulations were performed. It is shown that, depending on gate voltage, JL devices can present both larger Early voltage VEA and larger intrinsic voltage gain AV than IM devices of similar dimensions. In addition, VEA and AV are always improved in JL devices when the temperature is increased, whereas they present a maximum value around room temperature for IM transistors. [ABSTRACT FROM AUTHOR]

Aggressive transistor scaling affects the threshold voltage Vth in two ways: space and time. Transistors on the same die can have different Vth due to random dopant fluctuations (RDFs). On the other hand, Vth of a specific transistor can randomly shift in time due to random position of dangling bonds and random motion of atomic H or \H2 molecules in the oxide [negative bias temperature instability (NBTI)]. These two random effects are not totally independent because the dissociation rate of Si–H bonds at the silicon–oxide interface depends on the nonuniform electric field. In this paper, we describe the combined effect of RDF and NBTI on Vth using stochastic differential equation. In this paper, we are able to examine the effect of RDF on critical NBTI parameters such as kf, kr, and temperature and the correlation among these parameters. The efficacy of the proposed model is evaluated by performing Monte Carlo simulations on various transistors under different direct-current stress and obtained distributions for NIT and Vth. [ABSTRACT FROM PUBLISHER]

This paper presents a hybrid resonator architecture called the vibrating body field-effect transistor (VB-FET), which combines a silicon microelectromechanical (MEM) resonator and a FET in a single device. The active device provides improved motion sensing at the mechanical resonance based on charge- and/or piezoresistive-drain-current modulations. We detail the principles of the VB-FET for a clamped-clamped-beam resonator design. The different transduction mechanisms occurring in this structure are discussed, and the benefit of the FET detection with respect to the capacitive transduction in terms of reduced motional resistance is highlighted. The experimental characteristics of the resulting devices are detailed, including a full scattering-parameter characterization and temperature characterizations. An increase in the signal transmission by more than +30 dB over the conventional capacitive transduction is demonstrated under equivalent biasing conditions at 2 MHz. Intrinsic signal amplification in a hybrid MEM resonator is another unique property of active resonators demonstrated in this paper for VB-FET resonators. [ABSTRACT FROM AUTHOR]

A comprehensive study, which is presented in two parts, is performed to assess the radio-frequency (RF) performance potential of array-based carbon-nanotube field-effect transistors (CNFETs). In Part I, which is presented in this paper, the time-dependent Boltzmann transport equation is solved self-consistently with the Poisson equation to study the impact of nanotube phonon scattering on different aspects of intrinsic (single-tube, contact-independent) CNFET operation, including the attainable drive current and transconductance per tube, the intrinsic cutoff frequency, the intrinsic y-parameters, and the small-signal equivalent circuit for the intrinsic transistor. These intrinsic results are used to assess the tube-to-tube distance (pitch) that would be required in a multitube array-based structure to meet the drive current and transconductance requirements of the International Technology Roadmap for Semiconductors for the year 2015, which we use as a benchmark for CNFET technology going forward. In Part II of our paper, we elaborate on the results of Part I by adding the effects of extrinsic (contact-dependent) parasitics, thus providing an overall performance assessment of array-based structures. [ABSTRACT FROM AUTHOR]

This paper presents the optimization of double-gate silicon (Si) tunnel field-effect transistors (TFETs). It shows that, for the heterodielectric structure, the ION current is boosted by correctly positioning the source with respect to the gate edge. The second booster used in this paper is the Si thickness that is tuned in order to maximize the ION current. The effects that lead to the performance increase are explained on a physical basis. We also demonstrate that the ambipolar character of the TFET is completely inhibited by using only one spacer of 30-nm length to separate the drain and the gate. [ABSTRACT FROM PUBLISHER]

This paper investigates the cell stability of recently introduced four-transistor (4T) and conventional six-transistor (6T) fin-shaped field-effect transistor static random access memory (SRAM) cells operating in a subthreshold region using an efficient model-based approach to consider the impact of device variations. Compared with the 6T cell, this paper indicates that 4T SRAM cells exhibit a better nominal read static noise margin (RSNM) because of the reduced read disturb. For 4T cells, the nearly ideal values of Vwrite, 0 and Vwrite, 1 guarantee the positive nominal write static noise margin (WSNM) for selected cells. For half-selected cells on the selected bit line, a sufficient margin is observed between write time (for selected cells) and write disturb (for half-selected cells). Using the established model-based approach, the variability of subthreshold 6T and 4T SRAM cells is assessed with 1000 samples. Our results indicate that the 4T driverless cell with a larger \mu\RSNM and a slightly worse \sigma\RSNM shows a comparable \mu/\sigma ratio in RSNM with the 6T cell. Furthermore, for a given cell area, 4T SRAM cells using relaxed device dimensions with reduced \sigma\RSNM can outperform the 6T cell. For write operation, 4T SRAM cells exhibit a superior WSNM, whereas the design margin between write time and write disturb needs to be carefully examined to ensure an adequate margin considering device variability. [ABSTRACT FROM PUBLISHER]

This paper analyzes the impacts of intrinsic process variations and negative bias temperature instability (NBTI)/positive BTI (PBTI)-induced time-dependent variations on the stability/variability of 6T FinFET static random access memory (SRAM) cells with various surface orientations and gate dielectrics. Due to quantum confinement, (110)-oriented pull-down n-channel FETs with fin line-edge roughness (LER) show larger Vread,0 and Vtrip variations, thus degrading read static noise margin (RSNM) and its variability. Pull-up p-channel FETs with fin LER that are (100)-oriented show larger Vwrite,0 and Vtrip variations, hence degrade the variability of write SNM. The combined effects of intrinsic process variations and NBTI/PBTI-induced statistical variations have been examined to optimize the FinFET SRAM cells. Worst-case stress scenario for SNM stability/variability is analyzed. With the presence of both NBTI and PBTI in high-k metal-gate FinFET SRAM, the RSNM suffers significant degradation as Vread,0 increases, whereas Vtrip simultaneously decreases. Variability comparisons for FinFET SRAM cells with different gate stacks (\SiO2 and \SiO2/\HfO2) are also examined. Our paper indicates that the consideration of NBTI/PBTI-induced temporal variation changes the optimal choice of FinFET SRAM cell surface orientations in terms of the \mu/\sigma ratio in RSNM. [ABSTRACT FROM PUBLISHER]

The discussion section of paper “1.88-\m\Omega \cdot \cm^2 1650-V Normally on 4H-SiC TI-VJFET” which appeared in IEEE Transactions on Electron Devices, vol. 55, no. 8, August 2008, offers a comparative analysis between TI-VJFETs fabricated at USCI/Rutgers and VJFETs (SITs) fabricated at Northrop Grumman Electronic Systems (NGES) for power switching applications. I have a number of issues with this analysis which I wish to highlight. In addition, this paper claims VJFET performance records, which are dubious as they are based on on-resistance values obtained under bipolar operation and on blocking-voltages quoted at unspecified drain-current densities. [ABSTRACT FROM PUBLISHER]

In this paper, we study the impact of surface roughness and its combination with random discrete dopants on the current variability in nanometer-scale nanowire metal-oxide-semiconductor field-effect transistors. It is shown that these two variability sources cannot be regarded as independent in their effect on transport. Interface roughness results in body thickness fluctuations and scattering, which degrades transistor performance. This paper extends our previous study, in which we concentrated only on the impact of random discrete dopants in the source/drain regions in the same type of devices that lead to current variability. We have simulated ensembles of 30 devices, which differ due to the physical manifestation of the variability sources, including the detailed microscopic pattern of the interface in the channel and the number and configuration of discrete dopants in the source/drain regions. An ensemble of devices, with rough interfaces and continuous doping, has first been simulated to differentiate the effect of the interface roughness from the random discrete dopants before considering the combined case. It was found that, in some peculiar cases, the surface roughness induced resonant structures inside the device, producing quasi-bound states. These resonant states are similar to those related to individual discrete dopants in our previous study. We found that there is strong correlation between the microscopic patterns of the interface and the device performance due to the non-self-averaging of the microscopic features, which plagues devices with small channel lengths. The surface roughness induces a threshold voltage shift and decreases the ON-current of the device due to scattering. In the fully 3-D nonequilibrium Green's function formalism, both effects are combined in the propagation of the electron wave through the device. We have extracted the surface roughness related scattering contribution and estimated the associated mobility. [ABSTRACT FROM AUTHOR]

This paper provides more insight into the operation of the Charge Sheet Superjunction (CSSJ) proposed recently, whose specific on-resistance for a given breakdown voltage is even lower than that of a Superjunction (SJ). It is shown how the SJ and the CSSJ both evolve from a simple Γ-shaped p+ -n junction in which the heavily doped region surrounds the lightly doped region; the peak field in such a 2-D junction is less than that in a plane junction. The phenomena underlying the I-V and C-V characteristics of the CSSJ MOSFET are clarified with the help of charge and potential simulations. A simple analytical model is developed for the drain-source capacitance of the CSSJ MOSFET; the model is shown to apply to SJ MOSFET as well. It is argued that the insulator charges providing the charge sheet essential for CSSJ operation will not present the same reliability problems as those due to trapped charge in the gate insulator of small-signal MOSFETs; this is because the insulator field distribution in a CSSJ differs significantly from that in a small-signal MOSFET. The insight provided in this paper should build a strong motivation for the practical implementation of the new structure. [ABSTRACT FROM AUTHOR]

In this paper, we investigate quasi-ballistic transport in nanowire field-effect transistors (NW-FETs). In order to do so, we address the 1-D Boltzmann transport equation (BTE) and find its exact analytical solution for any potential profile with the constraint of dominant elastic scattering. A simulation code implementing a self-consistent Schrödinger-Poisson solver in the transverse direction and the present BTE solution in the longitudinal direction is worked out, providing the I-V characteristics of the NW-FET. Such characteristics are compared with those computed using a numerical BTE solver accounting for both inelastic and elastic collisions, and the two of them turn out to agree very nicely. From this comparison, it may be concluded that inelastic scattering plays a minor role for small-diameter FETs with device lengths in the decananometer range. Next, a methodology for the calculation of the transmission and backscattering coefficients is worked out for the first time starting from the scattering probabilities. The aforementioned coefficients turn out to be functions of the ratio between the carrier transit time and a suitably averaged momentum-relaxation time. Therefore, one of the main conclusions of this paper is that, so long as inelastic collisions are negligible, the so-called kT layer plays no role in 1-D quasi-ballistic carrier transport. [ABSTRACT FROM AUTHOR]

Recently, we proposed and experimentally demonstrated a very simply structured unipolar accumulation-type field-effect transistor (FET) using silicon nanowires (NWs). In this paper, we present an extensive numerical study of this accumulation metal-oxide-semiconductor FET (AMOSFET). This single-doping-type ohmically contacted structure relies on having a nanoscale dimension normal to the gate, thereby forcing the current path through an accumulated (ON-state) or depleted (OFF-state) region. It also relies on having contact-barrier and doping-dependent minimum source and drain lengths as well as minimum gate lengths to insure unipolar transistor action. The comprehensive report presented extends our previous examination of the device's operation by using extensive numerical simulations to offer a greater understanding of the origins of transistor operation. We explore a wide range of structural and material parameters to study their effects on the linear, saturation, and OFF-state currents. We also delve deeper into the uniquely weak dependence on gate capacitance. This paper establishes that this extremely simple accumulation-mode transistor structure offers its best performance for the more highly doped thinnest devices, giving, for example, for a 1017-cm-3 (doping) and 20-nm device a leakage current of ∼10-17 A/μm, a subthreshold swing of 65 mV/dec, and an on-off ratio approximately 1010. This paper also shows that such results should be attainable for AMOSFETs fabricated using NWs and nanoribbons, as well as nanoscale thin-film materials. [ABSTRACT FROM AUTHOR]

Part I of this paper dealt with the simulation study, using ATLAS 2D, of analog-circuit performance metrics for the dual-material-gate (DMG) silicon-on-nothing (SON) MOSFET. It was reported that, out of the several combinations in the DMG design studied, the DMG device with LM1 /L ratio as 1/2 amalga- mates the advantages of using a high metal work-function gate M1 and low metal work-function gate M2 in the most efficient manner. This paper focuses upon the effect of double-layer gate stack (DGS) (high.k/SiO2) on the single-material-gate (SMG) SON and the DMG SON MOSFETs. Improved Early voltage and reduced output conductance of the DMG SON MOSFETs are the driving forces behind the observed increase in intrinsic gain and fT-gain relationship for the DMG devices over SMG SON MOSFETs, with the DMG SON MOSFETs having LM1 /L ratio as 1/2, proving to be the best choice among various LM1/L ratios studied. A further improvement in intrinsic gain in DMG DGS SON MOSFETs comes about because of increased gate control on the channel, thus establishing design guidelines aiming at higher gain and better fT-gain relationship. [ABSTRACT FROM AUTHOR]

Part I of this paper dealt with the simulation study, using ATLAS 2D, of analog-circuit performance metrics for the dual-material-gate (DMG) silicon-on-nothing (SON) MOSFET. It was reported that, out of the several combinations in the DMG design studied, the DMG device with LM1/L ratio as 1/2 amalgamates the advantages of using a high metal work-function gate Ml and low metal work-function gate M2 in the most efficient manner. This paper focuses upon the effect of double-layer gate stack (DGS) (high-k/SiO2) on the single-material-gate (SMG) SON and the DMG SON MOSFETs. Improved Early voltage and reduced output conductance of the DMG SON MOSFETs are the driving forces behind the observed increase in intrinsic gain and fT-gain relationship for the DMG devices over SMG SON MOSFETs, with the DMG SON MOSFETs having LM1/L ratio as 1/2, proving to be the best choice among various LM1/L ratios studied. A further improvement in intrinsic gain in DMG DGS SON MOSFETs comes about because of increased gate control on the channel, thus establishing design guidelines aiming at higher gain and better fT-gain relationship. [ABSTRACT FROM AUTHOR]