Search

Negative capacitance FETs (NCFETs) have attracted significant interest due to their steep-switching capability at a low voltage and the associated benefits for implementing energy-efficient Boolean logic. While most existing works aim to avoid the ID – VG hysteresis in NCFETs, this paper exploits this hysteresis feature for logic-memory synergy and presents a custom-designed nonvolatile NCFET D flip-flop (DFF) that maintains its state during power outages. This paper also presents an NCFET fabricated for this purpose, showing <10 mV/decade steep hysteresisedges and high, up to seven orders inmagnitude, R\text {DS} ratio between the two polarization states. With a device-circuit codesign that takes advantage of the embedded nonvolatility and the high R\text {DS} ratio, the proposed DFF consumes negligible static current in backup and restore operations, and remains robust even with significant global and local ferroelectric material variations across a wide 0.3–0.8 V supply voltage range. Therefore, the proposed DFF achieves energy-efficient and low-latency backup and restore operations. Furthermore, it has an ultralow energy-delay overhead, below 2.1% in normal operations, and operates using the same voltage supply as the Boolean logic elements with which it connects. This promises energy-efficient nonvolatile computing in energy-harvesting and power-gating applications. [ABSTRACT FROM PUBLISHER]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

Silicon carbide (SiC) has shown substantial promise in the fabrication of high-power devices, and SiC Schottky diodes and field-effect transistors (FETs) have been considered as potential candidates for outerspace and sensors applications. Due to the multipolar structure, SiC gate turn-off thyristor (GTO) device is relatively sensitive to the irradiation-induced point defects. However, how SiC GTO devices perform under neutron irradiation still needs to be clarified. In this paper, the effects of neutron irradiation on the static and dynamic switch characteristics of high-voltage 4H-SiC GTOs are investigated for the first time. For the static electrical properties, it is found that the forward current significantly decreases with the increasing neutron irradiation fluence. While the cathode leakage current in the blocking characteristics shows an insignificant change up to a neutron fluence of ${1.0} \times {10}^{{13}}$ n/cm2. For the switching characteristics, both the pulse peak current and di/dt show substantial reduction as the neutron fluence increases while the delay time increases after irradiation. The degraded performance of the static and dynamic characteristics of SiC GTO devices was then analyzed and attributed to the weakened conductivity modulation and reduced carrier injection efficiency into the drift layer. These two aspects originate from the significantly reduced carrier lifetime and deteriorated forward characteristics of anode-gate diodes, respectively. [ABSTRACT FROM AUTHOR]

In this paper, the transition rate (TR) from the high-resistance state to the low-resistance state of a HfO2-based resistive random access memory (RRAM) is investigated. The TR is statistically characterized by applying constant voltage stresses in the range from 0.45 to 0.65 V. It is found that TR follows a voltage dependence which closely resembles the one exhibited by metal-insulator-semiconductor / metal-insulator-metal structures when subjected to constant voltage stress, but with remarkably different fitting parameters. This result suggests a common underlying mechanism in both evolutionary behaviors. Furthermore, the investigation provides additional evidence supporting the micro-structural changes in the oxide after the forming step as well as the role played by the atomic species during the SET event. [ABSTRACT FROM AUTHOR]

A p-type shield region (p-shield) under the gate trench is typically adopted in a SiC trench MOSFET for achieving a lower oxide field and reverse transfer capacitance ( Crss) . This paper comparatively studies the effects of a grounded p-shield and a floating p-shield. Device simulations using Sentaurus TCAD are carried out in this paper to reveal the devices’ internal dynamics. The floating p-shield can effectively reduce the OFF-state oxide field as a grounded p-shield does, without degrading its static performance. However, after being switched from the OFF-state, the ON-state oxide field in the trench MOSFET with a floating p-shield (FS-MOS) is dramatically elevated. Compared with the trench MOSFET with a grounded p-shield, the FS-MOS also exhibits a higher C{{\text {rss}}} and a consequently slower switching speed. Furthermore, the FS-MOS exhibits a degradation of dynamic R{ \mathrm{ON}} during switching operation. A charge storage mechanism is then presented to explain the dynamics in FS-MOS. Upon a high V{{\text {DS}}} , holes are emitted from the floating p-shield when the parasitic p-n-p structure consisting of p-shield, p-body, and n-region between them is punched through, leaving negative charges in the floating p-shield even when the high V{{\text {DS}}} is removed. Based on this mechanism, the behaviors of the FS-MOS are well explained. [ABSTRACT FROM AUTHOR]

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section (${A} _{\textsf {cross}}$) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance. [ABSTRACT FROM AUTHOR]

In this paper, an improved 4H-SiC U-shaped trench-gate metal–oxide–semiconductor field-effect transistors (UMOSFETs) structure with low ON-resistance (${R}_{ \mathrm{\scriptscriptstyle ON}}$) and switching energy loss is proposed. The novel structure features an added n-type region, which reduces ON-resistance of the device significantly while maintaining the breakdown voltage (${V}_{\textsf {BR}}$). In addition, the gate of the improved structure is designed as a p-n junction to reduce the switching energy loss. Simulations by Sentaurus TCAD are carried out to reveal the working mechanism of this improved structure. For the static performance, the ON-resistance and the figure of merit (FOM $= {V}_{\textsf {BR}}^{\textsf {2}}/{R}_{ \mathrm{\scriptscriptstyle ON}}$) of the optimized structure are improved by 40% and 44%, respectively, as compared to a conventional trench MOSFET without the added n-type region and modified gate. For the dynamic performance, the turn-on time (${T}_{ \mathrm{\scriptscriptstyle ON}}$) and turn-off time (${T}_{ \mathrm{\scriptscriptstyle OFF}}$) of the proposed structure are both shorter than that of the conventional structure, bringing a 43% and 30% reduction in turn-on energy loss and total switching energy loss (${E}_{\mathbf {SW}}$). [ABSTRACT FROM AUTHOR]

The reverse-conducting insulated gate bipolar transistor (RC-IGBT) has several benefits over a separate IGBT and diode solution and has the potential to become the dominant device within many power electronic applications; including, but not limited to, motor control, resonant converters, and switch-mode power supplies. However, the device inherently suffers from many undesirable design tradeoffs which have prevented its widespread use. One of the most critical issues is the snapback seen in the forward conduction characteristic which can prevent full turn-on of the device and result in the device becoming unsuitable for parallel operation (required in many high voltage modules). This phenomenon can be suppressed but at the expense of the reverse conduction performance. This paper provides an overview of the technical design challenges presented by the RC-IGBT structure and reviews alternative device concepts which have been proposed in literature. Analysis shows that these alternate concepts either present a tradeoff in performance characteristics, an inability to be manufactured, or a requirement for a custom gate drive. [ABSTRACT FROM AUTHOR]

Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator (SOI) FBFET with extremely steep switching (~1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. The prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail. [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel technique of realizing discrete-time (D-T) signal amplification using Nano-Electro-Mechanical systems (NEMS). The amplifier uses mechanical switches instead of traditional solid-state devices and acts as an inherent sample and hold amplifier. The proposed NEMS D-T amplifier operates on a wide dynamic range of signals without consuming the dc power. Moreover, the proposed amplifier does not suffer from the leakage current and the nonlinearity associated with the sampling ohmic switch. As a proof of concept, the proposed NEMS D-T amplifier is demonstrated in circuit simulations using the calibrated verilog-A models of the NEMS device. The simulated amplifier achieves a gain of ~5, handles the maximum differential input signal of 0.65 V, and consumes only $0.6~\mu \text{W}$ of power for a sampling frequency of 100 kHz. The nonidealities present in the proposed amplifier are highlighted and possible ways to overcome them are discussed. Finally, the design considerations required for the NEMS D-T amplifier are described. [ABSTRACT FROM AUTHOR]

In the quest for novel, scalable and energy-efficient computing technologies, spin-based logic devices are being extensively explored due to their potential for nonvolatility, small cell area, and low operational power. Spin torque majority gate (STMG) is one of the most promising options for beyond CMOS nonvolatile logic circuits for normally-off computing. However, significant problems arose with cascade-ability, signal nonreciprocity, and complicated circuit configurations based on STMG. In this paper, a novel magnetic majority gate (MMG) logic has been proposed, utilizing both spin transfer torque and spin–orbit torque effects. A logic family including and/nand and or/nor functions can be achieved with an easy configuration and under a stable operation. Communication between logic units is realized by spin current injection through a nonferromagnetic metal wire to ensure its cascade-ability and nonreciprocity to design multiple logic-depth circuits. With all of these advantages, the proposed cascadable MMGs can be utilized to design logic functions such as the BUFFER/ NOT, XOR/ XNOR, and complicated logic gates, which pave the pathway for designing robust and comprehensive logic circuits using full spintronic devices. [ABSTRACT FROM AUTHOR]

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of switching performances between the in-situ oxide, gallium nitride (GaN) interlayer FET (OG-FET) and the conventional GaN metal–oxide–semiconductor FET (MOSFET), and explores the influence of the channel electron mobility on the device switching performance. GaN OG-FET is a novel structure with a pristine GaN layer grown between the gate oxide and the p-GaN enhancing the channel mobility up to 185 cm2/ $\text {V}\cdot \text {s}$ , which is over $3{\times}$ larger than that of the typical reported value (50 cm2/ $\text {V}\cdot \text {s}$) in GaN MOSFET. Owing to the high channel electron mobility, the GaN OG-FET showed a switching loss 30% lower than that of the conventional GaN trench MOSFET. Our results indicate that GaN OG-FET has the potential to attain greater efficiency, particularly at higher frequencies, showing a possible patch toward megahertz range conversions. [ABSTRACT FROM AUTHOR]

When developing silicon carbide (SiC) devices, the reliability of the internal body diode is an important issue. Stacking faults (SFs) are expanded from basal plane defects by using a body diode. Although it is well known that ON-voltage degradation occurs due to SFs, their effects on dynamic reliability have not been studied well. Furthermore, including the effects of SFs, there are not many reports about the dynamic reliability of SiC-MOSFETs. In this paper, a double-pulse switching test using 3.3-kV SiC-MOSFETs was carried out to clarify the failure mechanism of the switching operation of SiC-MOSFETs and effects of SFs on the safe operation area (SOA). Before the switching test, current stress was applied to the body diode of the devices under test (DUTs) to expand the SFs. The circuit configuration was half-bridge type, and a double-pulse gate signal was applied to the lower arm DUT. The switching voltage was 1.8 kV, and the switching current increased at about 8-A steps to failure. As a result, reverse recovery SOA (RRSOA) reliability decreased depending on the amount of SFs in the SiC-MOSFET. Because RRSOA failure was caused by avalanche due to the hole concentration during reverse recovery and the SFs raised local current density, reverse bias SOA (RBSOA) hardly decreased even if SFs containing SiC-MOSFETs were used. This is because RBSOA failure was caused by degradation of the gate isolation layer due to overheating and the temperature coefficient of the SFs electric resistance indicated negative. [ABSTRACT FROM AUTHOR]

This paper reports on the suppression of single-transistor latch, an extreme condition of impact ionization (I.I.), in n-type double-gate germanium (Ge) junctionless (JL) transistors. It is shown that JL transistors can be latched to the on-state due to an increase in the I.I. generated power per unit volume with an increase in drain bias, film thickness, oxide thickness, and doping. Latch, being detrimental to switching, can be effectively suppressed by applying an appropriate negative (positive) back-gate bias for n-type (p-type) JL MOSFET. The independent gate operation with appropriate back bias allows the device to overcome latching and regain switching action with a subthreshold swing (${S}$ -swing) <10 mV/decade at room temperature. The work showcases the limit imposed on back bias due to an increase in off-state current due to band-to-band tunneling along with the utility of sidewall spacer to effectively suppress the same. We also show the tunability of hysteresis using back-gate bias. The work highlights a systematic methodology to eliminate single-transistor latch while preserving sub-60 mV/decade switching in Ge JL MOSFETs. [ABSTRACT FROM AUTHOR]

Power consumption of today’s integrated circuit is very difficult to reduce because the MOSFET is subjected to the thermal limit of 60 mV/decade for the subthreshold swing (SS). In this paper, we show that this SS limit of thermionic current can be conquered—thus power consumption drastically reduced by density of states (DOS) engineering at the source. Specifically, the linear DOS of Dirac electrons at the source concomitant with an efficient gate control brings the SS limit down to 37 mV/decade, and further down to very small values by suppressing the thermal tail contribution with a small bandgap in the injected DOS. Using the first principles analysis, we demonstrate that FETs with Dirac source to possess extremely promising device performance in both energy dynamic power and switching speed at the ultralow operating voltage regime of 0.3 V compared with ultrathin-body Si FETs. [ABSTRACT FROM AUTHOR]

This paper reports the significance of device architecture to enhance impact ionization (I.I.) resulting in steep increase in the current from OFF- to ON-state. Recognizing that the area over which I.I. occurs is a key factor governing impact generated power per unit volume in the semiconductor film, we use raised source/drain (RSD) architecture to achieve sub-60-mV/decade subthreshold swing (S-swing) in germanium (Ge) junctionless (JL) devices at drain bias ( ${V}_{\text {ds}}$ ) of 0.9 V. The performance of RSD Ge JL device is compared with double-gate Ge JL transistor to highlight the occurrence of subthermal S-swing <5 mV/decade in RSD topology. The impact of band-to-band tunneling (BTBT) on the switching characteristics shows that RSD JL device with relatively thicker side oxide can effectively suppress BTBT while enhancing I.I. The influence of parasitic capacitance due to RSD regions and vertical doping gradient is also analyzed. Results highlight new viewpoints for the design of RSD Ge JL MOSFETs with channel doping $({N}_{\text {ch}}) \ge {5}\times {10}^{18}$ cm−3 to facilitate sharp current transition. [ABSTRACT FROM AUTHOR]

Nonvolatile logic computations are of particular interest due to their zero standby leakage power consumption. In this paper, we explore a nonvolatile majority logic using voltage-driven magnetoelectric (ME) switching of ferromagnets. Specifically, we employ ME magnetic tunnel junctions (ME-MTJs) connected in parallel to construct a majority gate. We also present the cascadability of the proposed majority gate using CMOS inverters. Furthermore, through a mixed-mode simulation framework consisting of magnetization dynamics and electron transport model, we analyze the robustness of the proposed majority gate under process variations. Our analysis shows that due to parallel connection of the ME-MTJs, high tunnel magnetoresistance (TMR) ratios are required for proper functioning of the proposed majority gate, in presence of variations. In order to relax the constraints on the TMR requirements, we present an alternate implementation of the majority logic that does not require a parallel connection of ME-MTJs, thereby increasing the robustness against process variations. Energy and delay metrics are presented for a full adder implementation using the proposed majority gates. [ABSTRACT FROM AUTHOR]

In this paper, we present an effective switching current model ( I\textsf {eff} ) for inverter followed by a transmission gate structure (Inv-Tx) based on its switching trajectory. Unlike an inverter or NAND/NOR gates, where I\textsf {eff} depends only on nMOSFET (pMOSFET) current for a falling (rising) transition, it is a function of both nMOSFET and pMOSFET currents for an Inv-Tx cell. The proposed model is verified against HSPICE simulations for a wide range of supply voltages and fan-outs at different technology nodes (e.g., 180, 130, and 65 nm). The model predicts the transition delay values with an average (maximum) error of 7% (11%) compared with HSPICE simulations. Synopsys TCAD Sentaurus simulations at 32-nm technology node are also used to validate the basic model assumptions. To demonstrate the utility of our model, design of some representative circuits while incorporating layout-dependent effects and inverse-narrow-width effect is presented. Finally, we show that a 256X1 multiplexer and a static D-flip-flop, with their transistor sizes and layout, optimized using the proposed model improves the performance of these circuits significantly over the conventional design methodologies. [ABSTRACT FROM PUBLISHER]

This paper reports on the impact of soft- and hard-switching conditions on the dynamic ON-resistance of AlGaN/GaN high-electron mobility transistors. For this study, we used a special double pulse setup, which controls the overlapping of the drain and gate waveforms (thus inducing soft and hard switching), while measuring the corresponding impact on the ON-resistance, drain current, and electroluminescence (EL). The results demonstrate that the analyzed devices do not suffer from dynamic R {\mathrm{\scriptscriptstyle ON}} increase when they are submitted to soft switching up to V{\text {DS}}= 600 V. On the contrary, hard-switching conditions lead to a measurable increase in the dynamic ON-resistance (dynamic- R \mathrm{\scriptscriptstyle ON}) . The increase in dynamic R \mathrm{\scriptscriptstyle ON} induced by hard switching is ascribed to hot-electrons effects: during each switching event, the electrons in the channel are accelerated by the high electric field and subsequently trapped in the AlGaN/GaN heterostructure or at the surface. This hypothesis is supported by the following results: 1) the increase in R \mathrm{\scriptscriptstyle ON} is correlated with the EL signal measured under hard-switching conditions and 2) the impact of hard switching on dynamic R \mathrm{\scriptscriptstyle ON} becomes weaker at high-temperature levels, as the average energy of hot electrons decreases due to the increase scattering with the lattice. [ABSTRACT FROM PUBLISHER]

This paper presents low insertion loss, high isolation, ultra-wideband double-pole-double-throw (DPDT) switch matrix designed in a 0.13- \mu \textm commercial high resistivity trap-rich silicon-on-insulator (SOI) CMOS process for the first time. The switches are designed using series–shunt–series configuration in a ring-type structure with input and output matching networks. Transistor width and transistor channel length effects on the wideband DPDT switch performance are thoroughly investigated. The designed switches achieve widest bandwidth from dc to 30 GHz with a low insertion loss of 2.5 dB and a high isolation of 32 dB up to 30 GHz. The measured input P1dB of designed switches is higher than 18 dBm. It was found both second and third harmonics can be improved by widening switch transistor channel width, and third harmonic can be improved by shortening channel length. The active chip area of designed $2 \times2$ switch matrix is very small size of only 0.28 mm $\times0.21$ mm. [ABSTRACT FROM PUBLISHER]

This paper presents a methodology to model GaN power HEMT switching transients. Thus, a compact model to predict devices’ pulse switching characteristics and current collapse reliability issue has been developed. Parasitic RC subcircuits and a standard double-pulse switching tester to model intrinsic parasitic effects and to analyze power dissipation of GaN power HEMT are proposed and presented. Switching transient including gate-lag and drain-lag is predicted for ideal (without trap) and nonideal (with trap) devices. The results are validated by and compared to 2-D finite-element technology computer-aided design simulations. The original aim of this exercise is to develop a fast (near-real-time) model which can predict dynamic behavior of single and multiple power GaN HEMTs used for the switching transients of GaN power devices at circuit level. [ABSTRACT FROM PUBLISHER]

In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

Bidirectional power transistors are essential components of several power electronics systems, such as matrix converters. In this paper, we present the operating principles, design considerations, and experimental characteristics of a novel planar gate 4H-SiC bidirectional insulated gate bipolar transistors. The impact of various drift layer and unit cell parameters on blocking, on-state, and switching performance has been evaluated by using numerical simulations, and critical performance tradeoffs have been discussed. Based on the optimized design, devices were fabricated on lightly doped free-standing n-type 4H-SiC wafers. Fabricated devices showed good conductivity modulation, with a forward voltage drop of 9.7 V at 50 A/cm2 at room temperature, which increased to 11.5 V at 150 °C. [ABSTRACT FROM AUTHOR]

Ferroelectric field effect transistors (FeFETs) based on ferroelectric hafnium oxide (HfO2) thin films show high potential for future embedded nonvolatile memory applications. However, HfO2 films besides their recently discovered ferroelectric behavior are also prone to undesired charge trapping effects. Therefore, the scope of this paper is to verify the possibility of the charge trapping during standard operation of the HfO2-based FeFET memories. The kinetics of the charge trapping and its interplay with the ferroelectric polarization switching are analyzed in detail using the single-pulse ID – VG technique. Furthermore, the impact of the charge trapping on the important memory characteristics such as retention and endurance is investigated. [ABSTRACT FROM AUTHOR]

Many steeply switching logic devices have recently been proposed to overcome the energy efficiency limitations of CMOS technology. In this paper, circuit-level energy–performance analysis is used to derive the design requirements for these alternative switching devices. Using a simple analytical approach, this paper shows that the optimal Ion/Ioff and Edyn/Eleak ratios are set only by circuit-level parameters as well as the device transfer characteristic off-state Soff, on -state Son, and effective Seff inverse slopes. For a wide variety of switching device characteristics and circuit parameters, the optimal Edyn/Eleak ratio is approximately (K/\2)(Seff/Soff) - \0.56(Son/Soff) - \0.56, where K ranges from 6.23 to 11.9. Based upon this theoretical framework, simple requirements for Soff, Son, and Seff are established in order for an alternative switching device to be more energy efficient than a MOSFET. The results reemphasize that merely focusing on achieving the steepest local inverse slope S is insufficient, since energy dissipation is set mainly by Seff and not by S. Finally, the general shape of the energy–delay curve is also set by these inverse slopes, with its steepness directly proportional to Son/Soff. This analytical approach provides a simple method to assess the promise of any new device technology in potentially overcoming the energy efficiency limitations of CMOS technology. [ABSTRACT FROM AUTHOR]

In this paper, static and dynamic performances of an AlGaN/GaN-on-Si power FET utilizing the integrated photonic-ohmic drain (PODFET) were systematically investigated. The operational mechanisms of the PODFET, including both the conditions of photon generation and the related physical processes, were explained. The dynamic switching tests were carried out under two types of hard switching conditions. With the photon generation and channel current inherently switched ON and OFF in synchronization, the dynamic performances of the PODFET can be significantly enhanced owing to photon pumping of deep electron traps. In addition, the generated photons were proved to be confined in proximity of the drain terminal without causing adverse effects on the device performances (e.g., the OFF-state leakage degradation). [ABSTRACT FROM PUBLISHER]

Switching behavior in electron–hole bilayer tunnel FETs is known to be unaffected by the subthreshold swing limitation of 60 mV/decade imposed by thermal injection, due to the band-to-band tunneling phenomena on which they rely. However, in this paper, we show that, once parasitic lateral tunneling processes are suppressed by means of heterogate configurations, a new physical limitation arises at the onset of tunneling in this type of transistors, resulting from the interplay between field-induced quantum confinement and asymmetric concentrations of electrons and holes inside the channel. We demonstrate that this limitation comes from the fact that, regardless of the band profile sharpness, the tunneling distance at subband alignment cannot be reduced beyond a certain limit, which we find to be dependent on the body thickness and the material properties. [ABSTRACT FROM PUBLISHER]

Disordered ionic-bonded transition metal oxide thin-film transistors (TFTs) show promise for a variety of dc and RF switching applications, especially those that can leverage their low-temperature, substrate-agnostic process integration potential. In this paper, enhancement-mode zinc-oxide TFTs were fabricated and their switching performance evaluated. These TFTs exhibit the drain-current density of 0.6 A/mm and minimal frequency dispersion, as evidenced by dynamic current–voltage tests. A high-frequency power switch figure of merit $R_{{\mathrm{\scriptscriptstyle ON}}}Q_{G} of 359 \textm\Omega \,\cdot \, nC was experimentally determined for 0.75- \mu \textm long-channel devices, and through scaling 45.9 \textm\Omega \,\cdot \, nC is achievable for 11 V-rated devices (where R\mathrm{\scriptscriptstyle ON} is ON-state drain–source resistance, and QG is gate charge). An RF switch cutoff frequency fc of 25 GHz was measured for the same 0.75- \mu \textm TFT, whereas fc exceeding 500 GHz and power handling in the tens of watts are projected with optimization. [ABSTRACT FROM AUTHOR]

A positive feedback (PF) mechanism was adopted for the first time in the cell string of a 3-D NAND flash memory where n+ and p+ regions are formed on both ends of the string to implement a diode-type cell string. The body consists of a tube-type poly-Si channel. To generate the PF in the channel during a read operation, a new read operation scheme is proposed. In this paper, the simulator was calibrated in terms of trap density ( D\mathrm {it}) of a poly-Si channel extracted from fabricated 3-D NAND flash memory cells. By utilizing the PF, a NAND flash memory cell in a cell string has a steep subthreshold swing of <1 mV/decade. [ABSTRACT FROM AUTHOR]

Resistive switching memory (RRAM) has been proposed as an artificial synapse in neuromorphic circuits due to its tunable resistance, low power operation, and scalability. For the development of high-density neuromorphic circuits, it is essential to validate the state-of-the-art bistable RRAM and to introduce small-area building blocks serving as artificial synapses. This paper introduces a new synaptic circuit consisting of a one-transistor/one-resistor structure, where the resistive element is a HfO2 RRAM with bipolar switching. The spike-timing-dependent plasticity is demonstrated in both the deterministic and stochastic regimes of the RRAM. Finally, a fully connected neuromorphic network is simulated showing online unsupervised pattern learning and recognition for various voltages of the POST spike. The results support bistable RRAM for high-performance artificial synapses in neuromorphic circuits. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the influence of the drain electrode on the dynamic switching behavior of AlGaN/GaN high-electron-mobility transistors on Si substrate. By adding a field plate to the drain electrode, a dramatic increase in the dynamic ON-resistance dynR \mathrm{\scriptscriptstyle ON} was identified. The dispersion effect is correlated with the high electric field below the drain field plate (DFP), the onset of which is caused by the full electron depletion from both the channel and the GaN cap layer. We show that the electron distribution is modified by the passivation method, backside bias, or surface charges and, hence, shifts the onset voltage of the trapping effect. Trapped electrons underneath the DFP are thought to be responsible for the measured rise of the dynR \mathrm{\scriptscriptstyle ON} . With the introduction of an extended ohmic drain contact, the influence of a metallization overhang at the drain edge can be suppressed. The detrapping energies associated with the surface defects were determined to 0.2, 0.3, and 0.7 eV, respectively. Simulations and measurements indicate that charges inside the passivation below the DFP worsen the switching behavior. [ABSTRACT FROM AUTHOR]

This paper presents a comprehensive simulation analysis of the dynamic operation of T-RAM cells. The analysis addresses the evolution of cell electrostatics and of carrier concentrations and flows in the device when the gate voltage undergoes a fast low-to-high switch, as required by both read and write operations. The results clarify, first of all, the basic physics making holes in the p-base the physical element allowing information storage in the device. From this starting point, the working principles exploited for DRAM operation of the memory cell are then explained. [ABSTRACT FROM AUTHOR]

Through their high gain and low saturation voltage, source-gated transistors (SGTs) have applications in both analog and digital thin-film circuits. In this paper, we show how we can design SGT-based logic gates, which are practically unaffected by temperature variations. We discuss design characteristics, which ensure reliable operation in spite of SGT temperature dependence of drain current, and their implications for manufacturability and large signal operation. [ABSTRACT FROM AUTHOR]

This paper presents ferroelectric single-electron transistors (SETs) with tunable tunnel barriers and their application in a reconfigurable binary decision diagram (BDD) logic architecture. In this experimental demonstration, the SETs can be programmed into short, open, and Coulomb blockade modes to construct the BDD fabric. We experimentally demonstrate the decision node, consisting of two SETs, with robust path switching characteristics. Harnessing such programmability and path switching features, a nonvolatile reconfigurable low-power BDD logic is achieved. A ferroelectric dielectric-based split gate configuration and a differential biasing scheme are utilized to share the programming resources and reduce the energy consumption. Peripheral interface circuits are designed to recover the output signal swing for cascaded BDD logic demonstration and to provide noise immunity. The simulation shows that with sufficient circuitry complexity or a latched dynamic CMOS interface, the proposed BDD architecture achieves higher power efficiency than CMOS at the same throughput delay. [ABSTRACT FROM AUTHOR]

Two types of 4H-silicon carbide (SiC) MOSFETs are proposed in this paper. One is the novel designed V-groove trench MOSFET that utilizes the 4H-SiC (0-33-8) face for the channel region. The MOS interface using this face shows the extremely low interface state density ( D\mathrm {\mathbf {it}} ) of 3\times 10^11 \mathrmcm^-2~\mathrmeV^-1 , which causes the high channel mobility of 80 \mathrmcm^2~\mathrmV^-1~\mathrms^-1 results in very low channel resistance. The buried p+ regions located close to the trench bottom can effectively alleviate the electric field crowding without the significant sacrifice of the increase of the resistance. The low specific ON-state resistance of 3.5 m \Omega ~\mathrmcm^\mathrm \mathbf 2 with sufficiently high blocking voltage of 1700 V is obtained. The other is the double implanted MOSFET with the carefully designed junction termination extension and field-limiting rings for the edge termination region, and the additional doping into the junction FET region. With a high-quality and high-uniformity epitaxial layer, 6 mm $\times 6$ mm devices are fabricated. The well balanced specific ON-state resistance of 14.2 m \Omega ~\mathrm{cm}^{2} and the blocking voltage of 3850 V are obtained for 3300 V application. [ABSTRACT FROM AUTHOR]

This paper studies the application of tunnel FET (TFET) in designing a low power and robust cellular neural network (CNN)-based associative memory (AM). The lower leakage, steeper switching slope, and higher output resistance of TFET are exploited in designing an ultralow-power TFET-based operational transconductance amplifier (OTA). A TFET-OTA is utilized as a programmable synaptic weight multiplier for CNN. The ultralow-power of TFET-OTA enables a higher connectivity network even at a lower power, and thereby improves the memory capacity and input pattern noise tolerance of CNN-AM for low power applications. The TFET-based higher connectivity CNN also exploits the unique characteristics of TFET to improve the throughput efficiency of CNN-AM. [ABSTRACT FROM AUTHOR]

The recently discovered ferroelectric behavior of HfO2-based dielectrics yields the potential to overcome the main challenges of the ferroelectric field-effect transistors (FeFETs)—CMOS compatibility as well as scalability to the state-of-the-art technology nodes of logic transistors. In this paper, we study the impact of scaling on the memory performance of FeFET devices employing Si:HfO2 ferroelectric films. The operation capability was proven down to a gate length of 28 nm. Program/erase characteristics, endurance behavior, and retention properties were analyzed for FeFETs with gate lengths scaled down to 32 nm. The detected difference in the performance between the long and short channel devices could be for the most part attributed to transistor short channel effects. In addition, the effect of temperature on the device properties of Si:HfO2-based FeFETs was investigated in detail. The program/erase speed was ascertained to be independent of temperature. On the other hand, increase in temperature resulted in reduced initial memory window accompanied by its slightly accelerated decay with time. [ABSTRACT FROM AUTHOR]

An ideal switch with hysteresis-free \(S_{\rm ideal}=0~{\rm mV/decade}\) switching is desired to keep Moore’s law alive, but has never been achieved. Classical field-effect transistors (FETs) have supported Moore’s law for 50 years, albeit with a thermodynamically limited value of subthreshold swing \(S\ge 60\) mV/decade. Alternatives, such as, tunnel FETs, impact ionization FETs, and negative capacitance FETs promise \(S <60\) mV/decade, but ideal switching is not expected, even in theory. In this paper, we propose a zero subthreshold swing FET (ZSubFET), which is similar to a classical FET with a suspended-gate and a ferroelectric gate insulator. ZSubFET exhibits ideal switching through integration of two negative capacitors (namely, a ferroelectric and an air-gap) in the gate-stack, in series with the channel capacitance. We believe that the proposed device concept should not only lower the power dissipation in an IC, but also open up new research directions for the alternative of classical-FET. [ABSTRACT FROM AUTHOR]

Relentless performance and density scaling of modern CMOS devices has come at the expense of circuit stability and variability. In this paper, we specifically reveal how switching traps can cause intolerable V \(_{\rm TH}\) shifts and fluctuations, which are even visible during the I \(_{D}\) –V \(_{G}\) tracing in nanometer-scaled devices. Exploiting this feature, we have developed a methodology for random telegraph noise assessment capable of determining the capture and emission times \(\tau _{c}\) and \(\tau _{e}\) , and their impact on V \(_{\rm TH}\) as a function of gate voltage V \(_{G}\) and temperature T. This information is crucial for developing circuit simulators that assess the impact of single traps in the full V \(_{G}\) swing and operational temperatures. [ABSTRACT FROM PUBLISHER]

A compact microelectromechanical (MEM) switch design and associated family of logic gates, memory cells, and other basic very-large-scale integration (VLSI) digital circuit sub blocks are proposed to ensure zero crowbar current in addition to zero leakage current while minimizing mechanical delay. The circuit design methodology introduced in this paper also provides for lower device count and hence lower operating power consumption. A prototype of the MEM switch design is demonstrated. [ABSTRACT FROM PUBLISHER]

In this paper, we show performance and reliability improvement of Ag-GeS2-based conductive bridge RAM (CBRAM) devices by addition of a 2-nm-thick HfO2 layer between the electrolyte and the W bottom electrode. Our optimized dual-layer electrolyte stack (2-nm HfO2\--30\-nm~GeS2) leads to a resistance ratio (ROFF/RON) higher than 10^6 and projected 10 years read disturb immunity at 0.04 V. The improved memory resistance ratio is explained by means of physical modeling. Using compact modeling and circuit level simulations, we show that our optimized CBRAM device, integrated in a 1T-2R architecture, fits well with the aggressive requirements of field programmable gate array-type reconfigurable applications. Nonvolatility, back-end-of-line compatibility, and 1.3-nA leakage current during continuous reverse read operation at 1 V are strong benefits demonstrated on our device for such applications. [ABSTRACT FROM AUTHOR]

The sub-threshold swing (S) defines the sharpness of ON-OFF switching of a field effect transistor (FET), with S=0 corresponding to abrupt switching characteristics. While thermodynamics dictate S\geq 60~mV/decade for classical FETs, a new class of switches which we call “Landau switches” e.g., suspended gate FET (SG-FET) and ferroelectric FET (FE-FET) use inherently unstable (negative capacitance) gate insulators to achieve abrupt switching. Unfortunately, S=0 switching in Landau switches is always achieved at the expense of an intrinsic hysteresis, making them unsuitable for low-power applications. The fundamental question therefore is: under what conditions, hysteresis-free abrupt switching can be achieved in a Landau switch? In this paper, we first provide an intuitive classification of all semiconductor FETs in terms of their energy landscapes and identify a two-well energy landscape as the characteristic feature of all Landau switches. We then use the SG-FET as an illustrative example to conclude that a flat energy landscape is essential for hysteresis-free abrupt switching. In contrast, a hysteresis-free smooth switching (S\leq 60~mV/decade) is less restrictive, and is obtained by stabilizing the unstable gate insulator in its negative capacitance regime. Our conclusions have broad implications for the analysis and design of ultralow power sub-60 mV/decade switches. [ABSTRACT FROM AUTHOR]

This paper presents a physical model for program and retention transients in ferroelectric (FE) and charge hybrid nonvolatile memory. A region-by-region statistical model for domain switching in polycrystalline FEs was incorporated with the tunneling current simulations to predict the memory window (\Delta VTH) evolution during program and retention operations. The simulations validated the two-step program mechanism experimentally observed in such memories: rapid initial domain switching on account of high fields in the FE layer followed by field enhancement in the tunneling dielectric which initiates electron injection into the storage nodes. Further, these simulations were shown to accurately account for individual \Delta VTH from the two additive memory mechanisms at all program times. The depolarization effect was shown to be dominant for \Delta VTH loss at short and moderate retention time scales (<100~s). This model was further used to provide realistic estimates in achieving dual speed program and the corresponding dual mode retention characteristics akin to a DRAM and flash hybrid operation. [ABSTRACT FROM AUTHOR]

The electron–hole bilayer tunnel field-effect transistor (EHBTFET) is an electronic switch that uses 2-D-2-D sub-band-to-sub-band tunneling (BTBT) between electron and hole inversion layers and shows significant subthermal swing over several decades of current due to the step-like 2-D density of states behavior. In this paper, EHBTFET has been simulated using a quantum mechanical model. The model results are compared against transactions on computer-aided design simulations and remarkable differences show the importance of quantum effects and dimensionality in this device. Ge EHBTFET with channel thickness of 10 nm results as a promising device for low supply voltage, subthreshold logic applications, with a super steep switching behavior featuring SSavg\sim 40~\rm mV/\rm dec up to VDD. Furthermore, it has been demonstrated that high on current levels (\sim40~\muA/\mum) can be achieved due to the transition from phonon-assisted BTBT to direct BTBT at higher biases. [ABSTRACT FROM AUTHOR]

Nonvolatile memory (NVM) devices based on storage layers, p-n junctions and transistors, such as FLASH, suffer from poor retention at high temperature, high voltage writing, and wear out while cycling. This paper presents the structure, operation, and modeling of a nanoelectromechanical NVM based on the switching of a free electrode between two stable states. This electrode, called the shuttle, has no mechanical anchors and commutes between two positions. It is guided inside an insulator pod. Adhesion forces between the shuttle and fixed electrodes serve to hold the shuttle in stable positions. Smooth metal layers give strong Van der Waals stiction between two surfaces in contact. Memory detection is obtained by probing the conductance between two fixed contacts; the shuttle serves as a switchable open/short electrode. Electromechanical contacts have an ideally large resistance ratio between on and off levels. At microscale, gravity is found to be negligible compared with adhesion forces, which motivates the anchorless design for high-temperature data storage. The model proposed is based on charge induction over the surface of metal electrodes and is validated by finite-element method. Kinematic equations and energy transfers of the shuttle device are explored. Due to its unique anchorless design, the scalability of the anchorless shuttle memory is found to be excellent. [ABSTRACT FROM AUTHOR]

This paper presents, for the first time, the study of the application of a lateral diffused metal–oxide–semiconductor field-effect transistor (LDMOSFET) in a common-gate configuration to radio-frequency (RF) transmit/receive (T/R) switching circuits. A single-pole double-throw (SPDT) 900-MHz T/R switch is implemented using 0.25-\mu\m LDMOSFET foundry technology. Measured results show that our switching circuit can achieve a low insertion loss of 0.82 dB and a high power handling capability of 27 dBm. This result is promising in integrating power management integrated circuits, RF power amplifiers, and switching circuits in a single chip, based on LDMOSFET technology, to realize an RF transmit front-end system-on-chip solution. [ABSTRACT FROM AUTHOR]

The GaN high-electron mobility transistor (HEMT) structure has been widely investigated, particularly for radio-frequency applications. This structure is suitable for high-frequency switching applications in power electronics because of the high breakdown field of GaN and the high mobility of the channel. In this paper, a physical model for predicting the power-switching operation of GaN-based HEMTs as a function of material and device parameters is proposed. Analytical equations for total losses and power dissipation density are derived and discussed both qualitatively and quantitatively. [ABSTRACT FROM PUBLISHER]

In this paper, we examine the performance characteristics of bilayer graphene pseudospin devices as we scale the layer width of the monolayers of graphene which comprise the bilayer structure. We find that, for layer widths of 30 nm, the device performance can exceed analytical predictions due to thermal smoothing of the interlayer interactions. However, when the device is further scaled to 20 nm and below, we find an appreciable drop of the maximum current the device can sustain when compared with the predicted values which result from increased quantum interference between injected quasi-particles and those reflected off of the excitonic gap opened at the Fermi energy. These results provide important insight into the maximum achievable performance characteristics and optimal device-design parameters for this promising potential post-CMOS logic device. [ABSTRACT FROM PUBLISHER]

This paper presents a new class of charge-trap Flash memory device with resistive switching mechanisms. We propose a fused memory scheme using a structure of metal/\Pr0.7 \Ca0.3\MnO3 (PCMO)/nitride/oxide/silicon to graft fast-switching features of resistive random access memory onto high-density silicon/oxide/nitride/oxide/silicon memory structures. In this scheme, both program and erase (P/E) are performed by the conduction of the carriers that are injected from the gate into the nitride layer through the PCMO, which is a resistive switching material; the resistance state determines whether a program or erase function is performed. In the proposed memory devices, we observed improved memory characteristics, including the current–voltage hysteresis having a resistive ratio exceeding three orders of magnitude at a set voltage of \pm4.5 V, a memory window of 2.3 V, a P/E speed of 100 ns/1 ms, data retention of ten years, and endurance of \10^5 P/E cycles. This approach will offer critical clues about how one can best implement universal features of nonvolatile memories in a single chip. [ABSTRACT FROM PUBLISHER]