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The 2021 release of Reimagining Our Futures Together: A New Social Contract for Education by the United Nations Educational, Scientific, and Cultural Organization was a reaction to a number of serious problems discovered in worldwide educational reforms. It sought to establish a new social compact for education to fulfill its unmet promise in the face of many educational crises and to combat future uncertainty. Using the methods of 271 Education Group as a case study, this article examines China's efforts to transform basic education in response to widespread educational issues and how they have represented the major principles espoused by the UNESCO report. The article elaborates on the coping strategies of 271 Education Group, such as incorporating eco-civilization education into basic schooling, constructing life-based curricula that are built on knowledge commons, introducing pedagogy rooted in cooperation and solidarity, and promoting teacher professional development through collaborative educational research.

β-Ga2O3 has been subjected to intense research interest as an ultrawide bandgap semiconductor. The epitaxial growth technique of β-Ga2O3 thin films plays a fundamental and vital role in Ga2O3-based device fabrication. In this work, the epitaxial growth mechanisms of β-Ga2O3 on four low-Miller-index facets, (100), (010), (001), and ( 2 ¯ 01), are systematically explored using large-scale machine-learning molecular dynamics simulations at the atomic scale. The simulations reveal that the migration of the face-centered cubic stacking O sublattice plays a dominant role in the different growth mechanisms between the (100)/(010)/(001) and ( 2 ¯ 01) orientations. The resultant complex combinations of the stacking faults and twin boundaries are carefully identified and show good agreement with experimental observations and ab initio calculations. Our results provide useful insights into the gas-phase epitaxial growth of β-Ga2O3 thin films and suggest possible ways to tailor its properties for specific applications. [ABSTRACT FROM AUTHOR]

In this work, we focused on investigating the transport-limited trapping effects in GaN-on-Si buffer layers as well as impact of the thickness of buffer layers (TBuf) upon such effects. Vertical transport dynamics of charges within the buffer layers and their key energy levels are quantitatively and statistically investigated and analyzed. The results show that an increased TBuf diminishes both impurity conduction of the defect band formed by carbon doping as well as the injection of electrons from the substrate, greatly diminishing the current collapse and improving the stability of the device. Such enhancement is mainly attributed to the reduced vertical electric field within the thickened epitaxy, which provides an additional pathway to address the current collapse and yields more efficient power GaN-on-Si devices. [ABSTRACT FROM AUTHOR]

Ga2O3 is a wide-band gap semiconductor of emergent importance for applications in electronics and optoelectronics. However, vital information of the properties of complex coexisting Ga2O3 polymorphs and low-symmetry disordered structures is missing. We develop two types of machine-learning Gaussian approximation potentials (ML-GAPs) for Ga2O3 with high accuracy for β/κ/α/δ/γ polymorphs and generality for disordered stoichiometric structures. We release two versions of interatomic potentials in parallel, namely soapGAP and tabGAP, for high accuracy and exceeding speedup, respectively. Both potentials can reproduce the structural properties of all the five polymorphs in an exceptional agreement with ab initio results, meanwhile boost the computational efficiency with 5 × 102 and 2 × 105 computing speed increases compared to density functional theory, respectively. Moreover, the Ga2O3 liquid-solid phase transition proceeds in three different stages. This experimentally unrevealed complex dynamics can be understood in terms of distinctly different mobilities of O and Ga sublattices in the interfacial layer. [ABSTRACT FROM AUTHOR]

${p}$ -channel GaN field-effect transistors (FETs) with a SiNx/GaON gate stack have been demonstrated with enhanced stability within a wide range of voltage bias and temperature. In this letter, the gate leakage characteristics and reliability of this unconventional staggered gate stack are investigated. At relatively low gate voltages, the gate current is suppressed owing to the buried-channel structure and the presence of GaON that presents an effective hole barrier. With more negative gate biases, the gate leakage was found to be dominated by the transport of holes that spillover from the ${p}$ -channel through the SiNx via Poole-Frenkel emission. Based on this gate leakage mechanism at large gate bias, $\sqrt {{\mathrm {E}}} $ model was used for gate lifetime prediction. The maximum applicable ON-state gate voltage of −7.3 V is obtained for a 10-year lifetime with a 1% gate failure rate. [ABSTRACT FROM AUTHOR]

In this article, the impacts of the off-state gate bias (VGS,OFF) on dynamic on-resistance (RON) are systematically investigated in commercial Schottky-type p-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed I–V system are adopted to evaluate the dynamic RON with various off-state gate and drain bias (VDS,OFF) under hard- and soft-switching conditions. More negative VGS,OFF can aggravate the dynamic RON degradation under both soft- and hard-switching, especially when switching with a high VDS,OFF. The impacts of VGS,OFF on switching transients and off-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The off-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

In a ${p}$ -channel field-effect-transistor (${p}$ -FET) bridge HEMT device recently realized on a commercial ${p}$ -GaN/AlGaN/GaN-on-Si power HEMT epi-wafer, it is revealed that the device’s reverse-conduction turn-on voltage (${V}_{\text {RT}}$) can be effectively decoupled from the forward threshold voltage (${V}_{\text {TH}}$) of Schottky-type ${p}$ -GaN gate HEMTs. Unlike the conventional Schottky-type ${p}$ -GaN gate HEMTs, of which ${V}_{\text {RT}}$ is closely linked to ${V}_{\text {TH}}$ , the ${p}$ -FET-bridge HEMT enables separate designs of ${V}_{\text {RT}}$ and $V_{\text {TH}}$ so that low-loss reverse conduction and high threshold voltage can be simultaneously realized. In addition, ${V}_{\text {RT}}$ can be further reduced by engineering the AlGaN barrier layer, which will also benefit a lower channel sheet resistance without lowering ${V}_{\text {TH}}$. [ABSTRACT FROM AUTHOR]

In this work, we study the gate leakage mechanisms of E-mode p-n junction/AlGaN/GaN (PNJ) high electron mobility transistors (HEMTs), which have been shown to deliver low gate leakage and wide safe operating gate-bias range. The intrinsic gate leakage through the PNJ-gate was found to be limited by the transport of holes through the p-GaN layer, which occurs via Poole-Frenkel emission and phonon-assisted tunneling in low and high gate bias region, respectively. In addition, lateral leakage current and the role of variable hopping process (VRH) are also discussed. Gate leakage current models based on the revealed mechanisms can quantitatively reproduce the gate-leakage behavior in the entire relevant range of gate biases and temperatures. [ABSTRACT FROM AUTHOR]

When the gated channel region of a GaN high-electron-mobility transistor (HEMT) is configured into multiple sub-channels in parallel and separated by embedded isolating patterns, the effective resistance of the access regions could be reduced, and consequently, the knee voltage (${V}_{{\text {K}}}$) of the transistor could be lowered. In this work, each sub-channel is defined as a convergent funnel-like shape, with its width gradually shrunk from the source side to the drain side. Different from conventional channels with uniform width under the entire gate, the funnel-shaped channel could converge electrons as they transport from source side to drain side, which facilitates electrons’ acceleration toward saturation velocity under a smaller drain-to-source bias, leading to a reduced intrinsic ${V}_{{\text {K}}}$ in the gated channel. Thus, more desirable ${I}$ - ${V}$ characteristics and more balanced performance enhancement in RF linearity and power added efficiency are achieved at a low supply voltage, making the convergent-channel HEMT attractive for power amplifiers in mobile terminals. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate a GaN-based $\textit {p-n}$ junction gate (PNJ) HEMT featuring an ${n}$ -GaN/ ${p}$ -GaN/AlGaN/GaN gate stack. Compared to the more conventional ${p}$ -GaN gate HEMT with a Schottky junction between the gate metal and ${p}$ -GaN layer, the $\textit {p-n}$ junction can withstand higher reverse bias at the same peak electric-field as the depletion region extends to both the ${n}$ -side and ${p}$ -side, while exhibiting lower leakage current. The PNJ-HEMT shows a positive threshold voltage (${V}_{\text {TH}}$) of 1.78 V, a small gate leakage $(\sim 10^{-3}$ mA/mm @ ${V}_{\text {GS}} = {10}\,\, \text {V}$). In particular, a large forward gate breakdown voltage of 19.35 V at 25 °C and 19.70 V at 200 °C was achieved with the PNJ-gate HEMT. [ABSTRACT FROM AUTHOR]

We conducted reliability characterization under reverse-bias stress (i.e., stress at OFF-state with high VDS) on the E-mode GaN metal–insulator–semiconductor field-effect-transistors (MIS-FETs) with various substrate terminations. The MIS-FETs with floating substrate (FS) show worse threshold voltage (VTH) stability than that with a grounded substrate. A non monotonic dependence of VTH shifts and OFF-state time-to-breakdown (tbd) on the positive substrate bias (Vsub) was also observed. The underlying mechanisms are the different impacts of positive Vsub on the drift of electrons and holes during the long-term stress. An important indication is that positive-biased and FS terminations should be restricted at OFF-state in order to obtain good VTH stability in applications of the GaN MIS-FET. [ABSTRACT FROM AUTHOR]

In this paper, systematic characterization and the corresponding suppression strategies of dynamic OFF-state leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) are presented based on fast pulsed ${I}$ – ${V}$ measurement and consecutive switching measurement. It is found that the high ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under dynamic pulse mode without hole injection is a result of the reduced voltage blocking capabilities (both lateral and vertical) with weaker trapping effect in the buffer, and the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection is caused by further increased lateral conductivity through the buffer from source to drain. The corresponding behaviors under continuous waveforms with different switching conditions are analyzed to identify effective approaches for the suppression of dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ in practical switching operations. A higher temperature is shown to be beneficial to the reduction of the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ induced by ON-state hole injection. To completely eliminate the dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ caused by ON-state hole injection and minimize the OFF-state power consumption in practical power switching applications, a sufficiently large negative OFF-state gate bias (e.g., ${V}_{\text {GS}, \mathrm{\scriptscriptstyle OFF}}\le -{3}$ V) is recommended in the gate driver turn-off voltage design for the Schottky-type p-GaN gate HEMTs. [ABSTRACT FROM AUTHOR]

Low-loss reverse-conducting normally- OFF double-channel AlGaN/GaN power transistor with the built-in Schottky barrier diode (SBD) has been systematically studied. This device features the MOS-gate section and SBD-anode section paralleled to an interdigital layout along the gate width direction. A common access region that conducts current at both forward and reverse ON-states is employed, which is beneficial to reduce the conduction loss. With a MOS-HEMT/SBD finger width of ${4}~\mu \text{m}/2~\mu \text{m}$ and a total width ratio of 2:1, the device exhibits a threshold voltage of +0.8 V at a drain current of ${10}~\mu \text{A}$ /mm and a low forward ON-resistance of $12.1~\Omega \cdot \text {mm}$. The Schottky metal contacts 2-DEG directly, which results in a low reverse turn-on voltage of −0.6 V (at −1 mA/mm) and low reverse ON-state voltage of −1.7 V (at −50 mA/mm). A leakage suppression MOS field plate (FP) is applied to shield the Schottky contact from the strong electric field, leading to a low OFF-state leakage current of 14 nA/mm at +100-V drain bias and a high breakdown voltage (BV) of +698 V. The finger width and the number of fingers should be optimized. A narrow finger width benefits the current sharing at the access region, while the increasing number of fingers introduces more Schottky depletion regions along the gate width direction that degrade ${R}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

The drain induced dynamic threshold voltage (${V}_{\textrm {th}}$) shift of a ${p}$ -GaN gate HEMT with a Schottky gate contact is investigated, and the underlying mechanisms are explained with a charge storage model. When the device experiences a high drain bias ${V}_{\textrm {DSQ}}$ , the gate-to-drain capacitance (${C}_{\textrm {GD}}$) is charged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$). As the drain voltage drops to ${V}_{\textrm {DSM}}$ where ${V}_{\textrm {th}}$ is measured, ${C}_{\textrm {GD}}$ is expected to be discharged to ${Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). However, the metal/ ${p}$ -GaN Schottky junction could block the discharging current, resulting in storage of negative charges in the ${p}$ -GaN layer. For the device to turn on, additional gate voltage is required to counteract the stored negative charges, resulting in a positive shift of ${V}_{\textrm {th}}$. The dynamic ${V}_{\textrm {th}}$ shift is an intrinsic and predictable characteristic of the ${p}$ -GaN gate HEMT which is linearly correlated with $\Delta \!{Q}_{\textrm {GD}}={Q}_{\textrm {GD}}$ (${V}_{\textrm {DSQ}}$) $- {Q}_{\textrm {GD}}$ (${V}_{\textrm {DSM}}$). The ${V}_{\textrm {th}}$ shift is dependent on ${V}_{\textrm {DSQ}}$ as well as ${V}_{\textrm {DSM}}$ , indicating that the ${V}_{\textrm {th}}$ shift is varying along the load line during a switching operation. [ABSTRACT FROM AUTHOR]

In this work, we demonstrate an easy channel-engineering method using oxygen-plasma treatment followed by in-situ annealing before gate dielectric deposition on GaN. A crystalline GaON nanophase was identified to serve as an optimized channel layer in the gate region of E-mode GaN metal-insulator-semiconductor field-effect transistors (MIS-FETs). The atomic-scale element distribution and crystalline structure of the GaON nanophase were revealed by aberration-corrected scanning transmission electron microscopy. First-principles calculations further correlate the enhanced thermal stability with the atomic observation of the refined structure in the GaON nanophase. Owing to the atomically sharp gate-dielectric/channel interface and low interface trap density (Dit), the boosted performance of the E-mode MIS-FET was achieved with the GaON channel. This study not only validates an approach of local channel modification for high-performance normally off GaN MIS-FETs but also opens possibilities of utilizing this crystalline GaON nanophase as a promising channel material in various GaN devices. [ABSTRACT FROM AUTHOR]

Under reverse-bias stress (i.e., OFF-state stress with ${V} _{\text {GS}} < {V}_{\text {TH}}$) with high drain voltage, ultraviolet (UV) illumination and larger negative gate bias are found to accelerate the positive shift in threshold voltage (${V}_{\text {TH}}$) of enhancement-mode GaN MIS-FETs with fully recessed gate. These results suggest a hole-induced degradation mechanism. In the absence of UV illumination, holes could be generated by impact ionization in the high electric-field region, which is initiated by electrons injected from the source through the buffer layer. With a larger negative gate bias, more holes will flow to the gate side and pass through the silicon nitride (SiNx) gate dielectric, as SiNx does not present any energy barrier to holes. The enhanced hole transport through the dielectric under large negative gate bias could accelerate new defects generation and therefore result in the larger positive threshold voltage shifts. [ABSTRACT FROM AUTHOR]

The OFF-state drain leakage characteristics in 600-V p-GaN HEMTs with an ohmic gate contact are investigated under dynamic switching conditions instead of commonly used quasi-static measurement setup. It is found that fast dynamic OFF-state leakage current (dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$) is substantially higher than the slow-ramping quasi-static ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ due to the weaker trapping effect in the buffer layer. With sufficiently large positive ON-state gate bias, further increase in dynamic ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ is observed and is attributed to ON-state hole injection that leads to energy band lowering in the buffer. The underlying physical processes are explained by the dynamic behavior of the traps in the buffer layer. This letter indicates that the ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ under practical switching operations is much higher than the static measurement results and should be used to evaluate dynamic OFF-state power consumption in the p-GaN HEMTs with an ohmic gate contact. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiNx/PECVD-SiNx) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance (${R}_{ \mathrm{ON}}$), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET. [ABSTRACT FROM AUTHOR]

An MOS field plate-protected Schottky-drain (gated Schottky-drain) is successfully integrated on a double-channel AlGaN/GaN MOS-HEMT to provide reverse blocking capability. The leakage suppression MOS field plate is deployed on the etched upper GaN channel layer after a barrier fully recess process, leading to a low reverse OFF-state leakage current of −20 nA/mm (at −100 V). The drain metal is deployed adjacent to the MOS field plate, contacting the upper MOS-channel and lower heterojunction channel from the sidewall. A metal-2DEG Schottky contact with a low turn-ON voltage of 0.5 V is achieved. Since the lower channel (below the MOS field plate) is separated from the etched surface of upper GaN channel layer, a high-conductivity MOS-gated channel with a sheet resistance of 806 $\Omega$ /Square is obtained. The device exhibits a threshold voltage of +0.6 V (at $10~\mu \text{A}$ /mm and +1.9 V from linear extrapolation) and an ON-resistance of ~18 $\Omega {\cdot} \text {mm}$. Besides, a high forward (and reverse) breakdown voltage of 790 V (and −656 V, all at $10~\mu \text{A}$ /mm) is achieved. [ABSTRACT FROM AUTHOR]

In this work, characterizations are conducted to investigate the threshold voltage (VTH) stability of the normally‐off GaN metal–insulator–semiconductor (MIS‐) field‐effect transistor (FET) with fully recessed gate structure and highly reliable low‐pressure chemical vapor deposition SiNx gate dielectric. We conducted bias‐temperature instability (BTI) tests under both positive and negative gate bias. We demonstrated the highly stable VTH of the high‐performance MIS‐FETs with small BTI, which benefits from the effective interfacial protection layer. More specifically, combining the BTI tests and drain current 1/f noise analysis, we present extensive investigation of the physical origins of BTI. According to the experimental evidence and analysis, we ascribe the VTH instability to the trapping/detrapping of the pre‐existing trap states located at the SiNx/GaN interface and/or in the gate dielectric. [ABSTRACT FROM AUTHOR]

In this letter, we investigated the threshold voltage V\text {TH} stability under reverse-bias step-stress in the E-mode LPCVD-SiNx/PECVD-SiNx/GaN MIS-FET. Under the OFF-state reverse-bias stress with the same net gate-to-drain voltage ( V\text {GD} ), the V\text {TH} shift shows an obvious dependence on the negative gate bias. With a V\text {GS} of 0 V, the V\text {TH} shift is small and recoverable, while the V\text {TH} shifts are substantially larger with more negative gate bias ( V\text {GS}=-20 V). This larger V\text {TH} shifts caused by the negative V\text {GS} can be explained with a hole-induced degradation model. An important indication revealed by this model is that negative gate bias should be well confined in high-power switching applications of GaN E-mode MIS-FET for a stable V\text {TH} . [ABSTRACT FROM PUBLISHER]

An AlGaN/GaN double-channel Schottky barrier diode (DC-SBD) with dual-recess gated anode is demonstrated in this letter. The DC-SBD features two recess steps. The deep one cuts through two channels, and the anode metal contacts 2DEG directly from the sidewall of the recessed heterostructure. The shallow one terminates at the upper channel layer and is located adjacent to the Schottky contact. A MOS field plate is placed on the shallow recess region to pinchoff the underlying channels, so the off-state leakage current of the DC-SBD can be suppressed. Since the lower channel is separated from the etched surface, the field-effect mobility beneath this MOS structure shows a high peak value of 1707 cm2/( \text V\cdot \text s ). The DC-SBD with an anode-to-cathode length ( L\text {ac} ) of 15~\mu \textm exhibits a turn-on voltage ( V\text {T} ) of ~0.6 V (at 1 mA/mm), a leakage current of 7.8 nA/mm (at −100 V), and a breakdown voltage of 704 V (at 1~\mu \textA /mm). The double-channel design also allows both the deep and shallow recesses to be terminated at GaN layers that results in high uniformity of V\text {T} . [ABSTRACT FROM PUBLISHER]

In this paper, we report a systematic study of the nitridation effects on GaN surface by first-principles calculations and X-ray/ultraviolet photoemission spectroscopy (XPS/UPS). According to the calculated electronic structures, two surface bands (i.e., the upper band and the lower band) can be seen within the bandgap for the typical surface configurations that may occur in the experimental condition as a result of surface reconstruction. By the deployment of sufficient nitridation, the energy positions of the lower band are modified toward the valence band by ~1 eV, resulting in the overlapping of the lower surface band with the valence band. Meanwhile, the upper surface band is also modified toward the valence band, but by a smaller amount. The modification to the positions of the surface bands is furthermore manifested by XPS/UPS spectra characterization performed on GaN sample that underwent surface treatment with low-energy remote N2 plasma. The theoretical and experimental results insightfully proclaim the nitridation effects on material properties at atomic level, and support a surface-state ionization model for the GaN band-edge (3.4 eV) emission in metal-AlGaN/GaN Schottky-on-heterojunction diode under forward bias. [ABSTRACT FROM PUBLISHER]

Dynamic ON-resistance ( \mathrm RON ) of 650-V GaN-on-Si lateral power devices with a floating Si-substrate termination is investigated. Compared with the grounded substrate termination, the floating substrate could deliver smaller dynamic \mathrm RON under higher drain bias (> 400 V) switching operation, but leads to larger dynamic \mathrm RON under low-drain bias (< 400 V). The underlying physical mechanisms are explained by the tradeoff between charge storage in the Si substrate and electron trapping effect in the GaN buffer layer. [ABSTRACT FROM AUTHOR]

Developing effective technique to protect the etched- GaN surface from the degradation in a high-temperature (i.e., at ~ 780°C) process, such as low-pressure chemical vapor deposition (LPCVD), is essential for fabricating normally-off GaN MIS-FETs with high-quality dielectric/GaN interface and highly reliable gate dielectric. In this letter, we developed an approach of obtaining such a protection layer using oxygen-plasma treatment followed by in situ annealing prior to the LPCVD-SiNx deposition. A sharp and stable crystalline oxidation interlayer (COIL) between the LPCVD-SiNx and etched-GaN was successfully formed. The LPCVD-SiNx/GaN MIS-FETs with COIL deliver normally-off operation with a VTH of 1.15 V, small on-resistance, small hysteresis, and thermally stable VTH . [ABSTRACT FROM AUTHOR]

GaN power switching transistors featuring MIS- and MOS-gate structures are highly preferred over the Schottky-gate counterpart, because of suppressed gate leakage, enlarged gate swing, and more scalable threshold voltage. Nevertheless, MIS-/MOS-gate GaN devices are confronted with stability and reliability challenges, which arise from interface traps at the critical dielectric/III-nitride interface, as well as bulk traps inside the gate dielectric including border traps near the critical interface. In this work, we present several key techniques toward reliable MIS-/MOS-gate GaN power devices, including advanced interface engineering technology, gate structure optimizations for high-performance/stability normally-off GaN power transistors, and long-lifetime gate dielectric technology. Schematic cross sections of GaN-based MIS-HEMT and MOS-channel-HEMT. [ABSTRACT FROM AUTHOR]

In this letter, we demonstrate an integrated process that illustrates the compatibility of AlN/SiNx passivation with high-performance (i.e. low leakage and high breakdown) low-pressure chemical vapor deposition (LPCVD) SiNx gate dielectric for GaN-based MIS-HEMT. It is shown that the AlN/SiNx passivation structure maintains its superior capability of suppressing the current collapse after enduring high temperature of 780 °C during the LPCVD-SiNx deposition. The AlN/SiNx passivation is shown to be significantly better than the LPCVD-SiNx passivation by delivering small dynamic $R_{{\mathrm{\scriptscriptstyle ON}}}$ degradation, especially under high drain bias switching with $V_{{\mathrm{DS}}} > 100$ V. [ABSTRACT FROM PUBLISHER]

A low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with V\mathrm {th} of +0.5 V at I\mathrm {DS}= 10 ~\mu \text{A} /mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/( \textV\cdot \texts ). The on-resistance is as small as 6.9 \Omega \cdot \text mm for a DC-MOS-HEMT with LG/L\mathrm {GS}/L\mathrm {GD} = 1.5/2/15~\mu \text{m} , and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. [ABSTRACT FROM AUTHOR]

In this paper, we systematically investigated the leakage and breakdown mechanisms of the low-pressure chemical vapor deposition (LPCVD) silicon nitride thin film deposited on AlGaN/GaN heterostructures. The LPCVD-SiNx gate dielectric exhibits low leakage and high breakdown electric field. The dominant mechanism of the leakage current through LPCVD-SiNx gate dielectric is identified to be Poole–Frenkel emission at low electric field and Fowler–Nordheim tunneling at high electric field. Both electric-field-accelerated and temperature-accelerated time-dependent dielectric breakdown of the LPCVD-SiNx gate dielectric were also investigated. [ABSTRACT FROM PUBLISHER]

In this letter, silicon nitride (SiNx) film deposited at 780 °C by low-pressure chemical vapor deposition (LPCVD) was employed as gate dielectric for GaN-based metal–insulator–semiconductor high-electron-mobility transistors. The LPCVD-SiNx exhibit improved gate dielectric performance than the plasma enhanced chemical vapor deposition-SiNx, including smaller forward and reverse gate leakage, and higher forward gate breakdown voltage. [ABSTRACT FROM AUTHOR]

P-grid is a typical feature in power devices to block high off-state voltage. In power devices, the p-grid is routinely coupled to an external electrode with an Ohmic contact, but Schottky contact to the p-grid is also proposed/adopted for certain purposes. This work investigates the role of contact to p-grid in power devices based on the commonly adopted technology computer-aided design (TCAD) device simulations, with the silicon carbide (SiC) junction barrier Schottky (JBS) diode as a case study. The static characteristics of the JBS diode is independent of the nature of the contact to p-grid, including the forward voltage drop (VF) and the breakdown voltage (BV). However, during the switching process, a Schottky contact would cause storage of negative charges in the p-grid, which leads to an increased VF during switching operation. On the contrary, an Ohmic contact provides an effective discharging path for the stored negative charges in the p-grid, which eliminates the dynamic degradation issues. Therefore, the necessity of an Ohmic contact to p-grid in power devices is clarified. [ABSTRACT FROM AUTHOR]

Two-dimensional van der Waals heterostructures with strong intrinsic ferroelectrics are highly promising for novel devices with designed electronic properties. The polarization reversal transition of the 2D ferroelectric Ga 2 O 3 monolayer offers a new approach to tune the photocatalytic and electrical properties of MoS 2 /Ga 2 O 3 heterogeneous bilayers. In this work, we study MoS 2 /Ga 2 O 3 heterogeneous bilayers with different intrinsic polarization using hybrid-functional calculations. We closely investigate the structural, electronic and optical properties of two stable stacking configurations with opposite polarization. The results reveal a distinct switch from type-I to type-II heterostructures owing to polarization reversal transition of the 2D ferroelectric Ga 2 O 3 monolayer. Biaxial strain engineering leads to type-I-to-II and type-II-to-III transitions in the two polarized models, respectively. Intriguingly, one of the MoS 2 /Ga 2 O 3 heterolayers has a larger spatial separation of the valence and conduction band edges and excellent optical absorption ranging from infrared to ultraviolet region under biaxial strain, thus ensuring promising novel applications such as flexible electrical and optical devices. Based on the highly tunable physical properties of the bilayer heterostructures, we further explore their potential applications, such as photocatalytic water splitting and field-controlled switch channel in MOSFET devices.

A two-dimensional (2D) Ga 2 O 3 monolayer with an asymmetric quintuple-layer configuration was reported as a novel 2D material with excellent stability and strain tunability. This unusual asymmetrical structure opens up new possibilities for improving the selectivity and sensitivity of gas sensors by using selected surface orientations. In this study, the surface adsorptions of nine molecular gases, namely, O 2 , CO 2 , CO, SO 2 , NO 2 , H 2 S, NO, NH 3 , and H 2 O, on the 2D Ga 2 O 3 monolayer are systematically investigated through first-principles calculations. The intrinsic dipole of the system leads to different adsorption energies and changes in the electronic structures between the top- and bottom-surface adsorptions. Analyses of electronic structures and charge transport calculations indicate a potential application of the 2D Ga 2 O 3 monolayer as a room-temperature NO gas-sensing device with high sensitivity and tunable adsorption energy using plenary strain-induced lattice distortion.

A novel two-dimensional (2D) Ga 2 O 3 monolayer was constructed and systematically investigated by first-principles calculations. The 2D Ga 2 O 3 has an asymmetric configuration with a quintuple-layer atomic structure, the same as the well-studied α-In 2 Se 3 , and is expected to be experimentally synthesized. The dynamic and thermodynamic calculations show excellent stability properties of this monolayer material. The relaxed Ga 2 O 3 monolayer has an indirect band gap of 3.16 eV, smaller than that of β-Ga 2 O 3 bulk, and shows tunable electronic and optoelectronic properties with biaxial strain engineering. An attractive feature is that the asymmetric configuration spontaneously introduces an intrinsic dipole and thus the electrostatic potential difference between the top and bottom surfaces of the Ga 2 O 3 monolayer, which helps to separate photon-generated electrons and holes within the quintuple-layer structure. By applying compressive strain, the Ga 2 O 3 monolayer can be converted to a direct band gap semiconductor with a wider gap reaching 3.5 eV. Also, enhancement of hybridization between orbitals leads to an increase of electron mobility, from the initial 5000 to 7000 cm 2 V -1 s -1 . Excellent optical absorption ability is confirmed, which can be effectively tuned by strain engineering. With superior stability, as well as strain-tunable electronic properties, carrier mobility, and optical absorption, the studied novel Ga 2 O 3 monolayer sheds light on low-dimensional electronic and optoelectronic device applications.

Using remote N 2 plasma treatment to promote dielectric deposition on the dangling-bond free MoS 2 is explored for the first time. The N 2 plasma induced damages are systematically studied by the defect-sensitive acoustic-phonon Raman of single-layer MoS 2 , with samples undergoing O 2 plasma treatment as a comparison. O 2 plasma treatment causes defects in MoS 2 mainly by oxidizing MoS 2 along the already defective sites (most likely the flake edges), which results in the layer oxidation of MoS 2 . In contrast, N 2 plasma causes defects in MoS 2 mainly by straining and mechanically distorting the MoS 2 layers first. Owing to the relatively strong MoS 2 -substrate interaction and chemical inertness of MoS 2 in N 2 plasma, single-layer MoS 2 shows great stability in N 2 plasma and only stable point defects are introduced after long-duration N 2 plasma exposure. Considering the enormous vulnerability of single-layer MoS 2 in O 2 plasma and the excellent stability of single-layer MoS 2 in N 2 plasma, the remote N 2 plasma treatment shows great advantage as surface functionalization to promote dielectric deposition on single-layer MoS 2 .

Transistors based on MoS2 and other TMDs have been widely studied. The dangling-bond free surface of MoS2 has made the deposition of high-quality high-k dielectrics on MoS2 a challenge. The resulted transistors often suffer from the threshold voltage instability induced by the high density traps near MoS2/dielectric interface or inside the gate dielectric, which is detrimental for the practical applications of MoS2 metal-oxide-semiconductor field-effect transistor (MOSFET). In this work, by using AlN deposited by plasma enhanced atomic layer deposition (PEALD) as an interfacial layer, top-gate dielectrics as thin as 6 nm for single-layer MoS2 transistors are demonstrated. The AlN interfacial layer not only promotes the conformal deposition of high-quality Al2O3 on the dangling-bond free MoS2, but also greatly enhances the electrical stability of the MoS2 transistors. Very small hysteresis (ΔVth) is observed even at large gate biases and high temperatures. The transistor also exhibits a low level of flicker noise, which clearly originates from the Hooge mobility fluctuation instead of the carrier number fluctuation. The observed superior electrical stability of MoS2 transistor is attributed to the low border trap density of the AlN interfacial layer, as well as the small gate leakage and high dielectric strength of AlN/Al2O3 dielectric stack.