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A tunnel-oxide-free GaN-based non-volatile memory (NVM) device is proposed to untangle the trilemma among speed, retention, and endurance in the implementation of conventional NVM. The program and erase (P/E) are based on bipolar charge injection controlled by individual junction barriers, whereas the data retention relies on bipolar charge trapping in an interfacial charge storage layer. The wide bandgap energy of GaN allows the formation of deep-level traps at a dielectric/GaN interface and high junction barriers in GaN, both of which benefit long-term retention. As such, the GaN-based NVM device could get rid of the tunnel oxide, thereby enabling faster P/E processes and facilitating to decouple the enhancement of endurance from that of speed and retention. The proposed device demonstrates a P/E time of 100 ns, endurance over 106 cycles, and long retention time. [ABSTRACT FROM AUTHOR]

In a ${p}$ -channel field-effect-transistor (${p}$ -FET) bridge HEMT device recently realized on a commercial ${p}$ -GaN/AlGaN/GaN-on-Si power HEMT epi-wafer, it is revealed that the device’s reverse-conduction turn-on voltage (${V}_{\text {RT}}$) can be effectively decoupled from the forward threshold voltage (${V}_{\text {TH}}$) of Schottky-type ${p}$ -GaN gate HEMTs. Unlike the conventional Schottky-type ${p}$ -GaN gate HEMTs, of which ${V}_{\text {RT}}$ is closely linked to ${V}_{\text {TH}}$ , the ${p}$ -FET-bridge HEMT enables separate designs of ${V}_{\text {RT}}$ and $V_{\text {TH}}$ so that low-loss reverse conduction and high threshold voltage can be simultaneously realized. In addition, ${V}_{\text {RT}}$ can be further reduced by engineering the AlGaN barrier layer, which will also benefit a lower channel sheet resistance without lowering ${V}_{\text {TH}}$. [ABSTRACT FROM AUTHOR]

In this article, an ultrathin-barrier (UTB) AlGaN/GaN diode featuring metal–insulator–semiconductor (MIS)-gated hybrid anode (MG-HAD) and in situ Si3N4 cap passivation is demonstrated. The intrinsic turn-on voltage (VON) as low as 0.31 V determined by the as-grown AlGaN-barrier thickness (4.9 nm) is obtained and the VON exhibits excellent uniformity. More importantly, benefit from the MIS-gated hybrid anode structure, the UTB MG-HAD features good thermal stability in reverse blocking capability. The device delivers a substantially low leakage less than 1~μm/mm at −300 V at high temperature (HT) up to 200 °C, which is more than 100 × lower than that in the reference device w/o gate dielectric. Besides, the device exhibits respectably improved dynamic characteristics due to the incorporation of in situ Si3N4-cap passivation layer and remote plasma pretreatment (RPP) prior to Al2O3 gate dielectric deposition. The UTB MG-HAD featuring precisely VON modulation and low reverse leakage is of great interest for power electronic applications. [ABSTRACT FROM AUTHOR]

Low-loss reverse-conducting normally- OFF double-channel AlGaN/GaN power transistor with the built-in Schottky barrier diode (SBD) has been systematically studied. This device features the MOS-gate section and SBD-anode section paralleled to an interdigital layout along the gate width direction. A common access region that conducts current at both forward and reverse ON-states is employed, which is beneficial to reduce the conduction loss. With a MOS-HEMT/SBD finger width of ${4}~\mu \text{m}/2~\mu \text{m}$ and a total width ratio of 2:1, the device exhibits a threshold voltage of +0.8 V at a drain current of ${10}~\mu \text{A}$ /mm and a low forward ON-resistance of $12.1~\Omega \cdot \text {mm}$. The Schottky metal contacts 2-DEG directly, which results in a low reverse turn-on voltage of −0.6 V (at −1 mA/mm) and low reverse ON-state voltage of −1.7 V (at −50 mA/mm). A leakage suppression MOS field plate (FP) is applied to shield the Schottky contact from the strong electric field, leading to a low OFF-state leakage current of 14 nA/mm at +100-V drain bias and a high breakdown voltage (BV) of +698 V. The finger width and the number of fingers should be optimized. A narrow finger width benefits the current sharing at the access region, while the increasing number of fingers introduces more Schottky depletion regions along the gate width direction that degrade ${R}_{ \mathrm{\scriptscriptstyle ON}}$. [ABSTRACT FROM AUTHOR]

The impacts of static and dynamic gate stress on the threshold voltage (${V}_{\text {TH}}$) instability in Schottky-type ${p}$ -GaN gate AlGaN/GaN heterojunction field-effect transistors are experimentally investigated. ${V}_{\text {TH}}$ shifts negatively under large positive bias static stress (${V}_{\text {G}}\_ {\text {stress}} > 5$ V) by adopting conventional quasi-static characterization techniques. In contrast, ${V}_{\text {TH}}$ under fast-dynamic-stress exhibits positive shift, and a positive frequency dependence occurs within a wide range of frequency from 10 Hz to 1 MHz. The different ${V}_{\text {TH}}$ instability behavior under static and dynamic stress mainly originates from the time-dependent charges (electrons and holes) storage/release mechanisms in the ${p}$ -GaN layer, which is floating in the Schottky-type ${p}$ -GaN gate HEMT. [ABSTRACT FROM AUTHOR]

An MOS field plate-protected Schottky-drain (gated Schottky-drain) is successfully integrated on a double-channel AlGaN/GaN MOS-HEMT to provide reverse blocking capability. The leakage suppression MOS field plate is deployed on the etched upper GaN channel layer after a barrier fully recess process, leading to a low reverse OFF-state leakage current of −20 nA/mm (at −100 V). The drain metal is deployed adjacent to the MOS field plate, contacting the upper MOS-channel and lower heterojunction channel from the sidewall. A metal-2DEG Schottky contact with a low turn-ON voltage of 0.5 V is achieved. Since the lower channel (below the MOS field plate) is separated from the etched surface of upper GaN channel layer, a high-conductivity MOS-gated channel with a sheet resistance of 806 $\Omega$ /Square is obtained. The device exhibits a threshold voltage of +0.6 V (at $10~\mu \text{A}$ /mm and +1.9 V from linear extrapolation) and an ON-resistance of ~18 $\Omega {\cdot} \text {mm}$. Besides, a high forward (and reverse) breakdown voltage of 790 V (and −656 V, all at $10~\mu \text{A}$ /mm) is achieved. [ABSTRACT FROM AUTHOR]

A systematic analytical investigation of the charge distribution and gate control of the normally-off GaN double-channel MOS-HEMT (DC-MOS-HEMT) is presented in this paper. Compared to conventional GaN MOS-HEMT, the DC-MOS-HEMT features a thin AlN insertion layer (AlN-ISL) below the original two dimensional electron gas (2DEG) channel, thus forming a second channel at the interface between AlN-ISL and the underlying GaN. This paper reveals the impact of the AlN-ISL on the 2DEG distribution and the gate control of the channels. The sensitivity of ${V}_{\text {th}}$ against the recess depth is also analytically studied and is found to be nearly independent of the recess depth as long as the recess is terminated in the upper channel layer. The analytical results are well supported by numerical device simulations, and the physical mechanisms behind these findings are explained along with the analytical investigations. [ABSTRACT FROM AUTHOR]

An AlGaN/GaN double-channel Schottky barrier diode (DC-SBD) with dual-recess gated anode is demonstrated in this letter. The DC-SBD features two recess steps. The deep one cuts through two channels, and the anode metal contacts 2DEG directly from the sidewall of the recessed heterostructure. The shallow one terminates at the upper channel layer and is located adjacent to the Schottky contact. A MOS field plate is placed on the shallow recess region to pinchoff the underlying channels, so the off-state leakage current of the DC-SBD can be suppressed. Since the lower channel is separated from the etched surface, the field-effect mobility beneath this MOS structure shows a high peak value of 1707 cm2/( \text V\cdot \text s ). The DC-SBD with an anode-to-cathode length ( L\text {ac} ) of 15~\mu \textm exhibits a turn-on voltage ( V\text {T} ) of ~0.6 V (at 1 mA/mm), a leakage current of 7.8 nA/mm (at −100 V), and a breakdown voltage of 704 V (at 1~\mu \textA /mm). The double-channel design also allows both the deep and shallow recesses to be terminated at GaN layers that results in high uniformity of V\text {T} . [ABSTRACT FROM PUBLISHER]

(Al)GaN recess-free normally OFF technology is developed for fabrication of high-yield lateral GaN-based power devices. The recess-free process is achieved by an ultrathin-barrier (UTB) AlGaN/GaN heterostructure that features a natural pinched-off 2-D electron gas channel. The top–down manufacturing technique overcomes the challenges in etching of AlGaN barrier with well-controlled depth and uniformity, which is especially attractive for fabrication of normally OFF GaN-based high-electron-mobility transistors (HEMTs) and metal–insulator–semiconductor HEMTs (MIS-HEMTs) on large-size Si substrate. With SiNx passivation grown by low-pressure chemical-vapor deposition, on-resistance of the UTB-AlGaN/GaN-based power devices can be significantly reduced. High-uniformity low-hysteresis normally OFF HEMTs and Al2O3/AlGaN/GaN MIS-HEMTs are successfully demonstrated on the UTB AlGaN/GaN-on-Si platform. It is also a compelling technology platform for manufacturing high-performance GaN-based lateral power diodes, and normally OFF p-(Al)GaN heterojunction field-effect transistors. [ABSTRACT FROM PUBLISHER]

Bulk traps in the high-resistivity buffer stack underneath the 2-dimensional electron gas (2DEG), which can interact with the high vertical electric field at OFF state, impose a critical challenge to the dynamic ON-resistance (RON) of AlGaN/GaN-on-Si power devices. In this paper, the impact of substrate bias polarity on carrier injection/transport and buffer-induced current collapse has been investigated by using ramped and transient back-gating characterizations as well as TCAD simulations. High voltage applied to the conductive Si substrate can modulate 2DEG conductivity through the back-gate effect, whereby the dynamics of both acceptor and donor buffer traps are identified. Distinct buffer trapping and asymmetric vertical leakage under opposite top-to-substratebias polarities have been observed, which are attributed to the fundamentally different carrier injection/transport mechanisms. It is suggested that the energy barrier at the nucleation-layer/Si interface can limit the electron injection from Si substrate into the buffer stack and consequently influence the bufferrelated current collapse. [ABSTRACT FROM AUTHOR]

The switching behavior of on-chip photon sources, i.e., the p-doping-free Schottky-on-heterojunction light-emitting diodes (SoH-LEDs), which can be seamlessly integrated into the AlGaN/GaN-on-Si power high electron mobility transistors platform is investigated. It is demonstrated that the electroluminescence (EL) from an interdigital SoH-LED can be switched at least up to 10 MHz, fulfilling the requirement of most power switching circuits. In order to evaluate the EL switching limit of SoH-LEDs, a quantitative analysis of the dependence of junction current on operating frequency at different dc biases is performed based on S-parameter characteristics. At a criterion of junction-current/input-current to 50%, the cutoff frequency of an interdigital SoH-LED is obtained to be 210 MHz at a forward bias of 4 V. This letter proves that the SoH-LED is adequately fast for being employed as an on-chip synchronous photon source in GaN power switching applications. [ABSTRACT FROM PUBLISHER]

Ultra-thin-barrier (UTB) AlGaN/GaN heterostructure is utilized for fabrication of normally-OFF GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs). The sheet resistance of 2-D electron gas in the UTB Al0.22Ga0.78N(5-nm)/GaN heterostructure is effectively reduced by SiNx passivation grown by low-pressure chemical vapor deposition, from 2570 to 334~\Omega /□. The fabricated Al2O3/AlGaN/GaN MIS-HEMTs exhibit normally-OFF behavior with good V_{\mathrm {TH}} uniformity and low V_{\mathrm {TH}} -hysteresis. 20 mm-gate-width power devices featuring a low R\sc {\mathrm{ on}} of 0.75~\Omega ( \textI\mathrm {D,MAX} =6.5 A) are also demonstrated on the platform. [ABSTRACT FROM PUBLISHER]

In this paper, static and dynamic performances of an AlGaN/GaN-on-Si power FET utilizing the integrated photonic-ohmic drain (PODFET) were systematically investigated. The operational mechanisms of the PODFET, including both the conditions of photon generation and the related physical processes, were explained. The dynamic switching tests were carried out under two types of hard switching conditions. With the photon generation and channel current inherently switched ON and OFF in synchronization, the dynamic performances of the PODFET can be significantly enhanced owing to photon pumping of deep electron traps. In addition, the generated photons were proved to be confined in proximity of the drain terminal without causing adverse effects on the device performances (e.g., the OFF-state leakage degradation). [ABSTRACT FROM PUBLISHER]

A GaN/SiC hybrid field-effect transistor (HyFET) is proposed as a high-voltage power device that provides a high-mobility lateral AlGaN/GaN channel to reduce the channel resistance and a vertical SiC drift region to sustain the high OFF-state voltage. The performance of the HyFET is evaluated by numerical device simulations. Compared with the conventional SiC MOSFET, the HyFET exhibits a greatly reduced R\mathrm{\scriptscriptstyle ON} together with a low C\mathrm{ GD} and low gate charges. The figures of merit Q\mathrm{ G}\times R\mathrm{\scriptscriptstyle ON} and Q\mathrm{ GD}\times R\mathrm{\scriptscriptstyle ON} of the HyFET are dramatically improved. [ABSTRACT FROM AUTHOR]

Integration of a photon source into the AlGaN/GaN high election mobility transistor (HEMT) platform will realize the functionality of on-chip optical pumping of deep electron traps which suppress the dynamic performances of power HEMTs. Here, we report a Schottky-on-heterojunction light-emitting diode (SoH-LED) realized on the p-doping-free lateral AlGaN/GaN heterostructure. A physical mode based on hot electron induced surface states impact ionization was proposed to explain the hole generation and injection processes in this p-doping-free SoH-LED. Since the SoH-LED shares identical epitaxial structures with HEMT, integration of SoH-LED and HEMT requires no additional epi-layers during the wafer growth and minimum process modification during device fabrication. The SoH-LED structure was seamlessly integrated into the HEMT platform as an on-chip photon source. Experiment results showed that the SoH-LED photons can effectively assist the electron de-trapping processes from both of the surface and bulk deep traps, demonstrating the feasibility of using on-chip generated photons to improve the dynamic performances of AlGaN/GaN power HEMTs. [ABSTRACT FROM AUTHOR]

In this work, the Schottky-on-heterojunction light-emitting diodes (SoH-LED) are monolithically integrated with the AlGaN/GaN high-electron-mobility transistors (HEMT) on an AlGaN/GaN-on-Si platform commonly used for GaN lateral electronic devices. The on-chip electro-optic modulation is realized in a single device fabricated using HEMT-compatible process. Also, SoH-LED arrays are fabricated to demonstrate the on-chip addressable functionality with each SoH-LED pixel in the array individually controlled by the integrated HEMT. High-resolution micro-scale SoH-LED seven-segment displays are demonstrated to show the potential of using SoH-LEDs as a robust alternative for micro flat-panel displays. [ABSTRACT FROM AUTHOR]

A low on-resistance normally-off GaN double-channel metal–oxide–semiconductor high-electron-mobility transistor (DC-MOS-HEMT) is proposed and demonstrated in this letter, which features a 1.5-nm AlN insertion layer (ISL) located 6 nm below the conventional barrier/GaN interface, forming a second channel at the interface between the AlN-ISL and the underlying GaN. With gate recess terminated at the upper channel, normally-off operation was obtained with V\mathrm {th} of +0.5 V at I\mathrm {DS}= 10 ~\mu \text{A} /mm or +1.4 V from the linear extrapolation of the transfer curve. The lower heterojunction channel is separated from the etched surface in the gate region, thereby maintaining its high field-effect mobility with a peak value of 1801 cm2/( \textV\cdot \texts ). The on-resistance is as small as 6.9 \Omega \cdot \text mm for a DC-MOS-HEMT with LG/L\mathrm {GS}/L\mathrm {GD} = 1.5/2/15~\mu \text{m} , and the maximum drain current is 836 mA/mm. A high breakdown voltage (>700 V) and a steep subthreshold swing of 72 mV/decade are also obtained. [ABSTRACT FROM AUTHOR]

In this paper, we systematically investigated the leakage and breakdown mechanisms of the low-pressure chemical vapor deposition (LPCVD) silicon nitride thin film deposited on AlGaN/GaN heterostructures. The LPCVD-SiNx gate dielectric exhibits low leakage and high breakdown electric field. The dominant mechanism of the leakage current through LPCVD-SiNx gate dielectric is identified to be Poole–Frenkel emission at low electric field and Fowler–Nordheim tunneling at high electric field. Both electric-field-accelerated and temperature-accelerated time-dependent dielectric breakdown of the LPCVD-SiNx gate dielectric were also investigated. [ABSTRACT FROM PUBLISHER]

The temperature dependence of current collapse (CC) in AlGaN/GaN high-electron mobility transistors on silicon substrate is studied in this paper. Devices without and with Si3N4 passivation are used to investigate the behavior of surface- and buffer-induced CC, respectively. It is found that the degree of surface-induced CC in unpassivated devices has a weak temperature dependence, which is induced by the cancelling out between enhanced carrier injection based on surface hopping and enhanced emission when the temperature is increased. On the other hand, the degree of buffer-induced CC in the Si3N4 passivated devices is reduced at higher temperature since the energy of hot electrons is reduced due to the phonon scattering and the trapping of hot electrons in the buffer is mitigated. Temperature-dependent transient measurement is also carried out to investigate the recovery process for these two type of CC. Two types of trap levels are identified in the unpassivated and Si3N4 passivated devices, respectively. The trap level $E1$ with an activation energy of 0.08 eV is supposed to be related to the surface trapping, while $E2$ with an activation energy of 0.22 eV is located in the buffer layer. [ABSTRACT FROM AUTHOR]

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoHLED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The detrapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance Ron and/or threshold voltage Vth of the HEMT. The results show that the recovery processes of both dynamic Ron and threshold voltage Vth of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs. [ABSTRACT FROM AUTHOR]

The degradation of transient OFF-state leakage current in AlGaN/GaN HEMTs induced by ON-state gate overdrive was observed and studied. The OFF-state leakage current increases significantly with a pre- ON-state gate overdrive. It takes more than 30 s for the leakage current decay to its equilibrium level in dark. The decay processes follow a stretched-exponential law. We propose that this degradation corresponds to the persistent photoconductivity of GaN buffer induced by the electroluminescence during the Schottky gate overdrive. Both the ON-state gate overdrive bias and duration dependences of the OFF-states leakage degradation were studied. This work indicates that gate-protection is necessary to preserve low OFF-state leakage current and improve device reliability. (© 2014 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

We experimentally demonstrate a high-voltage low-standby power startup circuit for powering up the off-line switched-mode power supply (SMPS) during the startup period by exploiting monolithically integrated enhancement/depletion-mode metal–insulator–semiconductor high electron mobility transistors (E/D-mode MIS-HEMTs) fabricated on a GaN-on-Si power device platform. The E/D-mode MIS-HEMTs exhibit a threshold voltage of +1.2 and -11~V, respectively. The high-voltage D-mode device used in the demonstration features an OFF-state breakdown voltage of 640 V and a safe operating area with a thermal limitation of 11.6 W/mm, whereas the low-voltage E-mode device features a source-gate breakdown voltage of 98 V, satisfying the requirement of the startup circuit. The functionality of the startup circuit is successfully achieved with an input voltage range 10–200 V and a startup current of 1.08 mA. [ABSTRACT FROM AUTHOR]

In this paper, a surface potential-based terminal charge and capacitance model, including parasitic components for AlGaN/GaN HEMTs is developed. First, by solving the charge control equations, the sheet charge density in the channel is modeled with a close-form expression. Then, using this result, based on the surface potential definition, the intrinsic terminal charges and capacitances are derived consistently with current model. Finally, by introducing parasitic components, the capacitances for the full structure of the HEMT devices are given. The model is evaluated step-by-step with good agreements compared with the TCAD simulations and the experimental data. Meanwhile, the effects of bulk traps and surface traps in the capacitances are analyzed. The complete model, including currents and capacitances has been implemented in i-MOS platform for evaluations and circuit simulations. [ABSTRACT FROM PUBLISHER]

The threshold voltage ( VT) instability of metal-insulator-semiconductor high electron mobility transistors (MIS-HEMTs) is investigated. In the enhancement-mode AlGaN/GaN MIS-HEMT fabricated by fluorine plasma implantation technique featuring Al2O3 gate dielectric, a hysteresis of 0.6 V in transfer characteristics is observed by quasi-static I - V (current-voltage) measurement, in which the gate bias is swept at a low rate (0.7 V/s). Pulsed transfer characteristics measurement, however, unveils much larger hysteresis under the same gate voltage swing. The VT-instability is attributed to the traps located at the dielectric/III-nitride interface as well as in the bulk of gate dielectric. It is proposed that pulsed measurement can count for the effect of fast traps (shallow traps) while the quasi-static measurement can only reflect slow traps (deep traps), and is more accurate for VT-instability evaluation. In addition, the existence of bulk traps is implied by a slow time-dependent shift of VT under large gate bias. (© 2013 WILEY-VCH Verlag GmbH & Co. KGaA, Weinheim) [ABSTRACT FROM AUTHOR]

In this paper, we investigate the enhancement-mode (E-mode) LaLuO3 (LLO)-AlGaN/GaN metal-insulator-semiconductor high-electron mobility transistors (MIS-HEMTs) fabricated using fluorine (F) plasma ion implantation with a gate-dielectric-first planar process. The E-mode MIS-HEMTs exhibit a threshold voltage (VTH) of 0.6 V, a peak transconductance of \sim193~mS/mm, a small hysteresis of 0.04 V in linear region characterized by a pulse-mode current-voltage measurement, and significantly suppressed current collapse under high-drain-bias switching conditions. X-ray photoelectron spectroscopy and secondary ion mass spectrometry analyses manifest that the negatively charged F ions penetrating into the (Al)GaN barrier layer serve as the primary VTH modulation mechanism, whereas the F ions in the fluorinated LLO film form chemical bonds with La/Lu atoms and become charge-neutral. The suppressed current collapse is verified as an advantageous byproduct of the F plasma ion implantation that also fluorinated the SiNx sidewalls in the vicinity of the gate electrode, and therefore, suppress electron injection to the gate-drain access region. [ABSTRACT FROM AUTHOR]

In this paper, we demonstrate a 253% improvement in the off-state breakdown voltage (BV) of the lattice-matched \In0.17\Al0.83 \N/GaN high-electron-mobility transistors (HEMTs) by using a new Schottky-contact technology. Based on this concept, the Schottky-source/drain and Schottky-source (SS) InAlN/GaN HEMTs are proposed. The proposed InAlN/GaN HEMTs with an LGD of 15 \mu\m showed a three-terminal BV of more than 600 V, while the conventional InAlN/GaN HEMTs of the same geometry showed a maximum BV of 184 V. Without using any field plate, the BV of 650 V was measured in the SS InAlN/GaN HEMTs with LGD = \15\ \mu\m, which is the highest BV ever achieved on InAlN/GaN HEMT. The corresponding specific on-resistance (Rsp, on) is as low as 3.4 \m\Omega \cdot \cm^2. A BV of 118 V was also obtained in SS InAlN/GaN HEMTs with LGD = \1\ \mu\m, which is the highest BV in GaN-based HEMTs featuring such a short LGD with GaN buffer. The improvement of the BV relies on the effective suppression of source carrier injection into the GaN buffer under the SS due to the smooth metal morphology and elimination of metal spikes in the Schottky metallization. [ABSTRACT FROM AUTHOR]

Improvement of the AlGaN/GaN high-electron mobility transistor's (HEMT's) off -state breakdown voltage is achieved by implanting ^19\F^+ ions at an energy of 50 keV and dose of \1 \times \10^12\ \cm^-2 under the gate region using \BF3 as the source. The charge state of the implanted fluorine ions changes from positive to negative in the AlGaN/GaN structure because of fluorine's strong electronegativity. The negative-charged fluorine ions at the back side of the two-dimensional electron gas can raise the energy barrier of the GaN buffer layer under the channel, effectively blocking the current injected from the source to the high-field region of the GaN channel when the HEMT is biased at off-state. The source-injected electrons, if not blocked, could flow to the high-field region and initiate a premature three-terminal off-state breakdown in a conventional AlGaN/GaN HEMT. A 38% improvement of the three-terminal off-state breakdown voltage and 40% improvement of the power figure-of-merit VBD-off^2/Ron are achieved in the enhanced back barrier HEMT. [ABSTRACT FROM AUTHOR]

High-frequency and high-temperature dynamic performance of plasma-enhanced atomic layer deposition AlN-passivated enhancement-mode GaN metal–insulator–semiconductor high electron mobility transistors (MIS-HEMTs) has been investigated under hard switching conditions. Low dynamic ON-resistance ( $R_{{\mathrm{{\scriptscriptstyle ON}}}})$ degradation with small frequency dispersion and weak temperature dependence is obtained. The effectiveness of AlN passivation in suppressing current collapse is proved even under hard switching operations, which, according to other reports of SiNx-passivated devices, could worsen the dynamic $R_{{\mathrm{{\scriptscriptstyle ON}}}}$ degradation due to the trapping of additional hot electrons. [ABSTRACT FROM AUTHOR]

This letter reports a GaN high-electron mobility transistor (HEMT) with reduced current collapse using a multicycle combined plasma-free ozone oxidation and wet surface treatment before Si3N4 passivation. The surface oxide and decomposed layers could be effectively removed and a perfect AlGaN surface is obtained after the treatment. Pulsed $IV$ and RF power measurement indicate that the current collapse is greatly suppressed due to the removal of imperfect surface layer and damage free nature, providing an effective surface treatment method to improve the effect of passivation in GaN HEMT. [ABSTRACT FROM AUTHOR]

In this letter, we report high-performance enhancement-mode (E-mode) Al2O3/AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs) fabricated with high-temperature low-damage gate recess technique. The high-temperature gate recess is implemented by increasing the substrate temperature to 180 °C to enhance the desorption of chlorine-based etching residues during the dry etching of AlGaN barrier. High-crystal-quality Al2O3 gate dielectric was grown by atomic-layer deposition using O3 as the oxygen source to suppress hydrogen-induced weak bonds. The fabricated E-mode MIS-HEMTs exhibit a threshold voltage of 1.6 V, a pulsed drive current of 1.13 A/mm, and very low OFF-state standby power of 6.8 \times 10^\mathrm -8 W/mm at V\mathrm {GS} =0 V and V\mathrm {DS} =30 V. At 4 GHz and in pulse-mode operation, the output power density and power-added efficiency were measured to be 5.76 W/mm and 57%, both of which are the highest for GaN-based E-mode MIS-HEMTs reported to date. [ABSTRACT FROM AUTHOR]

In this letter, silicon nitride (SiNx) film deposited at 780 °C by low-pressure chemical vapor deposition (LPCVD) was employed as gate dielectric for GaN-based metal–insulator–semiconductor high-electron-mobility transistors. The LPCVD-SiNx exhibit improved gate dielectric performance than the plasma enhanced chemical vapor deposition-SiNx, including smaller forward and reverse gate leakage, and higher forward gate breakdown voltage. [ABSTRACT FROM AUTHOR]

Al2O3/AlGaN/GaN enhancement-mode metal-isolator-semiconductor high-electron-mobility transistor (MIS-HEMT) featuring a partially recessed (Al) GaN barrier was realized by a fluorine plasma implantation/etch technique. By properly adjusting the RF power driving the fluorine plasma, the fluorine plasma is able to produce two desirable results: 1) a well-controlled slow dry etching for gate recess and 2) implanting fluorine ions into the AlGaN barrier. The fluorine ions become negatively charged in the barrier layer and induce a positive shift in the threshold voltage. The proposed MIS-HEMT exhibits a threshold voltage ( V\mathrm {\mathbf {TH}}) of +0.6 V at a drain current of 10~\mu \textA /mm, a maximum drive current of 730 mA/mm, an ON-resistance of 7.07~\Omega \,\cdot \, mm, and an OFF-state breakdown voltage of 703 V at an OFF-state drain leakage current of 1~\mu \text{A} /mm. From room temperature to 200 °C, the device exhibits a small negative shift of V_{\mathrm {\mathbf {TH}}}$ ( $\sim 0.5$ V) that is attributed to the high-quality dielectric/F-implanted-(Al) GaN interface and the partially recessed barrier. [ABSTRACT FROM AUTHOR]

We report a high-performance normally-off Al2O3/AlN/GaN MOS-channel-high electron mobility transistor (MOSC-HEMT) featuring a monocrystalline AlN interfacial layer inserted between the amorphous Al2O3 gate dielectric and the GaN channel. The AlN interfacial layer effectively blocks oxygen from the GaN surface and prevents the formation of detrimental Ga-O bonds. Frequency-dispersion in C–V characteristics and threshold voltage hysteresis are effectively suppressed, owing to improved interface quality. The new MOSC-HEMTs exhibit a maximum drain current of 660 mA/mm, a field-effect mobility of 165 cm \(^{2}\) /V \(\cdot \) s, a high on/off drain current ratio of \(\sim 10^{10}\) , and low dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

This letter reports a 0.2-\mum gate AlGaN/GaN high-electron-mobility transistors (HEMTs) on an Si substrate passivated with an AlN/SiNx (4/20 nm) stack layer. The 4-nm-thick AlN was grown by plasma-enhanced atomic-layer-deposition. The AlN/SiNx-passivated HEMTs exhibit a high maximum drain current of 930 mA/mm, an three-terminal OFF-state breakdown voltage (BVDS) of 119 V, and a small threshold voltage shift of 130 mV in a wide drain bias range (VDS=3-24~V). Owing to the additional positive polarization charge in the AlN passivation layer, the access resistance Rs in the GaN-on-Si HEMTs is significantly reduced while maintaining small parasitic gate-drain capacitance Cgd, contributing to a high power-gain cutoff frequency fMAX of 182 GHz and a high Johnson's figure of merit of BVDS\times f\,T of 6.43\times 10^12~V/s simultaneously. The accuracy of the RF performance is verified by a small signal modeling based on measured S-parameters. [ABSTRACT FROM AUTHOR]

We report an in situ low-damage pre-gate treatment technology in an atomic layer deposition (ALD) system prior to the ALD-Al2O3 deposition, to realize high-quality Al2O3/III\-nitride (III-N) interface. The technology effectively removes the poor quality native oxide on the III-N surface while forming an ultrathin monocrystal-like nitridation interlayer (NIL) between Al2O3 and III-N surface. With the pre-gate treatment technology, high-performance Al2O3(NIL)/GaN/AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors are demonstrated, exhibiting well-behaved electrical characteristics including suppressed gate leakage current, a small subthreshold slope of \sim64~mV/dec, and a small hysteresis of \sim0.09~V. [ABSTRACT FROM AUTHOR]

In this letter, 600-V normally-OFF SiNx/AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistor (MIS-HEMT) is reported. Normally-OFF operation and low OFF-state gate leakage are obtained by using fluorine plasma ion implantation in conjunction with the adoption of a 17-nm SiNx thin film grown by plasma-enhanced chemical vapor deposition as the gate insulator. The normally-OFF MIS-HEMT exhibits a threshold voltage of +3.6~V, a drive current of 430 mA/mm at a gate bias of 14 V, a specific ON-resistance of 2.1 m\Omega\cdotcm^2 and an OFF-state breakdown voltage of 604 V at a drain leakage current of 1 \muA/mm with VGS=0~\rm V, and the substrate grounded. Effective current collapse suppression is obtained by AlN/SiNx passivation as proved by high-speed pulsed I\--V and low-speed high-voltage switching measurement results. [ABSTRACT FROM AUTHOR]

This letter reports a normally-OFF Al2O3/GaN gate-recessed MOSFET using a low-damage digital recess technique featuring multiple cycles of plasma oxidation and wet oxide removal process. The wet etching process eliminates the damage induced by plasma bombardment induced in conventional inductively coupled plasma dry etching process so that good surface morphology and high interface quality could be achieved. The fully recessed Al2O3/GaN MOSFET delivers true enhancement-mode operation with a threshold voltage of +1.7~V. The maximum output current density is 528 mA/mm at a positive gate bias of 8 V. A peak field-effect mobility of 251 cm^2/V\cdots is obtained, indicating high-quality Al2O3/GaN interface. [ABSTRACT FROM AUTHOR]

An effective passivation technique that yields low off-state leakage and low current collapse simultaneously in high-voltage (600-V) AlGaN/GaN high-electron-mobility transistors (HEMTs) is reported in this letter. The passivation structure consists of an AlN/\SiNx stack with 4-nm AlN deposited by plasma-enhanced atomic layer deposition and 50-nm \SiNx deposited by PECVD. The AlN/ \SiNx-passivated HEMTs with a gate–drain distance of 15 \mu\m exhibit a high maximum drain current of 900 mA/mm, a low off-state current of 0.7 \mu\A/mm at VDS = \600\ \V, and a steep subthreshold slope of 63 mV/dec. Compared with the static on-resistance of 1.3 \m\Omega \cdot \cm^2, the dynamic on-resistance after high off-state drain bias stress at 650 V only increases to 2.1 \m\Omega \cdot \cm^2. A high breakdown voltage of 632 V is achieved at a drain leakage current of 1 \mu\A/mm . [ABSTRACT FROM PUBLISHER]

We demonstrate high-voltage depletion-mode and enhancement-mode (E-mode) AlGaN/GaN high-electron-mobility transistors (HEMTs) on a GaN-on-silicon-on-insulator (SOI) platform. The GaN-on-SOI wafer features GaN epilayers grown by metal–organic chemical vapor deposition on a p-type (111) Si SOI substrate with a p-type (100) Si handle wafer. Micro-Raman spectroscopy significantly reveals reduced stress in the GaN epilayers, which is a result expected from the compliant SOI substrate. E-mode HEMTs fabricated by fluorine plasma implantation technique deliver high on/off current ratio (\10^8-\10^9), large breakdown voltage (1471 V with floating substrate), and low on-resistance (3.92 \m\Omega\cdot \cm^2). [ABSTRACT FROM PUBLISHER]

The physical mechanism of passivation of AlGaN/GaN HEMTs by AlN thin film prepared with plasma-enhanced atomic layer deposition (PEALD) is investigated by characterizing \Ni- \Al2\O3/\AlN-\GaN/\AlGaN/\GaN metal–insulator–semiconductor (MIS) diodes. The dielectric stack \Al2\O3/\AlN (13/2 nm) exhibits similar capability in suppressing the current collapse in AlGaN/GaN HEMTs as the 4-nm PEALD-AlN thin film used in our previous work but delivers much lower vertical leakage to facilitate the capacitance–voltage characterizations. Exceptionally large negative bias ( < -\8\ \V) is required to deplete the 2-D electron gas in the MIS diode's C– V measurement. By virtue of quasi-static C–V characterization, it is revealed that positive fixed charges of \sim\3.2 \times \10^13\ \e/\cm^2 are introduced by the PEALD-AlN. The positive fixed charges are suggested to be polarization charges in the monocrystal-like PEALD-AlN. They can effectively compensate the high-density slow-response acceptor-like interface traps, resulting in effective suppression of current collapse. [ABSTRACT FROM PUBLISHER]

On a GaN smart power integrated-circuit platform, a monolithically integrated gate-protected high-voltage AlGaN/GaN enhancement-/depletion-mode high-electron mobility transistor (HEMT) has been proposed. It can sustain large input gate voltage swing (> 20 V) with enhanced safety (no gate failure observed) and improved reliability (no observable shifting of the threshold voltage), and the breakdown voltage is not sacrificed. Such a protection scheme with a wide input gate bias range also facilitates simple and reliable connections between the gate driver circuits and the power switches without the level shifter circuits for conventional GaN Schottky gate power HEMTs. [ABSTRACT FROM AUTHOR]

Vertical leakage/breakdown mechanisms in AlGaN/GaN high-electron-mobility transistors grown on low-resistivity p-type (111) Si substrate are studied by temperature-dependent current–voltage (I–V) measurements. It is found that the top-to-substrate vertical breakdown voltage (BV) is dominated by the space-charge-limited current conduction involving both acceptor and donor traps in the GaN buffer/transition layer. From the temperature-dependent transient backgating measurements, the acceptor level at EV + \543\ \meV and the donor level at EC-616 meV were identified. [ABSTRACT FROM AUTHOR]

A high-\kappa\ \LaLuO3 (LLO) thin film is successfully incorporated into AlGaN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) as the gate dielectric. The LLO–AlGaN/GaN MISHEMTs fabricated with a planar process exhibit a high ION/IOFF of \10^9, a maximum drain current of 820 mA/mm at VGS = 3\ \V, a peak transconductance (Gm) of \sim192 mS/mm, and a steep subthreshold slope (SS) of \sim73 mV/dec. [ABSTRACT FROM PUBLISHER]

An effective passivation technique for AlGaN/GaN high-electron-mobility transistors (HEMTs) is presented. This technique features an AlN thin film grown by plasma-enhanced atomic layer deposition (PEALD). With in situ remote plasma pretreatments prior to the AlN deposition, an atomically sharp interface between ALD-AlN and III-nitride has been obtained. Significant current collapse suppression and dynamic ON-resistance reduction are demonstrated in the ALD-AlN-passivated AlGaN/GaN HEMTs under high-drain-bias switching conditions. [ABSTRACT FROM AUTHOR]

In this letter, enhancement-mode (E-mode) AlGaN/GaN high electron mobility transistors (HEMTs) were demonstrated based on lateral scaling of the 2-D electron gas channel using nanochannel array (NCA) structure. The NCA structure consists of multiple parallel channels with nanoscale width defined by electron-beam lithography and dry etching. Because of the improved gate control from the channel sidewalls and partially relaxed piezoelectric polarization, the fabricated 2 \mu\m-gate-length NCA-HEMT with a nanochannel width of 64 nm showed a threshold voltage of +0.6 V and a higher extrinsic transconductance of 123 mS/mm, compared to -1.6 V and 106 mS/mm for the conventional HEMT with \mu \m-scale channel width. The scaling of threshold voltages, peak transconductance, and gate leakage as a function of the nanochannel width were investigated. Small-signal RF performance of NCA-HEMTs were characterized for the first time and compared with those of conventional HEMTs. [ABSTRACT FROM AUTHOR]

In this letter, we present the deployment of Schottky source/drain (SSD) in InAlN/GaN metal–insulator–semiconductor high-electron-mobility transistors (MISHEMTs) for off-state breakdown voltage improvement. The improved breakdown voltage relies on the suppression of electron injection into the buffer under the Schottky source contact. A VBD of 460 V is obtained in an SSD MISHEMT with an LGD = \10\ \mu\m, at a 170% improvement compared with that of the control MISHEMT featuring ohmic source/drain. Despite the SSD contacts, an SSD MISHEMT with a gate length of 1 \mu\m exhibits a respectable drain current density of 416 mA/mm and a transconductance of 113 mS/mm. [ABSTRACT FROM PUBLISHER]

The Schottky-source forward current–voltage characteristics were measured and analyzed in a recently reported AlGaN/GaN metal–2-D-electron-gas tunnel junction field-effect transistor (FET) (TJ-FET) in order to characterize the effective Schottky barrier height (SBH) and its gate bias dependence. The SBHs were extracted and found to be gate bias dependent, varying from 0.57 eV at VGS = - \0.5\ \V to 0.3 eV at VGS = \1\ \V. This gate-induced Schottky barrier lowering (SBL) effect is explained by the image-charge effect. A 2-D device simulation is carried out to analyze the SBL effect and is shown to be in good agreement with the experiment results. The larger SBH at lower gate voltage enables off -state blocking, while the lower SBH at higher gate voltage leads to high on -state current driving capability in the AlGaN/GaN TJ-FETs. [ABSTRACT FROM PUBLISHER]

Kink effects are studied in conventional AlGaN/GaN high-electron-mobility transistors by measuring their current-voltage characteristics with various bias sweeping conditions at drain and gate terminals. It is found that the kink effect is induced by drain and gate pumping. The magnitude of kink is directly related to the maximum drain voltage and current levels during on-state operation. The hot electrons in the 2-D electron gas channel generated under high drain bias could be injected into the adjacent epitaxial buffer layer where they can be captured by donor-like traps. Hot electron trapping and the subsequent field-assisted de-trapping is suggested to be the dominant mechanism of kink generation in the studied device. The extracted activation energy of the traps accounting for the kink effect is 589 \pm 67 meV from temperature-dependent transient measurement, and is close to the energy of the E2 trap widely reported in GaN layers. [ABSTRACT FROM AUTHOR]

We present the first AlGaN/GaN tunnel-junction FETs (TJ-FETs) featuring a metal–2-D-electron-gas (2DEG) Schottky tunnel junction at the source. The control of the source-to-drain current flow is realized through a gate-controlled tunnel junction instead of a gate-controlled 2DEG channel. The TJ-FETs exhibit normally off operation (Vth = +\1.35\ \V) in an otherwise normally on as-grown sample. The unique high-density 2DEG in AlGaN/GaN heterostructures enables the formation of a Schottky tunnel barrier with nanometer-scale barrier thickness even with a large Schottky barrier height (e.g., \sim0.8 eV). In the off state, the source Schottky junction provides natural reverse-blocking capability, resulting in significant leakage reduction and low off-state current. A drive current of 326 mA/mm, a high ION/IOFF ratio (\10^10), and a low subthreshold swing (89 mV/dec) are obtained. [ABSTRACT FROM PUBLISHER]

A high-performance bootstrapped comparator operating with a single-polarity power supply is demonstrated for GaN high-temperature electronics applications. The comparator features monolithically integrated enhancement-mode (E-mode) and depletion-mode (D-mode) AlGaN/GaN HEMTs. The tail current source uses an E-mode HEMT, enabling single-polarity power supply. The E-mode input stage could cover a wide voltage comparison range (from 1 to 6 V) while the bootstrapped loads are implemented with D-mode HEMTs. At room temperature, the comparator delivers a voltage gain as high as 79 V/V and a unity-gain bandwidth of 206 MHz. At 250 ^ \circ\C, a maximum voltage gain of 40 V/V and a unity-gain bandwidth of 84 MHz are obtained. [ABSTRACT FROM AUTHOR]