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In this paper, we investigate the characteristics of short-term and long-term synaptic plasticity in a Si-based field-effect transistor-type memory device. An Al2O3/HfO2/Si3N4 gate dielectric stack is used to realize short-term and long-term plasticity (STP/LTP). Si3N4 and HfO2 layers are designed to implement short-term and long-term memory, respectively. The mechanism of STP and LTP operation has been figured out by analyzing the device response to the potentiation and depression pulses. To investigate the STP operation, paired-pulse facilitation measurement is performed. The retention characteristic is also studied to validate the LTP property of the device. By investigating a device with an Al2O3/Si3N4 stack as a control device, it is shown that the HfO2 layer contributes to LTP in device with Al2O3/HfO2/Si3N4 stack. Thus, it is confirmed that STP and LTP operations can be implemented simultaneously in devices with an Al2O3/HfO2/Si3N4 stack. [ABSTRACT FROM AUTHOR]

In this paper, we reported a ferroelectric HfAlOx negative capacitor transistor with gate-stress (GS) engineering. Compared to control device, the HfAlOx transistor with GS engineering percentage of $\text{I}_{ \mathrm{\scriptscriptstyle ON}}$ enhancement and 27% $\text{V}_{T}$ reduction under the assistance of the negative capacitance (NC) effect. The orthorhombic phase transition played a crucial role in realizing the NC effect. From the results of the material analysis, the theoretical Landau simulation and electrical measurement, we demonstrated that the GS is favorable for inducing orthorhombic phase crystallization of HfAlOx and stabilizing the NC effect, which shows the potential for the application of advanced technology node. [ABSTRACT FROM AUTHOR]

In this paper, a novel insulated gate triggered thyristor with the Schottky barrier (SB-IGTT) is proposed for improved the repetitive pulse life and high-di/dt characteristics. Different from the conventional cathode shorted MOS-controlled thyristor (CS-MCT), an SB is specially imbedded to enlarge the effective turn-on area and enhance the electron–hole plasma spread during short duration pulse, which contributes significantly to relaxing the thermal concentration and improving the repetitive pulse life as well as achieves superior di/dt characteristics. The experimental results show that the proposed SB-IGTT continuously undergoes more than 220 000 shots at the pulse frequency of 5 Hz, yielding a $10\times $ longer repetitive pulse life than the conventional CS-MCT. Simultaneously, SB-IGTT performs a di/dt up to 120 kA/ $\mu \text{s}$ with peak current near 10 kA, increasing di/dt by about 20%. Improved repetitive pulse life and simultaneous superior di/dt characteristics indicate that the proposed SB-IGTT is suitable for repetitive pulse power applications. [ABSTRACT FROM AUTHOR]

In this paper, we propose a misaligned double-gate p-i-n impact ionization MOS (MIMOS) with a deliberate misalignment between the top and bottom gates. The presence of a misaligned bottom gate leads to band-to-band-tunneling of electrons at the source-intrinsic region interface and increases the number of carriers for impact ionization. The electric field redistribution provides a longer transport path for the carriers. Therefore, carriers gain higher kinetic energy, and the impact ionization rate is enhanced in the MIMOS. This results in a significantly lower avalanche breakdown voltage compared to conventional single-gate IMOS structure. Using calibrated 2-D simulations, we demonstrate that MIMOS exhibits a steep subthreshold slope (~6 mV/dec) at a significantly low-supply voltage of (${V}_{\text {DS}}= {0.59}$ V), which is ~48% lower than that of the corresponding single-gate IMOS (${V}_{\text {DS}}= {1.15}$ V). [ABSTRACT FROM AUTHOR]

In this paper, we have comprehensively studied the performance boosts of both nLDMOS and pLDMOS under the mechanical strain. The electrical properties of LDMOS under the uniaxial tensile and compressive strains along the channel direction are examined thoroughly. We find that the uniaxial tensile strain benefits the nLDMOS, and the uniaxial compressive strain benefits the pLDMOS. Because the mechanical strain affects carriers’ transportation in bulk Si and inverted channel distinctly, the strain effects are strongly correlated with the gate voltage, drain voltage, and devices’ dimensions. It is found that the LDMOS with the longer gate length is more preferred for the strain. The piezoresistance coefficients of both nLDMOS and pLDMOS under the uniaxial strain are evaluated for the first time. It is also shown that the mechanical strain can enhance the drain current without the degradation of the breakdown voltage, which suggests a downshift of the ON-resistance versus breakdown voltage curve. [ABSTRACT FROM AUTHOR]

In this paper, we simulated the effects of the source/drain extensions (SDEs) of the 7-nm strained SiGe n-type FinFETs and the random dopant fluctuations (RDFs) therein by TCAD tools. First, we simulated different SDE lengths and doping concentrations to examine their effects on the device characteristics. Second, we simulated the RDF in SDE to examine the device variability. Simulation results show that increasing the SDE length and decreasing the SDE doping concentration are beneficial for the device characteristics. For the device variability, increasing the SDE length and decreasing the SDE doping concentration reduce the threshold voltage variation ($\sigma {V}_{T}$), on-current variation ($\sigma {I}_{ \mathrm{\scriptscriptstyle ON}}$), and off-current variation ($\sigma {I}_{ \mathrm{\scriptscriptstyle OFF}}$). Therefore, the SDE optimization is critical for both the device performance and the device variability of the 7-nm FinFETs. [ABSTRACT FROM AUTHOR]

In this paper, the electron transport properties of a C3N nanoribbon-based field-effect transistor (FET) in the ballistic regime have been simulated. Using the density-functional theory (DFT) to obtain the band structures, we found that the armchair-edged C3N nanoribbons are semiconductors, and their bandgaps are determined by their widths, while the zigzag-edged ribbons present the metallic properties. We have carried out calculations to study the transport properties of armchair-edged C3N nanoribbon by using DFT combined with the nonequilibrium Green’s function. Our simulation results revealed that both bandgap and current on/off ratio are reduced as the width increasing. Moreover, the gate length, channel length, and ribbon’s width are found to have prominent influences on the transfer characteristics. The armchair-edged C3N nanoribbon-based FETs have the highest current on/off ratio of 106 and the ideal subthreshold swing of 61.2 mV/dec, which make it promising for potential applications of FET. [ABSTRACT FROM AUTHOR]

The reverse-conducting insulated gate bipolar transistor (RC-IGBT) has several benefits over a separate IGBT and diode solution and has the potential to become the dominant device within many power electronic applications; including, but not limited to, motor control, resonant converters, and switch-mode power supplies. However, the device inherently suffers from many undesirable design tradeoffs which have prevented its widespread use. One of the most critical issues is the snapback seen in the forward conduction characteristic which can prevent full turn-on of the device and result in the device becoming unsuitable for parallel operation (required in many high voltage modules). This phenomenon can be suppressed but at the expense of the reverse conduction performance. This paper provides an overview of the technical design challenges presented by the RC-IGBT structure and reviews alternative device concepts which have been proposed in literature. Analysis shows that these alternate concepts either present a tradeoff in performance characteristics, an inability to be manufactured, or a requirement for a custom gate drive. [ABSTRACT FROM AUTHOR]

This paper reports on the usefulness of shell-doped (SD) junctionless (JL) transistor architecture for operation as capacitorless dynamic random-access memory (1T-DRAM). SD topology overcomes the problem associated with shallower potential depth in heavily doped devices, thereby enhancing the retention time (RT) along with improved scalability. The use of a thinner shell for achieving high RT is beneficial as it reduces generation and recombination of holes. The results show that an undoped core region with shell thickness (${T}_{\textsf {Shell}}$) of 2 nm yields maximum retention. An SD (${N}_{\mathrm {d}}$) of $10^{18}$ cm $^{-\textsf {3}}$ attains RT of ~5.5 s and ~630 ms at 27 °C and 85 °C, respectively, whereas higher ${N}_{\textsf {d}}$ ($10^{19}$ cm $^{-\textsf {3}}$ shows RT of ~13ms at 85 °C for ${L}_{\textsf {g}} = \textsf {200}$ nm. SD JL transistor shows less degradation in RT with temperature. A 10 nm SD JL device with RT of ~11 ms at 85 °C demonstrates applicability as 1T-DRAM at shorter gate lengths. [ABSTRACT FROM AUTHOR]

The impact of varying the GaN channel layer thickness (${t}_{\text {ch}}$) in InAlGaN/AlN/GaN HEMTs with C-doped AlGaN back barriers is investigated. ${t}_{\text {ch}}$ was 50, 100, and 150 nm, and the gate length of the fabricated HEMTs ranged from 50 to 200 nm. It is found that short-channel effects (SCEs) are significantly mitigated with a small ${t}_{\text {ch}}$. For HEMTs with a gate length of 50 nm, the drain-induced barrier lowering changes from 40 to 93 mV/V as ${t}_{\text {ch}}$ is increased from 50 to 150 nm. On the other hand, it is shown that dispersive effects are more severe for a smaller ${t}_{\text {ch}}$ , as demonstrated by a sixfold increase in the dynamic ON-resistance for ${t}_{\text {ch}} = 50$ nm compared to ${t}_{\text {ch}} = 150$ nm. The tradeoff between dispersion and SCEs is reflected in large-signal measurements at 30 GHz. The 50-nm channel, mainly limited by dispersion, exhibits an output power of 3.5 W/mm. The thicker channels reach a maximum of around 5 W/mm, but for different gate lengths due to the difference in severity of the SCEs. This paper elucidates the interplay between SCEs and dispersion related to ${t}_{\text {ch}}$ , its consequences for the large-signal performance and for the limitation in downscaling of the gate length. [ABSTRACT FROM AUTHOR]

In this paper, we propose an adaptive quantization method that can easily transfer the weights, which are trained in software network with floating point operation, to the real synaptic devices in hardware-based neural networks and maintain high performance. An n-type gated Schottky diode is investigated as a synaptic device, and the conductance behavior of this device is modeled successfully. Max value normalization and $3\sigma $ normalization are applied to the weights trained with an accuracy of 98.29% on fully connected neural network ($784\times 256\times10$) using software network. Then, the weights are quantized using the adaptive quantization method and can be transferred by adjusting the number of identical pulses applied to the synaptic devices. After applying the adaptive quantization method, accuracy rates of 98.09% and 97.20% in MNIST classification are obtained for both max value normalization and $3\sigma $ normalization, respectively. The proposed quantization method works well even when there is nonideality of synaptic devices such as nonlinearity of conductance behavior, limited conductance levels, and variation of conductance. [ABSTRACT FROM AUTHOR]

In this paper, a dual-gate laterally double-diffused metal–oxide–semiconductor (DG-LDMOS) device with shallow trench isolation (STI) and sinker at the source side has been proposed. STI and sinker help to provide isolation and reduce the leakage current, respectively, in the device. This is an improvement over a single-gate (SG) LDMOS device when only one gate is used and no STI and sinker are there. The study of both the devices has been carried out using the ATLAS SILVACO simulator. In the simulation studies, all the dimensions and doping parameters of both devices have been kept the same except gate length and channel doping. The distance between two gates of DG-LDMOS device has been kept smaller. This has been done to overcome the island and overlapping issues. The simulation studies have shown a significant improvement in DG-LDMOS device parameters in comparison to the SG-LDMOS device. The DG-LDMOS device provides high breakdown voltage, low ON-resistance, high $f_{\sf {T}}$ and $f_{\sf {max}}$ , low drain-induced barrier lowering, and better output conductance as compared to conventional SG-LDMOS device. These features make the DG-LDMOS device an excellent candidate for RF applications. [ABSTRACT FROM AUTHOR]

In this paper, we propose a new statistical corner model for the precise variation analysis of CMOS logic gate delay. The conventional corner model includes pessimism in its prediction of delay variation as a result of inadequate statistical consideration of device characteristics. Therefore, to develop an accurate delay corner model, we analytically derive corner modeling targets for device characteristics, which are statistically shrunk when considering the variation and the correlation of transistor and parasitic resistance and capacitance (RC). Then, the derived targets are obtained by multiplying the conventional corner parameters using the newly proposed corner scaling factors. Simulation results verify that the corner model fitted to the proposed targets accurately predicts the three standard deviation limits of delay variation. To implement the parasitic RC aware delay corner in compact models of the process design kit, an artificial neural network is used to model the complex relationship between the parasitic RC and the delay corner model. The delay variations predicted by the proposed model match well with the Monte Carlo simulation results at various simulation conditions, unlike the conventional corner model, which introduces pessimism. [ABSTRACT FROM AUTHOR]

The state-of-the-art RF and millimeter-wave circuits design requires accurate prediction of the nonquasi-static (NQS) effects at high frequency for all levels of channel inversion. This paper provides a practical insight to help high-frequency performance assessment of ultrathin body and box fully depleted silicon-on-insulator MOSFETs through a powerful frequency normalization scheme. Frequency dependence of small signal characteristics derived from experimental S-parameters is analyzed and reveals that the transconductance efficiency (${g}_{\textsf {m}}/{I}_{\textsf {D}}$) concept, already adopted as a low-frequency analog figure-of-merit (FoM), can be generalized to high frequency, including under asymmetric operation. We report that the normalized frequency dependence of the generalized transadmittance efficiency (${y}_{\textsf {m}}/{I}_{\textsf {D}}$) FoM only depends on the mobility and inversion coefficient. In addition, this approach is also used to extract essential parameters such as the critical NQS frequency ${f}_{\textsf {NQS}}$. [ABSTRACT FROM AUTHOR]

A comprehensive quantum transport study of ultrathin-body silicon double-gate pMOSFETs with gate length ${L}_{\textsf {g}}= \textsf {14}$ , 10, and 7 nm is performed by in-house developed nonequilibrium Green’s function solver employing the six-band ${k} \cdot {p}$ Hamiltonian. The effects of channel length, body thickness, as well as confinement and transport crystal orientations are studied systematically. Both ${I}$ – ${V}$ and ${C}$ – ${V}$ characteristics are analyzed in this paper. Furthermore, the CMOS performance benchmarking results, such as switching delay, energy consumption, and their product, are calculated with the influence of parasitic resistances and capacitances treated in an appropriate way. It is found that the crystal orientation effect on drive current is significant at both long and short channel lengths, while its effect on effective capacitance is more observable at ${L}_{\textsf {g}} = \textsf {7}$ nm. The drive current at ${L}_{\textsf {g}} = \textsf {14}$ nm and ${L}_{\textsf {g}} = \textsf {7}$ nm can be well explained by average ballistic hole velocity and source-to-drain tunneling ratio, respectively. Meanwhile, the effective capacitance is not only determined by the density of states but also affected by the distribution of holes in the confined direction. Both intrinsic and extrinsic performance assessments suggest that (001)/[100] and (110)/[001] are the optimal confinement/transport crystal orientation configurations at ${L}_{\textsf {g}}= \textsf {7}$ nm, while ${(}\textsf {110}{)}/[\overline {1}\textsf {10}]$ and ${(}\textsf {110})/[\overline {1}\textsf {11}]$ are the best choices at longer gate lengths. As ${L}_{\textsf {g}}$ shrinks, both intrinsic and extrinsic performances will be better at a scaled body thickness. [ABSTRACT FROM AUTHOR]

In this paper, analytical gate capacitance models for a large-signal compact model of AlGaN/GaN high-electron mobility transistors are proposed. Different from the MOSFET devices, different depletion regions on either side of the gate are fully considered for high-voltage GaN devices. The depletion regions are bias-dependent to implement the capacitance models into the large-signal compact model. A transfer function is proposed to characterize the switching behavior of the capacitances between on- and off-states, which is essential to describe all the states of a device, for example, operating at Class-B. Different from previous works, the current saturation phenomenon is taken into account in determining the intrinsic capacitances which are induced by nonstatic channel charge. The capacitance models can be easily implemented into the virtual-source-based model to accurately predict the S-parameters and large-signal output characteristics. [ABSTRACT FROM AUTHOR]

In this paper, we have devised on shallow trench isolation (STI) design considering leakage current (${I}_{ \mathrm{\scriptscriptstyle OFF}}$) in Bulk/silicon on insulator (SOI) FinFET and vertical FET (VFET). The ${I}_{ \mathrm{\scriptscriptstyle OFF}}$ tendency is considered in terms of the interface trap density (${D}_{\textsf {it}}$) difference depending on the STI material type and STI thickness. In the case of Bulk FinFET, the STI design for each of high performance (HP) and low power (LP) is presented. On the other hand, in the case of SOI FinFET and VFET, STI designs which do not distinguish HP/LP are presented. Max lattice temperature (${T}_{\textsf {L,max}}$)/thermal resistance (${R}_{\textsf {th}}$)/on current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) degradation rate according to STI design in each structure are also analyzed. Finally, we compare the hot carrier injection (HCI)/bias temperature instability (BTI) lifetime as a function of the device temperature which is varied depending on STI design. In conclusion, our proposed STI design effectively reduces the self-heating effect in each structure and increases the HCI/BTI lifetime accordingly. [ABSTRACT FROM AUTHOR]

Almost complete suppression of dynamic ON-resistance in AlGaN/GaN high-electron-mobility transistors is obtained by proton irradiation. In this paper, both small and large power transistors are characterized before and after 3-MeV proton irradiation at different fluences. The irradiated devices show a high robustness and for specific fluences unaltered threshold voltage and static ON-resistance. However, for fluences higher than 1013 cm−2, the dynamic ON-resistance is almost completely suppressed at 600 V and $T$ = 150 °C. After irradiation, a measurable increase in OFF-state leakage current is observed, indicating an increase in the unintentionally doped (UID) GaN layer conductivity. We propose a technology computer-aided design supported model in which this conductivity increase leads to an increased deionization rate, ultimately reducing the dynamic ON-resistance. [ABSTRACT FROM AUTHOR]

In this paper, a comparison of gate-all-around nanowire-FETs, nanoplate (NP)-FETs, and FinFETs was undertaken for the same areas of not only the gate metal but also the silicon channel, assuming the same conditions regarding the parasitic components. It is known that an NP-FET structure not only improves the delay performance but also enhances the immunity to short-channel effects. In addition, it is found that the use of a dual-k spacer with an NP-FET further improves the on-state as well as the off-state performances. [ABSTRACT FROM AUTHOR]

This paper presents the analyses on the self-sustained oscillation of superjunction MOSFET intrinsic diode. At first, the characteristics of the self-sustained oscillation for the superjunction MOSFET intrinsic diode are identified by the double-pulse switching test. The test results show that the self-sustained oscillation with significant self-amplification phenomenon can be triggered during the reverse recovery transient of superjunction MOSFET intrinsic diode. Based on the Sentaurus TCAD simulation, the self-sustained oscillation is reproduced. The simulation results reveal the root cause of the self-sustained oscillation. Due to the snappy reverse recovery of superjunction MOSFET intrinsic diode, the steep slope of diode snap off current can generate high voltage across the common source inductance, which drives the gate–source voltage and turns on the high-side MOSFET. The unexpected MOSFET turn-on can, in return, enhance the steepness of the current slope when the diode snap off. This leads to a positive feedback process and self-sustained oscillation is generated. In the end, based on the theoretical analyses and experimental results, the necessary methods that can suppress the oscillation are presented. [ABSTRACT FROM AUTHOR]

This paper proposes a synaptic device based on charge-trap flash memory that has good CMOS compatibility and superior reliability characteristics compared with other synaptic devices. Using hot-electron injection and hot-hole injection, we designed operation methods to implement gradual conductance modulation and spike-timing-dependent plasticity. We demonstrate the feasibility of the device for neuromorphic applications through both a device-level technology computer-aided design simulation and a system-level MATLAB simulation. For the first time, we also propose a 3-D stacked synapse array and present the structure, operation, and process methods. The proposed array architecture features a small area and low process cost and could be a novel solution for neuromorphic systems for implementing deep neural networks. [ABSTRACT FROM AUTHOR]

Feedback field-effect transistor (FBFET), an alternative switching device, has received attention due to its ideal steep switching feature. By utilizing the positive feedback phenomenon, the total amount of electrons and holes contributing to drain current is sharply surged. Although the device has conspicuous subthreshold slope (SS) properties, advanced research for structure and performance of it is lacking. In this paper, single-gated and spacer-less silicon-on-insulator (SOI) FBFET with extremely steep switching (~1 mV/decade) characteristic is studied in various aspects; SS attribute, performance variation of scaled FBFET, the impact of structural variation, the gate margin for the device layout, and the hysteresis window. The prospect of SOI FBFET as a future candidate for CMOS logic application is investigated in detail. [ABSTRACT FROM AUTHOR]

The prerequisite of gate oxide local thinning (OLT) effect for subthreshold swing (SS) reduction to sub-60 mV/decade on charge-coupled metal–insulator–semiconductor (MIS) tunnel transistor is specified in this paper. The OLT process is employed by positive voltage stress, which is regarded as an efficient method to create a soft breakdown of oxides. The gate OLT process dramatically reduces the SS of the device, for instance, from the minimum SS of 79.31 to 9.7 mV/decade. Meanwhile, average SS of 28.22 mV/decade for over two current decades is acquired after the gate OLT process. The enhanced efficiency for minority carrier supply under gate oxide is responsible for the amelioration. The physical mechanism is proposed as the OLT spot-induced energy lateral transport and reduction of the energy barrier for minority carrier supply. The mechanism is then clarified by 2-D TCAD simulation. The extremely low SS and its physical insights of gate OLT effect on charge-coupled MIS tunnel transistor are believed beneficial for future developments on low-SS-related devices. [ABSTRACT FROM AUTHOR]

Variability is a challenge for future scaling as process dimensions reduce. The emerging 3-D sequential stacking technology is more than Moore’s scaling alternative. The 3-D design flow requires the partitioning of the netlist between the tiers. This paper presents the variability analysis of circuits partitioned into different levels. A comparison among local and global variations effects on ring oscillators (ROs) and SRAM is demonstrated. The across-chip variations and correlation range are shown as a critical point for the 3-D very large-scale integrated circuits, where the local variability is dominant. The correlations between devices due to the distances or the allocation into different tiers are directly taken into account in the SPICE model due to a statically unified model applied to 3-D circuits based on Monte Carlo simulations. Design wise, the 3-D integration can further decrease the circuit variability as shown in RO output frequency and SRAM static noise margin. [ABSTRACT FROM AUTHOR]

A recently reported zero impact ionization and zero subthreshold swing device Z2FET is a promising candidate for capacitor-less dynamic random access memory (DRAM) memory cell. In the memory operation, data retention time determines refresh frequency and is one of the most important memory merits. In this paper, we have systematically investigated the Z2FET retention time based on a newly proposed characterization methodology. It is found that the degradation of HOLD “0” retention time originates from the gated-silicon on insulator (SOI) portion rather than the intrinsic-SOI region of the Z2FET. Electrons accumulate under front gate and finally collapse the potential barrier turning logic “0”–“1.” It appears that Shockley–Read–Hall (SRH) generation is the main source for electrons accumulation. Z2FET scalability has been investigated in terms of retention time. As the Z2FET is downscaled, the mechanism dominating electrons accumulation switches from SRH to parasitic injection of electrons from the cathode. The results show that the downscaling of Lg has little effect on data “0” retention, but Lin is limited to ~125 nm. An optimization method of the fabrication process is proposed based on this new understanding, and Lin can be further scaled down to 75 nm. We have demonstrated by 2-D TCAD simulation that Z2FET is a promising DRAM cells’ candidate particularly for Internet-of-Things applications. [ABSTRACT FROM AUTHOR]

Several optical and electrical methods have been developed to thermally characterize GaN high-electron mobility transistors (HEMTs) under DC operation. Gate resistance thermometry (GRT) has proven to be an inexpensive and reliable method to estimate the peak temperature. The complex Joule heating profile of a HEMT, however, is highly bias dependent, and its temperature profile under RF conditions may vary compared to the profile generated under DC operation. Evaluating the thermal performance of HEMTs under RF operation is thus necessary to quantify any differences between these two modes of operation. Implementing a differential probe, this paper highlights the capability of using GRT to measure accurately the temperature of GaN/Si HEMTs under RF operation. A larger gate-to-gate spacing is shown to decrease the overall temperature rise, while a linear correlation is found between the power-added efficiency and the junction temperature. The effect of the baseplate temperature on the device’s thermal performance both under steady-state and RF operations is presented. Overall, at a given power density and baseplate temperature, the RF temperature rise is shown to appear lower than its equivalent temperature under DC biasing. [ABSTRACT FROM AUTHOR]

In this paper, we investigate a vertical gate-based elevated tunnel source (TS) FET structure with and without a vertical n+ pocket and compare its performance with a lateral p-n-i-n TS (LTS) FET. The lined arrangement of gate not only provides a performance boosting as expected but it further allows the flexibility to minimize the degradations at higher pocket doping using source elevation. The vertical gate and pocket alignment overcome the full-depletion constraint of the LTS FET and maintain a better subthreshold swing (SS) over a higher range of pocket doping and width. An optimized average SS as low as ~26 mV/dec is achieved over five decades of current which is improved by 58% and 67%, respectively, as compared to the LTS and p-i-n tunnel field-effect transistors (TFETs) with an on-current enhancement of one order and $\sim 17\times $ , respectively. Furthermore, the gate-to-drain capacitance (${C} _{\textsf {GD}}$) in elevated source structures is a highly sensitive function of the pocket doping and can be significantly reduced by tuning the source elevation length ${L} _{\textsf {CV}}$ at higher pocket doping. At the same pocket conditions, a one order reduction in ${C} _{\textsf {GD}}$ is achieved with respect to the lateral configuration without compromising the intrinsic delay (${C} _{\textsf {GD}}\times {V} _{\textsf {DD}}/{I} _{\textsf {ON}})$. The circuit-level investigations show that due to the, otherwise, higher ${C} _{\textsf {GD}}$ in the LTS FET, the switching delay remains unaffected by the on-current boosting caused by higher pocket doping. However, it is drastically improved by ~23% in elevated source structures at a change from $4\times 10^{\textsf {19}}$ to $5\times 10^{\textsf {19}}$ /cm3. A faster switching delay ($\tau _{\textsf {p}}$) of ~116 ps is achieved at a ~33% reduced device base area. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, the record high-performance top-gated graphene technology platform is used for electrostatic discharge (ESD) physics exploration while investigating the implications of various design and technology options. Impact of diffusive versus ballistic carrier transport on the failure mechanism in top-gate as well as back-gate graphene FET (GFET) is investigated. A unique contact limited failure in graphene transistors is reported. Physical insights on current saturation in GFET and unique step-by-step failure in dielectric capped transistors are presented for the first time. Moreover, device degradation under ESD timescales and its implications on current saturation are revealed. Finally, the influence of various top-gate designs on the ESD performance is reported. New physical insights and matured GFET technology has eventually enabled record high ESD robustness. [ABSTRACT FROM AUTHOR]

We present the latest developments in Advance SPICE Model for GaN (ASM GaN) HEMTs in this paper. The ASM GaN model has been recently selected as an industry-standard compact model for GaN radio frequency (RF) and power devices. The core surface-potential calculation and the modeling of real device effects in this model are presented. We discuss the details of the nonlinear access region model and enhancement in this model to include a physical dependence on barrier thickness. We also present the novel model feature of configurable field-plate modeling and discuss the extraction procedure for the same. New results with the ASM GaN model on high-frequency and enhancement-mode GaN power devices are also presented. [ABSTRACT FROM AUTHOR]

The degradations of electrical parameters for double-trench silicon carbide (SiC) power metal-oxide-semiconductor field-effect transistors (MOSFETs) under repetitive avalanche stress are investigated in this paper. The injection of hot holes into the bottom oxide of the gate trench during avalanche process is demonstrated to be the dominant degradation mechanism, while the channel is rarely influenced by the stress. The injected holes attract extra electrons in the SiC layer along the SiC/SiO2 interface, decreasing the ON-state drain–source resistance (${R}_{{dson}}$). Due to this reason, the threshold voltage (${V}_{{th}}$) of the device also reduces slightly. Moreover, other than static electrical parameters, dynamic characteristics including the gate–drain capacitance (${C}_{{gd}}$) and the switching characteristics of the device also degrade. After being stressed by repetitive avalanche stress, the depletion region beneath the bottom of the gate trench gets thinner, leading to the increase in ${C}_{{gd}}$ , which further influences the switching behaviors. The turn- ON and turn- OFF switching times of the device are calculated. It illustrates that the repetitive avalanche stress results in an obvious delay in the turn- OFF procedure, but hardly influences the turn- ON behaviors of the double-trench SiC MOSFET. [ABSTRACT FROM AUTHOR]

A lumped-circuit nonquasi-static (NQS) model, that is applicable for both large-signal transient simulations and a small-signal ac analysis, is developed in this paper. An improved physical equivalent circuit, capturing NQS effects in the millimeter waveband, is derived using a transmission line model, by incorporating the high-frequency longitudinal gate electrode and a channel distributed RC network. The proposed model is implemented in a BSIM-BULK MOSFET model and validated with dc and RF data, obtained from technology computer-aided design device simulations and experimental data. The proposed model is in very good agreement with the data up to ${50}{f}_{t}$. The transient currents, for a gate-voltage switching rate of ${5}\times {10}^{{10}}$ V/s, show excellent match with the data. The dc, transient, and ac simulations using the proposed model are much faster than a 10-segmented MOSFET model. This shows that the proposed model is better than other computationally complex compact models, for most RF applications. [ABSTRACT FROM AUTHOR]

This paper illustrates the usefulness of the physics-based compact device models in investigating the impact of device behavioral nuances on the operation and performance of the circuits and systems. The industry standard MIT virtual source gallium nitride high electron-mobility transistor (GaN HEMT) (MVSG) model is used as the modeling framework to understand the operation of the GaN HEMTs and study the key device–circuit interactions in the GaN-based high-frequency and power conversion circuits. Details of the core model equations along with their physical underpinnings are presented along with the benchmark tests to verify the model’s convergence robustness and simulation accuracy. The usefulness of such a compact model in circuit design is highlighted through examples of the GaN-based high-voltage converter and RF-power amplifiers. It is shown that the slew-rates in hard-switched buck converters are determined by the dynamic charge distribution among the field plates in GaN HEMTs, indicating the importance of the device-level effect on circuit performance. Likewise, it is shown using the MVSG model that the performance metrics, such as drain efficiency and linearity, of the GaN RF-power amplifiers are heavily dependent on the device-level effects, such as access-region depletion, thermal effects, and charge-trapping effects. These GaN-based circuits designed using the MVSG model can be used as the example cases to demonstrate the importance of the accurate physical compact models in designing high performance circuits and systems in emerging technologies. [ABSTRACT FROM AUTHOR]

In this paper, several fundamental pseudo-CMOS digital circuits with n-type indium tin oxide-stabilized ZnO thin-film transistors (TFTs) were implemented and investigated. The optical transmittance of circuits varied from 77% to 92% throughout the visible wavelength band. Electrically, the operation frequency of inverters, nor gates, nand gates, D latches, and D flip flops were all found to exceed 10 kHz with a supply voltage of 10 V. Besides, 13-stage ring oscillators could be operated at 42 kHz with a propagation delay time of $0.92~\mu \text{s}$ when the supply voltage was set as 20 V. Among the state-of-the-art transparent designs, these proposed circuits based on the ITO-stabilized ZnO TFTs exhibited high-speed performance, which were promising as building blocks for transparent electronics with moderate frequency requirements. [ABSTRACT FROM AUTHOR]

In this paper, we describe an improved SPICE model for the negative capacitance field-effect transistor (NCFET). According to the law of conservation of charge, the model is built based on the relationship between the gate charge of the MOSFET and the charge reserved by the ferroelectric layer and includes the parasitic resistance and capacitance into consideration. Based on the model, the drain-induced barrier lowering (DIBL) and the negative resistance (NR) of the NCFET are analyzed. Finally, taking two well-known analog blocks (the current mirror and the latch comparator) for example, impacts of the DIBL effect and the NR property on analog circuit performances are discussed. Thanks to utilization of the NR feature, not only can impacts of the DIBL effect and the channel-length modulation (CLM) effect be alleviated to improve the mirroring accuracy, but also the comparison speed of the latch comparator be accelerated. [ABSTRACT FROM AUTHOR]

Silicon-based quantum computing has the potential advantages of low cost, high integration density, and compatibility with CMOS technologies. The detuning mechanism has been used to experimentally achieve silicon two-qubit quantum gates and programmable quantum processors. In this paper, the scaling behaviors and variability issues are explored by numerical device simulations of a model silicon quantum gate based on the detuning mechanism. The device physics of quantum gates modulation, tradeoff between device speed and quantum fidelity, and impact of variability on the implementation of a quantum algorithm are examined. The results indicate the attractive potential to achieve high speed and fidelity silicon quantum gates with a low operation voltage. To scale up, reducing the device variability and mitigating the variability effect are identified to be indispensable for reliable implementing a quantum computing algorithm with the silicon quantum gates based on the detuning mechanism. A scheme to use the control electronics for mitigating the variability of quantum gates is proposed. [ABSTRACT FROM AUTHOR]

In this paper, we investigate the impact of spacer dielectrics on the ultrascaled silicon gate-all-around junctionless transistor in the ballistic regime based on the in-house 3-D quantum simulator that self-consistently solves mode-space nonequilibrium Green function formalism and Poisson’s equation. Then, the impact of device parameters, such as lengths of source/drain region and channel, channel width, and nanowire direction, on the static performance is also discussed in detail. An available range of spacer dielectric constant is further selected. Results show that the high-k spacer introduced in the ultrascaled junctionless transistor can effectively enhance the direct-current performance of the device and suppress the variation of drain current and subthreshold characteristics induced by the aforementioned device parameters. It will be a great benefit for the junctionless device with a gate-all-around structure as the scaling continues to approach the end of MOSFETs. [ABSTRACT FROM AUTHOR]

TFETs are promising candidates for future low-power logic applications because of their potential for outperforming conventional MOSFETs under reduced supply voltage (${V} _{\textsf {DD}}$). Among all material systems currently being explored, group IV semiconductor SiGe holds the most potential due to its very large scale integration (VLSI) compatibility, mature synthesis techniques, and tunable bandgap, making it more likely to be adopted for future VLSI technologies. It has been shown experimentally that the on-state current (${I} _{\textsf {on}}$) of SiGe TFETs improves significantly with the increasing Ge content. However, increasing the Ge content leads to excessive leakage in the off-state and poses a challenge to the pseudomorphic growth of SiGe. In this paper, the concept of Ge-pocket TFET with a counter-doped pocket is proposed. By confining Ge to the pocket region, the proposed structure circumvents those problems. Both the steep subthreshold swing and high ${I} _{\textsf {on}}$ can be achieved. The proposed TFET also demonstrates excellent scalability in terms of physical gate length (${L} _{\textsf {gate}}$) and ${V} _{\textsf {DD}}$ , which makes it a promising replacement of conventional MOSFETs for low-power logic applications. [ABSTRACT FROM AUTHOR]

In this paper, Si tunnel FETs (TFETs) with the vertical tunneling junction (nVTFETs) were demonstrated by utilizing fabrication processes compatible to those used for conventional Si MOSFETs. The vertical tunneling junction was realized by forming n-type surface pocket regions under gate overlap regions of p-type source extensions only using the ion implantation (I/I). The impacts of carbon (C) coimplantation and formation of offset spacer (OSS) on the TFET performance were examined. As a result, the performance of the fabricated nVTFETs was enhanced by applying the C coimplantation and the OSS formation before the I/I for the vertical tunneling junctions. It has been found, on the other hand, that nVTETs exhibit a reverse short-channel effect, where the threshold voltage increases with decreasing the channel length, and that this effect is correlated with the enhanced temperature dependence of subthreshold slope. These phenomena are attributable to the existence of a thermionic barrier between the source junction and the channel, formed by boron diffusion from the source region. [ABSTRACT FROM AUTHOR]

In this paper, threshold voltage (${V}_{{\textsf {th}}}$) shift in Al2O3/ AlGaN/GaN metal–oxide–semiconductor high-electron-mobility transistors (MOS-HEMTs) induced by charge trapping and the impacts of postmetallization annealing (PMA) were studied. In addition to the transient voltage shift caused by interface trapping effect, retentive voltage shift was also observed which was attributed to border traps with very large emission time constant ($\tau _{e}$). PMA has little influence on the transient ${V}_{\textsf {th}}$ shift which is related to interface traps with $\textsf {18}~\textsf {s}< \tau _{e}< \textsf {54}$ s, while the total interface traps with $\textsf {4}~\textsf {s} < \tau _{e}< \textsf {54}$ s are reduced by PMA from $\textsf {4.03} \times \textsf {10}^{\textsf {12}}\,\,\textsf {cm}^{-\textsf {2}}$ to $\textsf {1.77} \times \textsf {10}^{\textsf {12}}\,\,\textsf {cm}^{-\textsf {2}}$. Interface trapping dominates at low program voltage (${V}_{p}$), while border trapping becomes remarkable with ${V}_{p}$ above the critical level. Due to the cumulative border trapping effect, an increase in program voltage by per volt causes an additional retentive voltage shift by about $\textsf {1}$ V. PMA leads to an increase in critical ${V}_{p}$ from 5 to 7 V, which therefore results in a decrease in the density of total accessible border traps from $\textsf {1.99} \times \textsf {10}^{\textsf {13}}\,\,\textsf {cm}^{-\textsf {2}}$ to $9.25\times \textsf {10}^{\textsf {12}}$ cm−2 with ${V}_{p}$ up to 12 V. The border trapping for both devices with and without PMA shows similar retention characteristics, with ${V}_{{\textsf {th}}}$ recovery as small as 1.2 V after one week. [ABSTRACT FROM AUTHOR]

The degradations of electrical parameters for silicon carbide power MOSFETs under repetitive short-circuit (SC) stress are investigated in detail in this paper. It demonstrates that the generation of negative charges along the gate–oxide interface of the channel region is the dominant degradation mechanism, which results in the increase in the threshold voltage (${V}_{\text {th}}$) and the rise of ON-state resistance (${R}_{\text {dson}}$) under low gate voltage bias condition. Furthermore, degradations of dynamic characteristics including gate charge (${Q}_{\text {g}}$) and switching behaviors of the device after the repetitive SC stress are extracted and analyzed for the first time. It illustrates that the increased ${V}_{\text {th}}$ contributes to the rise of the Miller plateau voltage (${V}_{\text {gp}}$), which further leads to the increase in gate–source charge (${Q}_{\text {gs}}$). Meanwhile, the increase in the turn-ON time and the reduction of turn-OFF time are observed, which are also resulted from the positive shifts of ${V}_{\text {th}}$ and ${V}_{\text {gp}}$ , leading to the rise of turn-ON switching energy (${E}_{{ \text {on}}}$) and the decline of turn-OFF switching energy (${E}_{\text {off}}$), respectively. [ABSTRACT FROM AUTHOR]

In this paper, analytical modeling of a charge plasma-based nanogap embedded surrounding gate MOSFET biosensor for label-free biosensing has been presented and verified with extensive simulated device data. Along the channel, considering parabolic potential profile, surface potential, threshold voltage, and drain currents have been modeled. Sensitivity has been analyzed by measuring the shift in ${I} _{ \mathrm{\scriptscriptstyle ON}}/{I} _{\mathrm{\scriptscriptstyle OFF}}$ and threshold voltage when the biosensor interacts with the neutral or charged biomolecules. Less thermal budgeting scheme with simplified fabrication process flow, i.e., no ion implantation or diffusion can be achieved easily here due to new charge plasma concept. In addition, the issues related to the doping control and random dopant fluctuations have been reduced significantly to make the device immune to the process variation. Hence, the proposed device has been optimized for the enhancement in device electrostatics and sensitivity. Extensive TCAD simulations have been performed to investigate the device parameters and to verify the model data. Hence, the proposed model can be considered as an optimal model of a biosensor for the future reference. [ABSTRACT FROM AUTHOR]

3-D sequential integration requires top MOSFETs processed at a low thermal budget, which can impair the device reliability. In this paper, top junctionless (JL) devices are fabricated with a maximum processing temperature of 525 °C. The devices feature high k/metal replacement gate and low-temperature Si:P and SiGe:B 60% raised source and drain for nMOS and pMOS fabrication, respectively. Device matching, analog, and RF performance of the top tier devices are in-line with the state-of-the-art Si technology processed at high temperature (>1000 °C). JL devices operate at reduced electric field and can meet in specification reliability (10-year reliable operation at ${V}_{\textsf {G}}= {V}_{\textsf {th}}+ 0.6$ V, 125 °C), even without the use of “reliability” anneal. The top Si layer is transferred on CMOS planar bulk wafers with W metal-1 interconnects, using a SiCN to SiCN direct wafer bonding. Comparison with silicon-on-insulator devices fabricated with the same low-temperature flow shows no impact on device electrical performance from the Si layer transfer. [ABSTRACT FROM AUTHOR]

This paper reports on 45-nm fin pitch strained p-type Ge gate-all-around devices fabricated on 300-mm SiGe strain-relaxed-buffers (SRB). By improving the process integration flow, excellent electrical performance is demonstrated: the $Q$ factor is increased to 25 as compared to our previous work, $I_{ \mathrm{\scriptscriptstyle ON}} = \textsf {500}~\mu \text{A}/ \mu \text{m}$ at $I_{ \mathrm{\scriptscriptstyle OFF}} = \textsf {100}$ nA/ $\mu \text{m}$ is achieved, approaching the best published results on Ge finFETs. Good negative-bias temperature instability reliability is also maintained, thanks to the use of Si-cap passivation. The process flow developed for the fabrication of the single Ge nanowire (NW) is adapted and vertically stacked strained Ge NWs featuring 8-nm channel diameter are successfully demonstrated. A systematic analysis of the strain evolution is conducted on both single and double Ge NWs after the most challenging steps of the process integration flow: 1.7-GPa uniaxial-stress is demonstrated along the Ge wire, which originates from the lattice mismatch between the Ge source/drain and the Si0.3Ge0.7 SRB. [ABSTRACT FROM AUTHOR]

Among the diverse and ever-expanding list of candidate technologies to serve the Internet of Everything, the rise of thin-film transistors on plastic as active components for ubiquitous ICs has been nothing short of meteoric. The stage for this explosion of interest was set by a pivotal advantage of the low manufacturing cost and ultrathin form factor, as demonstrated in recent prototypes of thin-film radio frequency identification (RFID) tags. Most RFID tags use inductive antennas, whereas, in this paper, capacitively coupled antenna is presented. Advantages of capacitive-coupled tags are the monolithic integrated antenna, the compact size, the additional security due to very short range of operation, and the localization and orientation abilities. The main circuit block of the tag, a 12-bit code generator, is demonstrated achieving only 160 nW of power dissipation at 0.3 V power supply transmitting data at 810 b/s on a 18 $\mu \text{m}$ -thick plastic substrate. The footprint of the monolithic integrated antenna is 1 cm2 and essentially defines the size of the full tag. [ABSTRACT FROM AUTHOR]

Gate-commutated thyristors (GCTs) are subject to uneven impedances along the current path from GCT circles to the gate contact, which leads to current redistribution between the GCT circles during turn-off. The current redistribution inequality significantly limits the maximum controllable current of GCTs. This paper presents an optimization method for GCT cell arrangement design to minimize the current redistribution inequality. First, the whole GCT wafer model is applied to calculate the inequality of the current redistribution. The whole GCT wafer model is a hybrid model built by physics-based GCT cell models connected with lumped parameter models. The GCT cell models applied here are improved compact models with multiple physical mechanisms, while the lumped parameter models represent the uneven impedances of the GCT circles along the GCT wafer. In order to measure those impedances, a set of physical concentric contact rings are developed. Finally, the Tabu search (TS), a heuristic algorithm, is applied to optimize the GCT cell arrangement. Using the optimization method based on TS, an optimized set of GCT cell numbers for a 4-in GCT wafer is obtained, reducing the inequality of the current redistribution by 20%. [ABSTRACT FROM AUTHOR]

The stress distributions and induced mobility gain in germanium (Ge)-based p-type MOSFETs (pMOSFETs) with an extended channel width are estimated in this paper. Several tin (Sn) concentrations of group-IV semiconductor GeSn alloys integrated with a compressive contact etching stop layer (CESL) are logically analyzed to evaluate the stress impact that results from the high lattice mismatch of embedded GeSn alloys on narrow device channels. Analytic results show that the stress intensity and corresponding mobility gain are enhanced by increasing the Sn concentration in the embedded source/drain GeSn stressors. By contrast, the performance variation of the short-channel Ge-based pMOSFET is strongly dominated by the extended width when the CESL covers the entire device. A mobility gain of up to ~124.07% is achieved for the 22-nm pMOSFET when a 100-nm extended width is considered. Moreover, the entire stress responses of high- ${k}$ /metal gate-last procedure combined with the following CESL deposition are investigated. Analytic results reveal that the stress relaxation along the channel height direction occurs after the poly gate etch process. Consequently, the adoption of a stressed CESL is demonstrated to be an effective approach to remedy the device mobility gain by stress improvement on the channel height direction. [ABSTRACT FROM AUTHOR]

Double-metal–insulator–semiconductor tunnel diodes with concentric structure are able to exhibit transistor and light sensor behavior. Generally, the outer ring is used to serve as a control gate and supply additional charges to the inner sensor through coupling. However, there is not yet any discussion about the contrary situation in exchanging the conventional role of the inner device and the outer ring. In this paper, we compare two operating situations with no other variants involved. Comparing the results of them, we find that when the inner device plays as a control gate and the outer ring being a sensor (i.e., inner gate outer sensor), the asymmetric coupling effect can make the outer sensor achieve much higher light-to-dark current ratio, however, only need nearly half of the sensor bias under the same control gate bias. In addition, further calculation of total power consumption shows that there is no larger power needed behind this more sensitive performance compared with the conventional operation. [ABSTRACT FROM AUTHOR]

This paper investigates the effects of parasitic source/drain (S/D) field plates (FPs) on electrical characteristics of channel-passivated amorphous indium gallium zinc oxide thin-film transistors (a-IGZO TFTs). For the S/D metal of the channel-passivated TFT, besides acting as conducting electrodes, they can be FPs to influence the carrier conduction in the semiconductor layer via the channel passivation (CHP) layer. We first fabricated a standard channel-passivated a-IGZO TFT. Based on this TFT, performance variations caused by different lengths of the S/D FPs under different thicknesses of the CHP and a-IGZO layers are explored by technology computer-aided design simulation. Carrier concentration distributions and current flow patterns are examined to study the physical mechanisms of the corresponding performance degradation or improvement. [ABSTRACT FROM AUTHOR]

This paper reports the response of an N-channel transparent gate recessed channel (TGRC) metal–oxide–semiconductor field-effect transistor (MOSFET) to X-ray radiation in the 0.5-k–10-krad dose range after irradiation. TCAD simulations for the same have been done to estimate the threshold voltage shift in MOSFET with different radiation dosages. Models accounting for electron–hole pair generation and recombination are applied along with the trap/detrap model for an insulator as well as interface charging. An improvement of 1.11 mV/krad in radiation sensitivity has been found in increasing the oxide thickness from 2 to 6 nm. The results suggest that TGRC-MOSFET can be effectively used as an X-ray dosimeter in the sub-30-nm scale. Along with a signal amplification and processing circuit, this device can find an enormous applicability in clinical and space environments. [ABSTRACT FROM AUTHOR]

The inclusion of quantum effects in the transport direction plays an important role in the extensive research of ultrascaled electronic devices. In this context, it is necessary to study how these phenomena affect different technological architectures in order to conclude which one can be the best candidate to replace standard technology. This paper presents the implementation of direct source-to-drain tunneling effect in a multisubband ensemble Monte Carlo simulator showing its influence in different structures such as fully depleted silicon-on-insulator, double-gate silicon-on-insulator, and FinFET devices. The differences in the potential profile and the electron distribution in the subbands for these architectures modify the number of electrons affected by this quantum mechanism and, therefore, their short-channel behavior. [ABSTRACT FROM AUTHOR]