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This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of ultra wide band gap semiconductors and devices for power control and conversion, including both experimental results and theoretical developments. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices. Topics of interest include, but are not limited to: IDtra Wide Band Gap Materials: Advances in material synthesis, defect characterization, transport and high-field properties, and material-level integration; evaluation of fundamental materials-limited figures of merit; Power Devices: Vertical and lateral MOSFETs, HEMTs and MIS-HEMTs, IGBTs, Schottky and pn junction rectifiers, and other device concepts; fabrication and device characterization; designs and device structures for controlling field profiles, edge termination; Thermal Management: Approaches to mitigate thermal effects in power devices using ultra wide band gap materials; Integration: Monolithic and heterogenous integration for system-level applications using ultra wide band gap materials. Integration with Si or other semiconductors for system-on-chip and system-in-package implementations, including heterogenous and package-level integration for high-performance power conversion applications. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

It is well known that there is a critical Sn content for a GeSn alloy, at which the conduction band edges at ${L}$ and $\Gamma$ symmetry points are aligned in energy. For GeSn tunnel FET (TFET) simulations, with a given donor concentration, this paper reveals that simulations neglecting the multivalley and nonparabolic band structure would incorrectly predict the subthreshold slope (SS) and the off-currents. We highlight the indispensability of the consideration of the multivalley band structure of GeSn for TFET simulations. This paper provides the required parameters, which may be useful for numerical simulations of other optoelectronic and electronic GeSn devices. [ABSTRACT FROM AUTHOR]

This paper describes the separation between the area and the perimeter current density components of 4H-SiC vertical p+-i-n diode with a circular Al+ implanted emitter of different diameters in the range 150-1000 µmand for temperatures of measurement in the range 30-290 °C. It is shown that before the diode series resistances become dominant, the forward current is given by the sum of an area plus a perimeter component, both of exponential trend with ideality factor 2; while toward high voltages, an area componentwith exponential trend and ideality factor 1 adds to the previous components. Moreover, this paper shows that forward area and perimeter current density components can be used for a straightforward identification of the parameters controlling the current transport, provided that they can be fit by the p-n junction equations in the frame of the abrupt junction approximation. Finally, this paper shows that the area reverse current density can be used for the identification of the electrically active defects in the drift layer. [ABSTRACT FROM AUTHOR]

In contrast to the conventional planar p-i-n photodiode and a metal-semiconductor-metal photodetector, the 3-D dual-gate photosensitive thin-film transistor (TFT) architectures presented here attain excellent photoresponse characteristics. Operating the device in the subthreshold regime further boosts the photoconductive gain as a result of light-induced decrease in the threshold voltage. This paper presents design considerations along with a performance comparison between 3-D photosensitive TFTs that have π- and FIN-shaped channels and conventional TFT with a planar channel. Our paper shows that the π-shaped structure tends to have a higher sensitivity while the FIN-shaped counterpart is more responsive with wider dynamic range. For both structures, a measured photoconductive gain of 104~106% is obtained with spectral responsivity ranging from near UV to near IR, and the photoresponse time in the range of tens of milliseconds. The 3-D dual-gate photosensitive TFT architecture appears to be very promising for large-area, low-level UV, visible, and IR detection applications. [ABSTRACT FROM AUTHOR]

FETs made on 2-D semiconductors, typically without degenerate doping at the contacts, have a significant Schottky junction (SJ) resistance, which complicates transistor analysis. This paper evaluates the effect of the contact resistance on the 2-D-material FET characteristics through four-terminal (4-T) resistance measurements on WSe2 FETs, which allow studying the channel and contacts characteristics separately. Apart from showing the nonnegligibility of contact resistance, this paper enables a finer understanding of commonly observed phenomena, such as transistor performance improvement with dielectric-encapsulation is observed to have a stronger effect on the contact than the channel; the resistance of the forward-biased SJ is observed to be not negligible, but comparable to that of the reverse-biased junction; at biases commonly referred to as “low-bias,” the WSe2 FET resistance could be dominated by the contacts; and pinchoff can be observed at relatively lower current levels, being related to the channel-contact resistance ratio rather than their magnitudes. In the devices where true channel pinchoff can be verified, a correlation emerges between current saturating behavior and asymmetry in the output characteristics with respect to the drain–source bias polarity, a feature that may serve as a guide toward interpreting standard FET output characteristics in 2-D materials. [ABSTRACT FROM PUBLISHER]

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability. [ABSTRACT FROM PUBLISHER]

Thin-film transistors (TFTs) fabricated using solution-processed zinc–tin-oxide (ZTO) semiconductor thin films as the channel layers are proposed in this paper. Effect of the ZTO annealing temperature on the TFT performance is studied. Significant reduction of oxygen-vacancy and chlorine residue contents in the ZTO semiconductor can be obtained when the annealing temperatures are 500 °C–700 °C. The ZTO semiconductor with the annealing process at 600 °C in air can give an optimal ZTO TFT having a low leakage current of 10−12 A and a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 3 $\times \,\,10^{7}$. The subthreshold swing is 0.39 V/decade corresponding to an interface trap density of $1.2\times \,\,10^{12}\,\,$ cm−2eV−1. [ABSTRACT FROM AUTHOR]

High-performance ambipolar chemical sensors toward electron-detonating NH3 and electron-accepting NO2 are obtained based on the solution-based films of two ambipolar (${p}$ -fluoro)phenoxy substituted tris(phthalocyaninato) rare earth semiconductors with different metal ions, named Gd2 [Pc(OPhF)8]3(1) and Tb2 [Pc(OPhF)8]3(2). Measurements over the films fabricated from 1 and 2 by a simple quasi-Langmuir–Shäfer (QLS) method reveal their ambipolar semiconductor nature, with a ${p}$ -type response in NH3 sensing and n-type response in NO2 sensing, associated with not only suitable highest occupied molecular orbital and lowest unoccupied molecular orbital energy levels but also the different electronic induction effects of the analytes. Interestingly, the devices from the QLS film of 2 with a weaker intermolecular $\pi $ – $\pi $ stacking in J-type (edge-to-edge) packing mode display much better sensing properties to both NH3 and NO2, compared to those from QLS film of 1 with a stronger intermolecular $\pi $ – $\pi $ stacking in the H-type (face-to-face) packing mode. This is mainly because of the larger specific surface area from the J-aggregate with the more uniform-sized nanoparticles for the QLS film of 2. In particular, the highly sensitive, stable, and reproducible responses to 1–20-ppm NH3 with a limit of detection of 0.15 ppm only in 1 min are obtained from the QLS film of 2 for the first time. This paper unravels, first, the effect of central metal ions of sandwich triple-deckers on molecular stacking mode, film structure, and gas sensing performances, which would be helpful for designing and preparing high-performance ambipolar gas sensor devices by combining the molecular design and the device fabrication technique. [ABSTRACT FROM AUTHOR]

In this paper, the electron transport properties of a C3N nanoribbon-based field-effect transistor (FET) in the ballistic regime have been simulated. Using the density-functional theory (DFT) to obtain the band structures, we found that the armchair-edged C3N nanoribbons are semiconductors, and their bandgaps are determined by their widths, while the zigzag-edged ribbons present the metallic properties. We have carried out calculations to study the transport properties of armchair-edged C3N nanoribbon by using DFT combined with the nonequilibrium Green’s function. Our simulation results revealed that both bandgap and current on/off ratio are reduced as the width increasing. Moreover, the gate length, channel length, and ribbon’s width are found to have prominent influences on the transfer characteristics. The armchair-edged C3N nanoribbon-based FETs have the highest current on/off ratio of 106 and the ideal subthreshold swing of 61.2 mV/dec, which make it promising for potential applications of FET. [ABSTRACT FROM AUTHOR]

In this paper, a tunable acid-resistant Zr-doped indium oxide (ZrInO) semiconductor material was developed. Detailed studies showed that the acid resistance of ZrInO thin films is tunable and increases with the increase in annealing temperature. Taking advantage of this special property, we successfully fabricated back-channel-etched (BCE) thin-film transistors (TFTs) based on the tunable acid-resistant ZrInO thin film. ZrInO-TFTs with BCE structure exhibited excellent electrical performance with a saturation mobility of 21.4 cm $^{\textsf {2}}\textsf {V}^{-\textsf {1}}\textsf {s}^{-\textsf {1}}$ , a subthreshold swing of 0.28 V/decade, and an ON/OFF current ratio of $1.0\times107$. These results envision that the developed ZrInO semiconductor with tunable acid resistance has a good prospect for the channel layer of BCE-TFTs. [ABSTRACT FROM AUTHOR]

Considering the demand of III–V multigate (MUG) transistors for next-generation CMOS technologies, a compact model is required to test their performance in different circuits. The low effective mass and highly confined geometry of these MUG devices demand the use of computationally expensive coupled Poisson–Schrödinger (PS) solver for terminal charges and surface potential. In this paper, we propose an approximation, which decouples the PS equations and enables the development of a computationally efficient analytical model. The surface potential and semiconductor charge equations for III–V low effective mass channel cylindrical nanowire (NW) transistors are derived using the proposed approximation. The proposed model is physics-based and does not include any empirical parameters. The accuracy of the model is verified across NWs of different sizes and materials using the data from the 2-D PS solver and found to be accurate. [ABSTRACT FROM AUTHOR]

The stress distributions and induced mobility gain in germanium (Ge)-based p-type MOSFETs (pMOSFETs) with an extended channel width are estimated in this paper. Several tin (Sn) concentrations of group-IV semiconductor GeSn alloys integrated with a compressive contact etching stop layer (CESL) are logically analyzed to evaluate the stress impact that results from the high lattice mismatch of embedded GeSn alloys on narrow device channels. Analytic results show that the stress intensity and corresponding mobility gain are enhanced by increasing the Sn concentration in the embedded source/drain GeSn stressors. By contrast, the performance variation of the short-channel Ge-based pMOSFET is strongly dominated by the extended width when the CESL covers the entire device. A mobility gain of up to ~124.07% is achieved for the 22-nm pMOSFET when a 100-nm extended width is considered. Moreover, the entire stress responses of high- ${k}$ /metal gate-last procedure combined with the following CESL deposition are investigated. Analytic results reveal that the stress relaxation along the channel height direction occurs after the poly gate etch process. Consequently, the adoption of a stressed CESL is demonstrated to be an effective approach to remedy the device mobility gain by stress improvement on the channel height direction. [ABSTRACT FROM AUTHOR]

The 1-D nanoribbon (NR) of monolayer materials has gained immense interest due to their unique properties qualitatively distinct from their bulk properties and the demand for nanoscale applications. In this paper, the quantum transport properties of two most prominent 2-D materials, i.e., silicene NR (SiNR) and a graphene NR (GNR) tunnel field-effect transistor (TFET) with the effect of different dopant molar fractions in the drain region are studied numerically using nonequilibrium Green’s function formalism. In SiNR TFET, higher on-state current (${I}_{ \mathrm{\scriptscriptstyle ON}}$) is observed due to wider tunneling energy window and high transmission probability of carriers. In order to observe the effect of variation of doping density in the drain region, we have studied analog figures of merit such as the transconductance (${g}_{m}$), output resistance (${r}_{o}$), transconductance generation factor (${g}_{m}/{I}_{D}$), and the intrinsic gain (${g}_{m}{r}_{o}$) for different molar fractions. Similarly, we have evaluated the RF performance of the SiNR and GNR TFETs as a function of cutoff frequency (${f}_{T}$), gate capacitance (${C}_{G}$), and transport delay ($\tau$). [ABSTRACT FROM AUTHOR]

The incomplete ionization of impurity atoms affects the free carrier concentration of several wide-bandgap (WBG) semiconductor materials even at room temperature, thus modifying the electrical properties of power devices. In this paper, the influence of the partial ionization of the dopants on the static and dynamic behaviors of WBG semiconductor-based superjunction (SJ) devices has been numerically investigated through extensive 2-D finite-element simulations. While this physical effect has only a minor impact on the static device characteristics, if a reverse bias pulse with a rise time comparable or smaller than the ionization time constant is applied to the structure, a “dynamic ionization” phenomenon can take place. The onset of this time-dependent ionization is the cause of charge unbalance effects in the device structure, due to the temporal dependence of the activated number of dopants. Electrothermal simulations, which have been carried out for a 4H-silicon carbide SJ diode, show a nonuniform temperature distribution during the transients which leads, in turn, to the self-heating of the device. Through an accurate redesign of the cross-sectional view of the device, the drawbacks of the incomplete ionization have been mitigated and the device performance enhanced. [ABSTRACT FROM AUTHOR]

The figure of merit (FOM) of a semiconductor device represents an important quality as it pertains to its performance limits and is often used to drive the technology development in a specific direction. Comparing the performances of switching power MOSFETs using their FOMs has become ubiquitous practice in power semiconductor and power electronics industries. In this paper, a critical review of the proposed power MOSFET FOMs is presented, and key limitations are discussed. It is shown that the quality factor ${Q}_{F2}={(}{\lambda {E}_{c}}/{R_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}}{)}$ along with ${Q}_{G}$ and ${T}_{j\textsf {max}}$ may be used to guide the development of future generations of power semiconductor device technologies for power electronics switching applications, where $\lambda $ and ${E}_{c}$ are the thermal conductivity and critical electric field strength for the avalanche breakdown of the semiconductor material, respectively, ${R}_{ \mathrm{\scriptscriptstyle ON},\textsf {sp}}$ is the specific on-state electrical resistance, ${Q}_{G}$ is the gate charge, and ${T}_{j\textsf {max}}$ is the maximum junction temperature of the semiconductor power device, respectively. [ABSTRACT FROM AUTHOR]

Among the different types of bilayer tunneling field-effect transistors exploiting interband tunneling phenomena with tunneling directions aligned with gate-induced electric fields, the utilization of InAs/GaSb channels proves to be an appealing means to enhance ON-current levels. Ultrathin channel thicknesses make quantum confinement be the agent that closes the broken gap of the InAs/GaSb heterojunction leading to a staggered gap which blocks the tunneling current in the OFF state. In this paper, the gate leakage tunneling current is analyzed as one of the main critical processes degrading the performance of the proposed structure. Appropriate gate stacks of HfO2/Al2O3 combined with gate-to-drain underlaps are shown to effectively suppress this leakage tunneling, while at the same time, preserve an adequate electrostatic control over the channel. Simulation results for the most optimized configurations feature ON-state levels of up to $400\mu \text{A}/\mu \text{m}$ and subthreshold swings of $\approx 3$ mV/dec over more than 7 decades of current. [ABSTRACT FROM AUTHOR]

A new Pd nanoparticle (NP)/Pd film/GaOx/GaN-based metal–oxide–semiconductor diode hydrogen sensor is fabricated and studied. In this paper, appropriate photochemical drop coating and an H2O2 surface treatment were used to form Pd NPs and a GaOx dielectric layer. The Pd NPs increased the surface area/volume ratio, and the presence of GaOx layer led to the effective dissociation of hydrogen molecules. The improved hydrogen sensing properties include a very high sensing response of $1.24 \times 10^{{7}}$ (in 1% H2/air gas at 300 K) and an extremely low detection level (${\le} 1$ ppm H2/air). Furthermore, based on a kinetic adsorption analysis, the activation energy was only 13.1 $\text {KJ}\cdot \text {mol}^{-{1}}$ that is beneficial for hydrogen sensing. The proposed device is therefore promising for high-performance hydrogen sensing applications. [ABSTRACT FROM AUTHOR]

This paper presents a comparison of switching performances between the in-situ oxide, gallium nitride (GaN) interlayer FET (OG-FET) and the conventional GaN metal–oxide–semiconductor FET (MOSFET), and explores the influence of the channel electron mobility on the device switching performance. GaN OG-FET is a novel structure with a pristine GaN layer grown between the gate oxide and the p-GaN enhancing the channel mobility up to 185 cm2/ $\text {V}\cdot \text {s}$ , which is over $3{\times}$ larger than that of the typical reported value (50 cm2/ $\text {V}\cdot \text {s}$) in GaN MOSFET. Owing to the high channel electron mobility, the GaN OG-FET showed a switching loss 30% lower than that of the conventional GaN trench MOSFET. Our results indicate that GaN OG-FET has the potential to attain greater efficiency, particularly at higher frequencies, showing a possible patch toward megahertz range conversions. [ABSTRACT FROM AUTHOR]

The 2-D material-based TFETs are among the most promising candidates for low-power electronics applications since they offer ultimate gate control and high-current drives that are achievable through small tunneling distances ($\Lambda $) during the device operation. The ideal device is characterized by a minimized $\Lambda $. However, devices with the thinnest possible body do not necessarily provide the best performance. For example, reducing the channel thickness (${T}_{\text {ch}}$) increases the depletion width in the source, which can be a significant part of the total $\Lambda $. Hence, it is important to determine the optimum ${T}_{\text {ch}}$ for each channel material individually. In this paper, we study the optimum ${T}_{\text {ch}}$ for three channel materials: WSe2, black phosphorus, and InAs using full-band self-consistent quantum transport simulations. To identify the ideal ${T}_{\text {ch}}$ for each material at a specific doping density, a new analytic model is proposed and benchmarked against the numerical simulations. [ABSTRACT FROM AUTHOR]

In this paper, we present a charge-based compact model for transition metal dichalcogenide (TMD)-based thin-channel field-effect transistor. In model development, first, charge densities at the source and drain terminals are calculated in terms of the applied gate and drain voltages. Calculated charge densities are then used to develop a charge-based drain-current model. Effects of interface traps, ambipolar current behavior, and negative capacitance are then included in the developed drain-current model in terms of charge densities. Predictions of the proposed model are verified by the simulation and experimental data of the TMD channel material-based n-type and p-type MOSFETs. [ABSTRACT FROM AUTHOR]

Full-band atomistic quantum transport simulations based on first principles are employed to assess the potential of band-to-band tunneling FETs (TFETs) with a 2-D channel material as future electronic circuit components. We demonstrate that single-layer (SL) transition metal dichalcogenides are not well suited for TFET applications. There might, however, exist a great variety of 2-D semiconductors that have not even been exfoliated yet; this paper pinpoints some of the most promising candidates among them to realize highly efficient TFETs. SL SnTe, As, TiNBr, and Bi are all found to ideally deliver ON-currents larger than 100 $\mu \text{A}/\mu \text{m}$ at 0.5-V supply voltage and 0.1 nA/ $\mu \text{m}$ OFF-current value. We show that going from single to multiple layers can boost the TFET performance as long as the gain from a narrowing bandgap exceeds the loss from the deteriorating gate control. Finally, a 2-D van der Waals heterojunction TFET is revealed to perform almost as well as the best SL homojunction, paving the way for research in optimal 2-D material combinations. [ABSTRACT FROM AUTHOR]

The combination of two highly versatile materials as reduced graphene oxide (rGO) and molybdenum disulfide (MoS2) forms the layered rGO–MoS2 hybrids that have great potential for sensing applications. In this paper, we developed a cost-effective, time-saving, and efficient microwave-assisted method to exfoliate rGO and MoS2 nanosheets in a powder mixture for the formation of rGO–MoS2 hybrids. The formation of hybrids with a combination of organic and inorganic 2-D layered materials offers new possibilities for the development of gas sensitive materials. The applied microwave treatment is a simple and fast process for the large-scale synthesis of rGO–MoS2 hybrids. The synthesized rGO–MoS2 hybrids were characterized by X-ray diffraction, scanning electron microscope, energy dispersive X-ray spectroscopy, Raman, X-ray photoelectron spectroscopy, and thermogravimetric analyses to determine the phase structure, surface morphology, defect formation, binding energy, thermal stability and so on. The synthesized rGO–MoS2 hybrids were tested for sensing application and showed the good performance to detect gases such as O2, N2, and NH3 at room temperature. [ABSTRACT FROM AUTHOR]

Sub-bandgap (SBG) impact ionization (II) enables steep subthreshold slope that enable devices to overcome the thermal limit of 60 mV/decade. This phenomenon at low voltage enables various applications in logic, memory, and neuromorphic engineering. Recently, we have demonstrated sub-0.2-V II in n-i-p-i-n diode experimentally primarily based on steady-state analysis. In this paper, we present the detailed experimental transient behavior of SBG-II in n-i-p-i-n. The SBG-II generated holes are stored in the p-well. First, we extract the leakage mechanism from the p-well to show two mechanisms: 1) recombination–generation and 2) over the barrier (OTB), where OTB dominates when barrier height ${\phi }_{b}<\textsf {0.59}~\textsf {eV}$. Second, we analytically extract the SBG-II current (${I}_{\textsf {II}}$) at 300 K from the experimental results. The drain current (${I}_{D}$), electric field (${E}{-}\textsf {field}$), and ${I}_{\textsf {II}}$ are plotted in time. We observe that ${I}_{\textsf {II}}$ increase as ${E}{-}\textsf {field}$ reduces which indicates that ${E}$ -field does not primarily contribute to ${I}_{\textsf {II}}$. Furthermore, ${I}_{D}$ shows two distinct behaviors: 1) ${I}_{\textit {II}} ({I}_{D}$) is constant at the beginning and 2) eventually “universal” ${I}_{\textsf {II}} ({I}_{D}$) is linear, i.e., ${I}_{\textsf {II}}={k}\times {I}_{D}$ where ${k} = \textsf {1}\textsf {0}^{-\textsf {3}}$ ; we also show that the electrons primarily contributing to ${I}_{D}$ are directly incapable of II due to insufficient energy ($< {E}_{g}$). Fischetti’s model showed that SBG-II is primarily caused by “hot” electrons that accept energy in an Auger-like process from “cold” drain electrons to enable SBG-II. We speculate that if ${I}_{D}$ electrons “heat-up” the cold drain electrons, which would further energize the hot electrons to produce the observed ${I}_{\textsf {II}}{(}{I}_{D}$) universal dependence. [ABSTRACT FROM AUTHOR]

The threshold voltage of an organic thin-film transistor (OTFT) is sensitive to several variables, which makes it attractive for sensing applications. However, its measurement is not straightforward, especially, when mobility is gate voltage-dependent, and source and drain resistances are significant. The on-state voltage of a TFT does not suffer from these drawbacks, and thus, offers an alternative variable for use as a sensing variable. However, conventional measurement of on-state voltage marking the onset of conduction in the device requires measurement of very low current values, and extrapolation as a result of which it is not commonly employed. This paper demonstrates a simpler alternative method for measurement of on-state voltage that requires measurement of floating drain voltage as source voltage is linearly ramped while maintaining gate voltage constant. The drain voltage tracks the source voltage until the channel is completely removed. 2-D numerical simulation results are presented to validate that the proposed technique for the extraction of on-state voltage yields reliable estimates under different device conditions. Experimental results obtained with pentacene/poly (4-vinyl phenol)-based top contact bottom-gate OTFTs are also presented to illustrate the proposed concept. [ABSTRACT FROM AUTHOR]

In this paper, we carried out a systematic comparison between the enhancement-mode GaN-based fully recessed metal-insulator-semiconductor field-effect transistors (MIS-FETs) and partially recessed MIS-high-electron-mobility transistors (MIS-HEMTs) with the same gate dielectric stack (LPCVD-SiNx/PECVD-SiNx) that has delivered promising long-term reliability and stability. Despite a moderately larger on-resistance (${R}_{ \mathrm{ON}}$), the MIS-FETs deliver superior ${V}_{\text {TH}}$ uniformity and thermal stability. Under long-term gate bias stress, both the MIS-HEMT and MIS-FET deliver similar small positive-bias temperature instability, while the negative-bias temperature instability of the MIS-HEMT is much larger than that of MIS-FET. The MIS-FET also delivers a higher ${V}_{\text {TH}}$ stability than the MIS-HEMT under dynamic gate bias stress. It is suggested that the differences in ${V}_{\text {TH}}$ stability mainly originate from the different spatial separation between the trap states and the conducting channel, with it being larger in MIS-HEMT than in MIS-FET. [ABSTRACT FROM AUTHOR]

This paper shows the effect of performing consecutive measurement prior to negative bias stress instability (NBSI) on diamond metal–oxide–semiconductor capacitor (MOSCAP). For the first time, time-dependent stress tests have been carried out in order to investigate the stability of the flatband voltage (${V}_{\text {FB}}$) of MOSCAPs through capacitance–voltage (CV) measurements. Two tests have been performed. In the first test, consecutive CV measurements with the device biased from deep depletion to the accumulation regime were performed to monitor the recovery of the ${V}_{\text {FB}}$. In the second test, NBSI technique has been applied. ${V}_{\text {FB}}$ stability has been measured by means of a time-dependent bias stress in which the device was polarized at a fixed negative voltage for a specific time interval prior to performing the next CV measurement. As ${V}_{\text {FB}}$ is directly connected to the effective oxide charge (${N}_{\text {eff}}$), the two different tests allowed the extraction of total amount of ${N}_{\text {eff}}$ that interfered during the measurements. The result observed shows that the postoxidation annealing process induces a strong enhancement of the MOSCAP stability together with a decrease of ${N}_{\text {eff}}$ [ABSTRACT FROM AUTHOR]

This paper reports a comprehensive study on the anisotropic electrical properties of vertical ($\overline {\textsf {2}}01$) and (010) $\beta $ -Ga2O3 Schottky barrier diodes (SBDs). The devices were fabricated on single-crystal substrates grown by an edge-defined film-fed growth method. The temperature-dependent current–voltage (I–V) and capacitance–voltage (C–V) characteristics were systematically measured, analyzed, and compared. The ($\overline {\textsf {2}}01$) and (010) SBDs exhibited on-resistances (${R}_{{ \mathrm{\scriptscriptstyle ON}}}$) of 0.56 and $0.77~\textsf {m}\Omega \cdot \textsf {cm}^{{\textsf {2}}}$ , turn- ON voltages (${V}_{{ \mathrm{\scriptscriptstyle ON}}}$) of 1.0 and 1.3 V, Schottky barrier heights (SBHs) of 1.05 and 1.20 eV, electron mobilities of 125 and 65 cm2/($\textsf {V}\cdot ~\textsf {s}$), respectively, with an on-current of ~1.3 kA/cm2 and on/off ratio of ~109. The (010) SBD had a larger ${V}_{{ \mathrm{\scriptscriptstyle ON}}}$ and SBH due to anisotropic surface properties (i.e., surface Fermi level pinning and band bending), as supported by X-ray photoelectron spectroscopy measurements. Temperature-dependent I–V also revealed the inhomogeneous nature of the SBH in both devices, where the ($\overline {\textsf {2}}01$) SBD showed a more uniform SBH distribution. The homogeneous SBH was also extracted: 1.33 eV for the ($\overline {\textsf {2}}01$) SBD and 1.53 eV for the (010) SBD. The reverse leakage current of the devices was well described by the two-step trap-assisted tunnelingmodel and the 1-D variable range hopping conduction model. The ($\overline {\textsf {2}}01$) SBD showed a larger leakage current due to its lower SBH and/or smaller activation energy, and thus a smaller breakdown voltage. These results indicate that the crystalline anisotropy of $\beta $ -Ga2O3 can affect the electrical properties of vertical SBDs and should be taken into consideration when designing $\beta $ -Ga2O3 electronics. [ABSTRACT FROM AUTHOR]

In this paper, we investigated the influence of both source gas and deposition temperature in plasma-enhanced chemical vapor deposition (PE-CVD) for a SiO2 passivation layer on the electrical properties and reliability of a bottom-gate In–Ga–Zn–O thin-film transistor (IGZO TFT). Two gas chemistries consisting of SiH4–N2O–N2 and tetraethoxysilane (TEOS)–O2 were utilized as the source gases for the PE-CVD SiO2 deposition, and the deposition temperature (${T}_{D}$) was adjusted from 180 °C to 380 °C. The TFT properties were basically identical for both gas chemistries at ${T}_{D}$ of 180 °C. When ${T}_{D}$ increased to 300 °C or higher, the TFTs with the SiO2 passivation deposited by SiH4–N2O–N2 gas chemistry (SiH4-SiO2) drastically changed from the transistor to the conductor. In contrast, the TFT with TEOS-SiO2 passivation maintained its TFT characteristics even at ${T}_{D}$ of 380 °C, despite the degradation of subthreshold characteristics and a negative shift of turn-on voltage were observed due to an electron injection barrier lowering as ${T}_{D}$ increased to 310 °C or higher. We also revealed that a stacked SiO2 passivation that is deposited at a different ${T}_{D}$ is an effective technique to improve the performance and reliability of the IGZO TFT. [ABSTRACT FROM AUTHOR]

The effects of the internal gain originated from the trapping of minority carriers and illumination-induced stored charges have been investigated systematically in MgZnO metal–semiconductor–metal (MSM) photodetectors (PDs) by a proposed semianalytical equivalent circuit model with the basic semiconductor equations and the external parasitic elements taken into account. To verify the accuracy and effectiveness of this model, the simulated steady and transient results are compared with the reported experimental data. It is found that a fall time of 400 ns, much longer than the response time with no internal gain, is attributed to the hole trapping process, inducing an internal gain with a value of 181. In addition, for the high input optical pulse energy (above 10 pJ), the time-delay of the response is caused by the stored charges. This paper indicates that it is very important to improve the MgZnO thin-film quality and balance the optical gain with the response speed. Meanwhile, a reasonable compromise should be found between the energy level of the optical pulse and the bias voltage to minimize the stored charges effect for practical applications. This paper is helpful for the design of high-speed and high-power MgZnO MSM PDs. [ABSTRACT FROM AUTHOR]

This paper revisits the physics of current filamentation in grounded-gate NMOS (ggNMOS) devices and presents new physical insights which were not addressed in earlier works. A clear distinction between electrical and thermal instabilities is presented. Moreover, filament dynamics under electrical and thermal instability in both silicided and silicide blocked devices is discussed while highlighting observations which contradict with established theory of current ballasting. Interplay between electrical and thermal instabilities and its dependence on the presence or absence of silicide blocking is explored further. Filament spreading in ggNMOS devices and it is dependence on silicide blocking is discussed. Finally, while using the developed physical insights, missing correlation between TLP and HBM extracted failure current of silicided ggNMOS device is explained. [ABSTRACT FROM AUTHOR]

Resistive random access memory is known as a type of nonvolatile memory. An abnormal volatile memory characteristic of a normal ZnSnO resistive memory is first demonstrated in this paper. Although the ${I}$ – ${V}$ curves exhibit a normal and stable resistive switching memory behavior, the resistance state is found to be only determined by the initial applied voltage along with the voltage sweep direction. It is set/reset processes free. Namely, it is volatile. The resistance states are found to be dominated by trap-assisted tunneling, trap-controlled space-charge-limited conduction, and hopping transport. Different resistance states are related to different carrier transport mechanisms. Each resistance state can independently and repeatably appear for over 1000 voltage sweeps. The ratio of the high-resistance state to the low-resistance state is $\sim 3\times 10^{2}$. [ABSTRACT FROM AUTHOR]

Through numerical simulations corroborated by an analytical subthreshold model considering drain coupling, this paper systematically investigates the short-channel effects in negative-capacitance FETs with 2D MoS2 channel (2D-NCFET). Our study indicates that, due to the impact of drain coupling on the negative-capacitance effect, the 2D-NCFET exhibits distinct short-channel behaviors such as improved average subthreshold swing and threshold-voltage roll-up with decreasing gate length. In addition, the fringe field through the high-k interlayer dielectric can significantly alter the subthreshold characteristics of the short-channel 2D-NCFET, and hence needs to be carefully taken into account. Our study may provide insights for device design using negative-capacitance FETs. [ABSTRACT FROM AUTHOR]

In this paper, design of an ultracompact bandpass filter (BPF) in GaAs technology without compromising its electrical performance is investigated by means of both theoretical analysis and electromagnetic simulation. In particular, the relationship between the external quality factor and the coupling coefficient of the second-order BPF is formulized to better understand the principle of the mutual coupling effect. To prove the concept, the designed filter is implemented in a commercial 0.1-µm GaAs technology. A step-by-step design guideline is elaborated. The BPF has not only the merits of ultracompactness, but also remarkable insertion loss (IL) compared with other state-of-the-art on-chip designs. The measurement results show that the 1-dB bandwidth of the BPF is from 28 to 36 GHz, while the IL is less than 1 dB at 29.5 GHz. In addition, more than 40-dB rejection is achieved from 56 to 69 GHz. The size of the filter is only 230 x 280 µm², excluding the pads, which is equivalent to 0.074 x 0.09 λg² at 28 GHz. To the best of our knowledge, the proposed design is known to be the most compact one in the open literature using GaAs technologies. [ABSTRACT FROM AUTHOR]

A gate engineered InGaN dopingless tunnel FET (DL-TFET) using the charge plasma concept is proposed and investigated by silvaco Atlas simulation. In0.75Ga0.25N is a direct gap semiconductor, and the effective tunneling mass of electron and hole is smaller than that of silicon, which induces that the drain current and average subthreshold swing (SSavg) of InGaN DL-TFET improve 1.3 x 10² times and 51.1% than that of Si DL-TFET at the overdrive voltage of 0.5 V, respectively. What is more, better device performances are achieved by gate engineering with appropriate "In" fraction, proper space between the gate and source (Lgs), and appropriate tunneling gate work function (ΦTG). The direct-current, RF, and energy-efficient performance studies show that SSavg of 7.9 mV/dec, an on-state current (ION) of 8.02 x 10-5 A/µm, a cutoff frequency (fT) of 119 GHz, and an energy delay product of 0.64 fJ-ps/µm can be obtained in the proposed TFET. This paper indicates that the gate engineered InGaN DL-TFET is a promising TFET for low-power RF and digital logic applications. [ABSTRACT FROM AUTHOR]

Write-once-read-many-times (WORM) characteristics of sol-gel InZnO (IZO) thin films are investigated in this paper. The Ag/IZO/n+-Si WORM memory exhibits a poor read disturb immunity. Although a postannealing process is capable of improving the performance due to formation of a thin interfacial AgxO layer, the memory window is only 5 x 10² and the resistance in high resistance state degrades dramatically during read disturb testing. By replacing the Ag electrode with an Al electrode, without the postannealing process, the Al/IZO/n+-Si WORM memory shows a superior read disturb immunity and a large memory window of 4 x 10³. The read endurance is over 104 cycles. X-ray diffraction, X-ray photoelectron spectroscopy, transmission electron microscopy, and energy dispersive spectroscopy were utilized to investigate the physical mechanisms of the WORM characteristics. The carrier conduction mechanisms were also explored. [ABSTRACT FROM AUTHOR]

From man-made satellites and interplanetary missions to fusion power plants, electronic equipment that needs to withstand various forms of irradiation is an essential part of their operation. Examination of total ionizing dose (TID) effects in electronic equipment can provide a thorough means to predict their reliability in conditions where ionizing dose becomes a serious hazard. In this paper, we provide a historical overview of logic andmemory technologies that made the biggest impact both in terms of their competitive characteristics and their intrinsically hardened nature against TID. Further to this, we also provide guidelines for hardened device designs and present the cases where hardened alternatives have been implemented and tested in the lab. The technologies that we examine range from silicon-on-insulator and FinFET to 2-D semiconductor transistors and resistive random access memory. [ABSTRACT FROM AUTHOR]

An extensive investigation of fabricated AlGaN/GaN fin-shaped metal-insulator-semiconductor high-electron-mobility transistors (Fin-MISHEMTs) with Al2O3 dielectric is presented in this paper. Based on the pulsed I-V measurements and numerical simulation, the dynamic characteristics of GaN-based Fin-MISHEMTs were carried out under various quiescent bias conditions and temperatures. Moreover, the physical mechanisms of current collapse and dynamic on-resistance increase induced by trapping effects were analyzed. The results show that the observed nonmonotonic variation of current collapse with the gate quiescent bias voltage is resulted from the combination of gate leakage injection-related and hot-electron injection-related trapping effects. Compared with the conventional planar MISHEMTs, the current collapse of AlGaN/GaN Fin-MISHEMTs is smaller due to lower gate leakage and smaller threshold voltage shift, which is benefited from its enhanced gate controllability. The current collapse and dynamic on-resistance increase of Fin-MISHEMTs can be further suppressed by optimizing the device structure, such as designing the fin channels only under the gate. [ABSTRACT FROM AUTHOR]

This paper utilizes electrical analyses and a study of physical mechanisms to investigate metal gate structure-dependent performance in amorphous InGaZnO (a-IGZO) thin-film transistors. The effects of different shielding areas between the IGZO layer and metal gate are investigated. In devices with shorter metal gate lengths, an abnormal rise in capacitanceat the off-state in capacitance--voltage ( C-V) characteristic curves can be observed. This can be attributed to the stronger electric field induced by the edge of themetal gate under bias sweepwhen themetal gate length is shorter than the IGZO layer length. Light illumination measurements indicate a negative shift in threshold voltage and an increase in subthreshold-leakage current regardless of relative metal gate length. Moreover, negative threshold voltage shift becomes more severe with a more obvious hump in C-V characteristic curves under backlight illumination of a shorter width device, a phenomenon which has been verified by simulation. [ABSTRACT FROM AUTHOR]

In the last years,memristor devices have been proposed as key elements to develop a new paradigm to implement logic gates. In particular, the memristor-based material implication (IMPLY) gate has been presented as a potential powerful basis for logic applications. In the literature, the IMPLY operation has been widely simulated, but most of the efforts have been just focusedon accomplishing its truth table, only considering the initial and final states of the gate. However, a complete understanding of the time evolution between states is stillmissing and barely reported yet. In this paper, the time evolution of the memristors involved in an IMPLY gate are studied in detail for every case of the gate. Furthermore, the impact on IMPLY gate operation of the internal resistor connected in series with the memristors of the IMPLY gate is included. [ABSTRACT FROM AUTHOR]

A new oscillational phenomenon has been found in high-biased semi-insulating (SI) 4H-SiC photoconductive semiconductor switches (PCSSs) with high densities of vanadium and nitrogen dopants, and this oscillational phenomenon has no relationship with the laser wavelength, bias voltage, the charge capacitor, and the shape/size of the 4H-SiC PCSS. This paper shows that the photo activated charge domain theory in SI GaAs PCSS may explain this phenomenon. Due to the high densities of vanadium and nitrogen dopants, the intervalley scattering may occur in the 4H-SiC PCSS, and the space charge field region will appear in the 4H-SiC PCSS for the electrons accumulation. This region looks upon an equivalent capacitor, when the accumulation of the electrons is over, the equivalent capacitor will discharge, and the oscillational phenomenon appears. [ABSTRACT FROM AUTHOR]

Due to high surface-to-volume ratio, surface traps play crucial role in electronic properties of semiconductor nanowires and nanowire-based devices. Recently, it was experimentally demonstrated that surface traps even can induce conductivity type inversion in semiconductor nanowires. Here, we have performed theoretical and numerical analyses to investigate the influence of surface traps on semiconductor nanowire conductivity including possible inversion due to surface traps. The Poisson equation with consideration of both type of mobile charges and ionized donors was solved having surface trapped charges in Neumann boundary conditions. Different semiconductor materials and surface trap densities have been considered. Calculations were done considering single energy level of surface traps and then the results were generalized to exponential energetic distribution of surface states density. The effect of surface traps was analyzed both for low-doped and highly doped nanowires. It was shown that for moderate or lightly doped NWs, the conductivity type switching from n- to p-type can occur at small radii. The developed potential-based analytical model allows calculating the inversion charge raised due to surface traps. The accuracy of analytical calculations has been validated with TCAD simulations and qualitatively compared with published experimental data. This paper is useful for design optimization of nanowire-based photodetectors, sensors, and reconfigurable FETs. [ABSTRACT FROM AUTHOR]

In this paper, we propose a vertical transistor with n-bridge and body on gate (BOG-DRAM) for Low-power 1T-DRAM application. The vertical channel of the device can reduce the short-channel effect and improve scalability. The storage region stacked on the gate leads to the efficient utilization of storage space. The device with junctionless channel layers on three sides can improve writing time. The conventional current bridge device only has one side gatecontrol depletion region, but the proposed BOG-DRAM has triple-side gate-control depletion region which can improve programming window at shorter gate lengths. BOG-DRAM achieves programming window of 33.6 μA/μm when the storage length is 20 nm. In addition, the work function offset is exploited for low-power application. [ABSTRACT FROM AUTHOR]

In this paper, we have demonstrated an oxygen-vacancy-based bipolar RRAM on a pure logic 14-nm-node HKMG FinFET platform. A unit cell of the memory consists of a control transistor (FinFET) and a storage transistor (a second FinFET). The later performs as a bipolar RRAM. This unit cell can be integrated in an AND-type memory array. The memory cell has an ON/OFF ratio equal to 200 and 400 for the n-type and p-type FinFET RRAMs, respectively, endurance larger than 400 and 1000 times for n- and p-type devices, respectively, and the retention test for over 1 month under 125°C temperature environment. To analyze the array performance of the AND-type FinFET RRAM at the circuit level, we have further discussed the issues of the sneak path and disturbance, in which an active-fin isolation of FinFET in an AND-type array has been suggested to minimize the leakage current induced by sneak paths. The results have shown a large window with up to 103 ON/OFF ratio, 30% standby power reduction, and 90% active power reduction with reference to the conventional AND-type array. As a result, the bipolar FinFET RRAM exhibits great potential for the embedded memory applications, in particular it can be extended to 28-nm HKMG and the FinFET platform beyond 14-nm technology node, to fill the Moore's gap between the high-performance logic and the embedded memory. [ABSTRACT FROM AUTHOR]

This paper proposes a pull-up control scheme in the pseudo-CMOS inverter to design a low-power ring oscillator (RO) realized by only n-type transistors. For comparing 11-stages, the proposed RO and the conventional RO are both fabricated by metal-oxide thin-film transistors with the etch stop layer structure. It is measured that the power-delay product of the proposed RO is reduced by more than 50% under the same value of supply voltage. At the same oscillation frequency, the power consumption tends to be reduced by 18% as oscillation frequency increases. Furthermore, the peak-to-peak voltage of the proposed RO can almost receive a full swing at any supply voltage. [ABSTRACT FROM AUTHOR]

Characteristics of deep-ultraviolet (DUV) light-emitting diodes (LEDs) are investigated. DUV LEDs possess severe electron current leakage due to insufficient carrier confinement of the active region. Simply increasing the Al composition of quantum barriers (QBs) or electron-blocking layer (EBL) to enlarge the relevant potential barrier height would arise unexpected detrimental effects, such as extra polarization effect or more obstruction for hole injection. In this paper, band-engineered composition-graded QBs and EBL are proposed to resolve this issue. Simulation results show that, with appropriate designs, the leakage current of DUV LEDs could be effectively diminished with just slight side effects. [ABSTRACT FROM AUTHOR]

In this paper, we have investigated Ni-based AlGaN/GaN Schottky diodes comprising capping layers with silicon-technology-compatible metals such as TiN, TiW, TiWN, and combinations thereof. The observed change in Schottky barrier height of a Ni and Ni/TiW/TiWN/TiW contact can be explained by stress effects induced by the TiW/TiWN/TiW capping layer, rather than by chemical reactions at the metal–semiconductor interface. Secondary-ion mass spectroscopy and transmission electron microscopy techniques, for samples with and without a TiW/TiWN/TiW cap, have been used to show that no chemical reactions take place. In addition, electrical characterization of dedicated samples revealed that the barrier height of Ni/TiW/TiWN/TiW contacts increases after stepwise selective removal of the TiW/TiWN/TiW cap, thus demonstrating the impact of strain. [ABSTRACT FROM PUBLISHER]

Achieving high latch-up immunity is critical for power-rail electrostatic discharge (ESD) clamp circuits in high-voltage (HV) integrated circuit products. To investigate how shunt resistance affects the transmission line pulsing current–voltage characteristics of resistance-triggered stacked silicon controlled rectifiers (SCRs), a lateral SCR (LSCR) and a modified LSCR were combined in several SCR stacked structures with various shunt resistances. Compared with in tradition stacked ESD cells, the snapback margin of the SCRs does not expand and can even be reduced. A high holding voltage of 33.4 V is achieved using the resistance-triggered stacked SCR technique in a 0.11~\mu \textm 32-V HV process. A trigger voltage of approximately 51 V and a failure current of 3.3 A is achieved in this experiment. According to theorem analysis based on a voltage decoupling equation, the minimum trigger voltage can probably be further reduced to 46 V by using the resistance-triggered stacked SCR technique. This paper can offer a simple guideline for designing ESD protection circuit using the resistor-triggered SCRs stacking structure. [ABSTRACT FROM PUBLISHER]

In this paper, an analytical model of insulated gate bipolar transistor (IGBT) on-state voltage ( V\mathrm {{ {{ON}}}} ) and turn-off loss ( E\mathrm {{ {{OFF}}}} ) is developed to find the optimum solution (minimum power loss) for a given application. With this model, it is found that IGBT on-state voltage is limited by the fact that holes can only flow from the anode to the cathode. The minimum on-state voltage for a Si IGBT with 110- \mu \textm wide drift region is found out to be around 0.835 V at 100 A/cm2 and room temperature. For a given operating frequency and chip size, a tradeoff between on-state voltage and turn-off loss that gives minimum device power loss can be achieved by manipulating the carrier profile in the drift region with an optimum structure design. This minimum device loss decreases mildly with increasing chip size, i.e., a merely 45% loss reduction when the chip size increases from 0.2 to 5 cm2. These results clearly indicate that the performance of an IGBT is not area sensitive. They are encouraging for device manufacturers who wish to reduce the device chip size to lower cost. However, the constraint comes from the device thermal dissipation capabilities which decrease quickly with decreasing chip size. These results are validated with numerical 2-D device simulations for a large variety of device structures, chip size, and operating frequencies (2 to 200 kHz). State-of-the-art IGBT product performance is compared against the theoretical limit indicating there is still substantial room for improvement at low and high frequencies. [ABSTRACT FROM PUBLISHER]

With the aid of an analytical and scalable model, this paper explores the design space for negative-capacitance (NC) field-effect transistors (FETs) with a 2D semiconducting transition-metal-dichalcogenide channel. In addition, the impact of back-gate biasing on the design space and the body effect of 2D-NCFETs is also investigated. Our study indicates that, to mitigate the conflict between subthreshold swing and hysteresis and to maximize the design space for the 2D-NCFET, a thin buried oxide and an adequate reverse back-gate bias can be applied to achieve the optimum design. [ABSTRACT FROM PUBLISHER]