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This Special Issue of the IEEE Transactions on Electron Devices will feature the most recent developments and the state of the art in the field of ultra wide band gap semiconductors and devices for power control and conversion, including both experimental results and theoretical developments. Papers must be new and present original material that has not been copyrighted, published or accepted for publications in any other archival publications, that is not currently being considered for publications elsewhere, and that will not be submitted elsewhere while under considerations by the Transactions on Electron Devices. Topics of interest include, but are not limited to: IDtra Wide Band Gap Materials: Advances in material synthesis, defect characterization, transport and high-field properties, and material-level integration; evaluation of fundamental materials-limited figures of merit; Power Devices: Vertical and lateral MOSFETs, HEMTs and MIS-HEMTs, IGBTs, Schottky and pn junction rectifiers, and other device concepts; fabrication and device characterization; designs and device structures for controlling field profiles, edge termination; Thermal Management: Approaches to mitigate thermal effects in power devices using ultra wide band gap materials; Integration: Monolithic and heterogenous integration for system-level applications using ultra wide band gap materials. Integration with Si or other semiconductors for system-on-chip and system-in-package implementations, including heterogenous and package-level integration for high-performance power conversion applications. [ABSTRACT FROM AUTHOR]

The first part of this paper presented mymargin the device-level comparison of emerging materials (In0.53Ga0.47As and 2-D materials) and device architecture (NW FETs) with s-Si FinFETs. In order to further understand the performance and energy efficiency of these device options for future technology nodes, it is required to go beyond the device-level comparison by accounting for not only intrinsic but also the extrinsic parasitic elements. In this paper, we present the comparison of s-Si, In0.53Ga0.47As, and 2-D material-based n-type MOSFETs using the circuit-level figure of merits across three successive future technology nodes. The analysis incorporates both device characteristics obtained from an advanced quantum mechanical simulation tool and circuit-level comparison, which accounts for device parasitic elements and wiring load. The results show that 2-D material DG MOSFETs present a more energy-efficient device option than s-Si and In0.53Ga0.47As FinFETs in sub-0.7-V supply voltage regime and In0.53Ga0.47As nanowire (NW) FETs can outperform s-Si multi-gate (MuG) FETs and 2-D material FETs, but when considering non-idealities, s-Si NW FETs remain both faster and more energy-efficient device option. [ABSTRACT FROM AUTHOR]

The dielectric screening property of a semiconductor is very crucial for the electrical characteristics of a MOSFET, and which can be described mathematically by Poisson equation via the permittivity. While the theory and experiments have corroborated the permittivity reduction of nanoscale Si, this paper studies the electrical characteristics of MOSFETs considering the reduced channel permittivity by quantum transport simulations. It is found that the channel permittivity reduction may mitigate the short-channel effects, showing subthreshold swing improvement and threshold voltage shift of MOSFETs in nanoscale. Compared to quantization effects, the positive and negative impacts of the channel permittivity reduction on the devices in particularly nanoscale have been investigated. This paper elucidates the necessity of considering semiconductor permittivity reduction for nanoscale device design and simulations. [ABSTRACT FROM AUTHOR]

This paper presents an optoelectronics-based compact equivalent circuit model of an n-Ge/p-Ge1–xSnx/n-Ge1–xSnx heterojunction phototransistor (HPT). This paper includes the static electrical and optical characteristics of the device, Gummel characteristics, effect of temperature, and overall noise analysis of HPT based on various parametric variations. We then investigate the effect of parasitic capacitance on the noise performance of the HPT. The estimated results show that the signal-to-noise ratio (SNR) is strongly dependent on not only the operating frequency but also the operating temperature and applied base-bias voltage. Estimated performance shows that SNR of HPT >90 dB up to 100 GHz and >80 dB up to 50 °C can be achieved, which ensured the operation of the device as high-speed and low-noise detector. [ABSTRACT FROM AUTHOR]

In this paper, we have developed a physics-based analytical model for the electrical characteristics of passivated silicon carrier-selective contact (CSC) solar cells and validated it with numerical simulations. The model comprises analytical solutions of: 1) the Poisson equation, accurately capturing the level of inversion and accumulation at the crystalline silicon (c-Si) layer interfaces, and 2) the recombination current capturing the various recombination mechanisms at work in the solar cell. The calculations establish that CSC solar cells have the potential to achieve an efficiency greater than 26% even when both c-Si interfaces have realistic SRV values of 100 cm/s. The model helps illustrate the physics underlying the performance of CSC solar cells for variation in key device parameters such as surface recombination velocities, bulk lifetime, contact layer doping, and amorphous silicon (a-Si) thickness amongst others. By circumventing the need for resource-intensive numerical simulations, the analytical model described in this paper can assist in the design and development of high-performance CSC solar cells. [ABSTRACT FROM AUTHOR]

In this paper, an analytical model has been developed to observe the recombination losses involved in a tunnel oxide passivated contact solar cell with a carrier-selective layer constituting polycrystalline silicon (poly-Si). The main focus of this paper is to observe the contribution of each component of recombination current density and its effect on open-circuit voltage, Voc. The effect of emitter saturation current density (Joe), surface recombination velocity, substrate thickness, and doping density of carrier-selective layer on Voc has been presented. The analysis indicates that Voc = 766 mV can be achieved for Joe = 2 fA/cm2, and a doping density of poly-Si > 1021cm−3 in a c-Si/SiO2/poly-Si contact for a 50- $\mu \text{m}$ -thick substrate in case of ideal surface passivation. For identical conditions, Voc attains a lower value of 750mV for a 180- $\mu \text{m}$ -thick substrate. The dependence of Voc on bandgap of tunnel layers has also been observed by considering other materials like Si3N4 and SiC. These results from the analyticalmodel have been compared with results froma simulation using automat FOR simulation of HETerostructures v2.5 and have been found to be in good agreement with each other. [ABSTRACT FROM AUTHOR]

In this paper, we propose a model for estimating short-channel effects (SCEs) in the shell-doped double-gate junctionless (JL) MOSFET. The main emphasis of this paper is to estimate SCEs by effectively capturing source/drain (S/D) extensions beyond the gate edges for different values of undoped core thickness (${T}_{\textsf {core}}$), shell doping (${N}_{\textsf {d}}$), gate length (${L}_{\textsf {g}}$), and gate (${V}_{\textsf {gs}}$) and drain (${V}_{\textsf {ds}}$) biases in subthreshold regime. The threshold voltage (${V}_{\textsf {th}}$), drain-induced barrier lowering and subthreshold swing (${S}$), extracted from transfer characteristics, are in good agreement with the simulation results. Results highlight the utility of shell doping and core thickness to provide an additional degree of freedom to control SCEs. The proposed model can be useful in estimating SCEs and optimizing core–shell JL architecture for low-power applications. [ABSTRACT FROM AUTHOR]

In this paper, the threshold voltage characteristics of silicon nanowire metal–oxide–semiconductor field-effect transistor (MOSFET) with a double-layer gate structure are presented. This type of device is considered to be the most promising application of nanodevice in ultralarge-scale integration, due to several advantages such as similar operation principle as the junctionless nanowire transistor, the screening effect of the upper gate (UG) to shield the lower gate MOSFETs from external electromagnetic disturbance, the tradeoff between the short channel and the thick-gate oxide layer, and the compatible fabrication process with the conventional MOS technology. In this paper, the relations of threshold voltage versus the gate length, the UG bias, the substrate bias, the drain bias, and the temperature are measured and analyzed. Moreover, the penetration effect of the UG electric field is proposed to interpret the short-channel characteristics of the device, and a piecewise curve model is presented to reveal the underlying physics of the relation of the threshold voltage versus the drain bias. The double-layer gate structure technology enables the design of many devices, such as small-signal analog circuit units, single-electron devices, and quantum bit cells. [ABSTRACT FROM AUTHOR]

In part I of this paper, we developed physical insights into the role and impact of acceptor and donor traps—resulting from C-doping in GaN buffer—on avalanche breakdown in AlGaN/GaN HEMT devices. It was found that the donor traps are mandatory to explain the breakdown voltage improvement. In this paper, silicon doping is proposed and explored as an alternative to independently engineer donor trap concentration and profile. Keeping in mind the acceptor and donor trap relative concentration requirement for achieving higher breakdown buffer, as depicted in part I of this paper, silicon & carbon codoping of GaN buffer is proposed and explored in this paper. The proposed improvement in breakdown voltage is supported by physical insight into the avalanche phenomena and role of acceptor/donor traps. GaN buffer design parameters and their impact on breakdown voltage as well as leakage current are presented. Finally, a modified Si-doping profile in the GaN buffer is proposed to lower the C-doping concentration near GaN channel to mitigate the adverse effects of acceptor traps in GaN buffer. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, we demonstrate the improvement in power capability and safe operating area of silicon-on-insulator laterally double-diffused MOS (SOI-LDMOS) transistors for power amplifier applications by the introduction of a partial n+ buried layer (PNBL). The power capability of a transistor can be evaluated by ${P}_{\text {max}}/A$ , which is the maximum power per unit area that can be delivered by the transistor and is an important parameter for power amplifiers. ${P}_{\text {max}}$ is dependent on the snapback voltage (${V}_{\text {sb,QS}}$), OFF-state breakdown voltage (${V}_{\text {bd}, \mathrm{\scriptscriptstyle OFF}}$), and maximum current (${I}_{\text {max}}$) in the quasi-saturation regime of an LDMOS transistor. Increase of ${P}_{\text {max}}/A$ by the introduction of a PNBL in the SOI-LDMOS transistors is reported in this paper. The effects of variation of the length, thickness, and doping concentration of the PNBL on ${V}_{\text {sb,QS}}$ and ${P}_{\text {max}}/A$ are analyzed in detail. It is shown that by optimizing the doping and length of the PNBL layer, the maximum power output from the transistor can be made significantly higher than that of a conventional device without PNBL. A procedure to design the optimized structure is also presented. [ABSTRACT FROM AUTHOR]

Esaki diodes based on interband tunneling have the characteristics of negative differential resistance (NDR) and ultrafast transient time, which lead to broad applications including oscillators, multivalue memories, and terahertz detectors. In this paper, we present the first demonstration of Esaki diodes based on 2-D/3-D heterojunctions—more specifically, chemical vapor deposition MoS2 on degenerately doped silicon. As compared to traditional 3-D heterostructures, these 2-D/3-D heterostructures have the following advantages: dislocation-free 2-D crystals even when the lattices are mismatched, dangling bond-free surface, and capability for large-scale synthesis at low cost. In this paper, monolayer, bilayer, and trilayer MoS2 are synthesized directly on degenerated Si substrate, forming the ultraclean heterostructures without surface contamination from tape and resist. Based on these pristine heterostructures, we are able to observe prominent NDR effect at room temperature. This NDR effect is attributed to the degenerately p-type doping in silicon and the natural n-type doping in MoS2. We also found that the peak voltage corresponding to the local maximum tunneling current depends on the MoS2 thickness. While MoS2 is changing from the monolayer (0.7 nm) to bulk (9.5 nm), the peak voltage increases from 0.8 to 1.6 V. This phenomenon can be explained by the energy-level differences between the monolayer and bulk MoS2. This paper provides the experimental groundwork for the synthesis of transition metal dichalcogenides on degenerately doped Si substrates and opens up new and exciting opportunities for electronic applications of 2-D/3-D heterostructures. [ABSTRACT FROM AUTHOR]

In 2-D van der Waals heterostructures, interactions between atomic layers dramatically change the vibrational properties of the hybrid system and demonstrate several interesting phenomena that are absent in individual materials. In this paper, we have investigated the vibrational properties of the heterostructure between transition metal dichalcogenide (TMD) and hexagonal boron nitride (hBN) on gold film at low- and high-frequency ranges by Raman spectroscopy. Nineteen Raman modes have been observed from the sample, including a new interlayer coupling mode at 28.8 cm−1. Compared to reported experimental results of tungsten disulfide (WS2) on SiO2/Si substrates, the Raman spectrum for WS2 on hBN/Au emerges a blue shift of about 8 cm−1. Furthermore, a remarkable enhancement of Raman intensity can be obtained when tuning hBN thickness in the heterostructure. Through systematic first-principles calculations, numerical simulations, and analytical calculations, we find that the 28.8 cm−1 mode originates from the shearing motion between monolayer TMD and hBN layers. In addition, the gold substrate and hBN layers form an optical cavity and the cavity interference effects enhance the obtained Raman intensity. This paper demonstrates the novel vibrational modes of 2-D van der Waals heterostructure as an effective tool to characterize a variety of such heterostructures and reveals a new method to enhance the Raman response of 2-D materials. [ABSTRACT FROM AUTHOR]

In this paper, a n-type junctionless FET (JLFET) with a p-type fin body (FB) is investigated using a 3-D numerical simulator. We show that the proposed device (FB-JLFET) with a p+ FB can control the electrostatic potential of the channel more efficiently for multi- ${V} _{\text{TH}}$ (threshold voltage) and dynamic threshold (DT) operation. Moreover, body bias application is implemented in FB-JLFET and a large body factor ($\gamma $) is predicted for wide range ${V} _{\text{TH}}$ modulation. Thanks to the stronger potential coupling between the channel and FB, the proposed device exhibits $\gamma $ improvement compared to the conventional JL bulk FinFETs under the same electrostatic control. In addition, DT operation is studied in the form of a JLFET for the first time and it exhibits 37% improvement of the on-state drive current and better subthreshold swing (S.S.) compared to FB-JLFET without DT. This paper provides the feasibility of multi- ${V} _{\text{TH}}$ operation with body bias mode for high performance or low-power applications and DT operation for high-speed circuits with low power consumption. [ABSTRACT FROM AUTHOR]

This paper presents an extensive investigation of the impact of the resistivity of the silicon substrate on the vertical leakage and charge trapping in 200 V GaN-on-Si enhancement-mode high-electron mobility transistors. Three wafers having different substrate resistivities were submitted to combined DC characterization, step-stress experiments, and electroluminescence (EL) analysis. The results described within this paper demonstrate that: 1) the use of a highly resistive silicon substrate can increase the vertical breakdown voltage of the transistors, due to the fact that the voltage drop on the GaN buffer is mitigated by the partial depletion of the substrate (this latter causes a plateau region in the drain to substrate I–V characteristic) and 2) highly resistive substrate results in stronger trapping effects, due to the capacitance of the depleted substrate and the resulting backgating effects. The results described within this paper indicate that the choice of the resistivity of the substrate is the result of a tradeoff between high breakdown voltage (that could be in principle achieved through a highly resistive substrate) and the minimization of trapping processes (which can be hardly obtained with a resistive substrate). [ABSTRACT FROM AUTHOR]

With technology node scaling down to 5 nm, the narrow device geometry confines the material thermal conductivity and further aggravates the self-heating effect in gate-all-around (GAA) transistors. In this paper, we investigate the self-heating of horizontally stacked three-layer GAA nanosheet transistors by 3-D finite-element modeling (FEM) simulation. The anisotropic thermal conductivity of nanosheets with the dependence of silicon thickness and temperature is implemented in the FEM simulator to evaluate thermal behavior accurately. The impact of layout design on thermal properties is investigated comprehensively from single device to device arrays with implication on electrical performance. The results indicate that the width of nanosheet is the key parameter to make the tradeoffs between self-heating and electrical characteristic. Meanwhile, the optimizations of layout design are given to suppress the thermal effects, including self-heating, nonuniformity of temperature, and thermal crosstalk at device level. This paper will provide guidelines for layout design, thermal management, device performance, and thermal-aware reliability prediction in the GAA-stacked structure. [ABSTRACT FROM AUTHOR]

In this paper, we explored the characteristic fluctuations induced by various random discrete dopants (RDDs) on gate-all-around silicon nanowire metal–oxide semiconductor field-effect transistors. A 3-D quantum-mechanically corrected transport model was employed to analyze the simulated devices. The statistical results indicate that the variation of threshold voltage ( ${V}_{\text {th}}$ ) not only can be reduced from 28.6% to 10.7% without channel doping and penetration from the source/drain into the channel, but also the variation of 3-dB frequency can be reduced from 8% to 2.7% due to the reduction of the variation of ${V}_{\text {th}}$. We reported that the high-frequency characteristic fluctuations (voltage gain and cutoff frequency) were dominated by electron mobility. This caused by RDDs from the drain extension exhibited less variability than that caused by RDDs from the source extension due to a reduced injection velocity near the S side and a negligible difference in the electron saturation velocity near the D side. This paper provides pertinent information on the design of high-frequency amplifier circuits in relation to devices with RDDs induced by variations in the semiconductor process. [ABSTRACT FROM AUTHOR]

This paper presents experimental and simulation analysis of an $\Omega $ -shaped silicon junctionless nanowire field-effect transistor (JL-NWT) with gate lengths of 150 nm and diameter of the Si channel of 8 nm. Our experimental measurements reveal that the ON-currents up to 1.15 mA/ $\mu \text{m}$ for 1.0 V and 2.52 mA/ $\mu \text{m}$ for the 1.8-V gate overdrive with an OFF-current set at 100 nA/ $\mu \text{m}$. Also, the experiment data reveal more than eight orders of magnitude ON-current to OFF-current ratios and an excellent subthreshold slope of 66 mV/dec recorded at room temperature. The obtained experimental current–voltage characteristics are used as a reference point to calibrate the simulations models used in this paper. Our simulation data show good agreement with the experimental results. All simulations are based on drift-diffusion formalism with activated density gradient quantum corrections. Once the simulations methodology is established, the simulations are calibrated to the experimental data. After this, we have performed statistical numerical experiments of a set of 500 different JL-NWTs. Each device has a unique random distribution of the discrete dopants within the silicon body. From those statistical simulations, we extracted important figures of merit, such as OFF-current and ON-current, subthreshold slope, and voltage threshold. The performed statistical analysis, on samples of those 500 JL-NWTs, shows that the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic is in excellent agreement with the experimental measurements. Moreover, the mean ${I}_{D} - {V}_{\text {Gs}}$ characteristic reproduces better the subthreshold slope data obtained from the experiment in comparison to the continuous model simulation. Finally, performance predictions for the JL transistor with shorter gate lengths and thinner oxide regions are carried out. Among the simulated JL transistors, the configuration with 25-nm gate length and 2-nm oxide thickness shows the most promising characteristics offering scalable designs. [ABSTRACT FROM AUTHOR]

Transconductance efficiency ( gm/{I}D ) is an essential design synthesis tool for low-power analog and RF applications. In this paper, the invariance of gm/{I}D versus normalized drain current curve is analyzed in an asymmetric double-gate (DG) fully depleted MOSFET. This paper studies the breakdown of this invariance versus back-gate voltage, transistor length, temperature, drain-to-source voltage, and process variations. The unforeseeable invariance is emphasized by measurements of a commercial 28-nm ultrathin body and box fully depleted Silicon-on-Insulator (SOI) (FDSOI) CMOS technology, thus supporting the gm/{I}D -based design methodologies usage in DG FDSOI transistors sizing. [ABSTRACT FROM AUTHOR]

One shortcoming of capacitive micromachined ultrasonic transducers (CMUTs) for commercial use is the weak output power relative to traditional ultrasonic transducers. Recently, we reported an annular CMUT cell with an improved transmit efficiency over a conventional circular cell in air. Extending this paper, we designed and fabricated a nine-element concentric CMUT array to enhance the transmit power and offer depth focusing. The proposed 200-kHz array has an aperture diameter of 2.13 cm and a fill factor of 81%. A pillar-free etching process was developed to create the deep large-area cavities of the proposed wafer-bonded CMUT. The fabricated device was characterized for the static and dynamic performance using a profilometer and a laser Doppler vibrometer, respectively. The average maximum plate dynamic displacements of the CMUT driven by 20-Vpp ac excitation voltage at dc biases of 100 and 150 V were measured to be 1.28 and 1.97 μm, respectively. Accordingly, the surface output power densities were calculated to be 0.40 and 0.96 KW/m2. We investigated the crosstalk between neighboring cells and the plate-cracking phenomenon, and provided relative suggestions for improvement. This paper demonstrates the feasibility of the concentric annular-cell CMUT array design for air-coupled applications. [ABSTRACT FROM PUBLISHER]

The main purpose of this paper is to introduce an ultracompact device for electrostatic discharge (ESD) protection based on a bipolar metal oxide silicon (BIMOS) transistor merged with a dual back-to-back silicon-controlled rectifier (SCR) for bulk and for ultrathin body box fully depleted (FD)-silicon on insulator (SOI) advanced CMOS technologies in the hybrid bulk thanks to process co-integration. It is well known that ESD protection is a challenge for IC in advanced CMOS technology. In this paper, an optimized solution is described through the concept, design, 3-D technology computer aided design (TCAD) simulation, and silicon characterization in 28-nm FD-SOI in hybrid bulk. Measurements are done thanks to transmission line pulsed (TLP), very fast TLP and dc behavior. Moreover, the overvoltage is investigated through very fast transient characterization system measurements. It demonstrates a promising candidate to protect against ESD event and to develop new ESD network dedicated to system on chip. [ABSTRACT FROM PUBLISHER]

In this paper, an innovative process flow developed to improve the thermal resistance of power ICs was presented. In this field, one of the major device failure mechanisms is related to the high temperatures reached during the working cycles due to the extremely critical electrical current densities. Therefore, heat transfer and dissipation are crucial aspects that need continuous improvements. Usual approaches to face this issue deal with package heat sinks design, solder selection, and wafer thinning. In this paper, a novel technological approach was settled, in which heat sinks microstructures were successfully integrated at wafer level stage on standard p-i-n diodes. To this aim, the bulk Si on the backside was partially replaced with Cu, a material characterized by a higher thermal conductivity material. Moreover, the well microstructures filled by Cu provide the advantage of wafer self-support, without requiring dedicated and more expensive thinning and handling technologies. An extensive characterization of the final devices was also carried out to evaluate the process and the thermal and electrical improvements. Finally, a failure analysis on selected devices was performed to identify any critical issue with the standard packaging process. [ABSTRACT FROM PUBLISHER]

In this paper, we develop an explicit model to predict the dc electrical behavior in ultrathin surrounding gate junctionless (JL) nanowire field-effect transistors (FETs). The proposed model considers 2-D electrical and geometrical confinements of carrier charge density within few discrete subbands. Combining a parabolic approximation of the Poisson equation, the first-order perturbation theory for the Schrödinger subband energy eigen-values and the Fermi–Dirac statistics for the confined carrier density lead to an explicit solution of the dc characteristic in ultrathin JL devices. Validity of the model has been verified with technology computer-aided design simulations. The results confirm its validity for all regions of operation, i.e., from deep depletion to accumulation and from linear to saturation. This represents an essential step toward analysis of circuits based on JL nanowire devices. [ABSTRACT FROM AUTHOR]

In this paper, alternative operational mode (AOM) of Si-based blocked impurity band (BIB) detectors is thoroughly investigated. The basic structure of the detector evolves from the prototype of the ion-implanted BIB detector, which is potentially compatible with CMOS processes. Benefiting from lower dark current, the detectivity of ion-implanted devices studied in this work is comparable with the Si BIB detectors ever reported. For ion implantation devices, a peak blackbody detectivity of ${5} \times {10}^{{12}}$ cm $\cdot $ Hz1/2/W (background temperature T = 40 K) occurs at 2 V under AOM. These merits make the ion-implanted device a powerful candidate for a wide range of applications from infrared to terahertz band. By analyzing the carrier distribution and the band structure in different functional regions of the device at the measured temperature, depletion junction formed in the region of active layer near active layer/cathode interface side is deduced when the device is operated under AOM. The theory is successfully used to interpret experimental data, including the detectivity comparable to the epitaxial device, significantly reduced dark current. [ABSTRACT FROM AUTHOR]

Silicon nanowire (SiNW) field-effect transistors (SiNWFETs) are of great potential as a high-sensitivity charge sensor. The signal-to-noise ratio (SNR) of an SiNWFET sensor is ultimately limited by the intrinsic device noise generated by carrier trapping/detrapping processes at the gate oxide/silicon interface. This carrier trapping/detrapping-induced noise can be significantly reduced by replacing the noisy oxide/silicon interface with a Schottky junction gate (SJG) on the top of the SiNW. In this paper, we present a tri-SJG SiNWFET (Tri-SJGFET) with the SJG formed on both the top surface and the two sidewalls of the SiNW so as to enhance the gate control over the SiNW channel. Both experiment and simulation confirm that the additional sidewall gates in a narrow Tri-SJGFET indeed can confine the conduction path within the bulk of the SiNW channel away from the interfaces and significantly improve the immunity to the traps at the bottom buried oxide/silicon interface. Therefore, the optimal low-frequency noise performance can be achieved without the need for any substrate bias. This new gating structure holds promises for further development of robust SiNWFET-based charge sensors with low noise and low operation voltage. [ABSTRACT FROM AUTHOR]

The gate–source overlap length (${L}_{{\text {OV}}}$) in the line tunneling FET (L-TFET) can be used as a design parameter to improve the analog circuit performance. In this paper, we investigate the drain current (${I}_{D}$) dependence on ${L}_{{\text {OV}}}$ , considering the electrostatics of the gate–source overlap region. It is observed that ${I}_{D}$ increases with ${L}_{{\text {OV}}}$ exhibiting a nonlinear behavior. This happens as the impact of the lateral electric field at the far end of the tunnel junction reduces, thereby reducing the tunneling rate. Based on our semiempirical physical ${I}_{D}$ – ${L}_{{\text {OV}}}$ model, a novel ${L}_{{\text {OV}}}$ variation-aware small signal model for L-TFET is also proposed. The output resistance and the gate–drain capacitance remain almost independent of ${L}_{{\text {OV}}}$ in the saturation regime. The gate–source capacitance and the transconductance linearly increase with ${L}_{{\text {OV}}}$. A common source amplifier is demonstrated with ~2.4 times increase in the voltage gain when ${L}_{{\text {OV}}}$ is increased from 20 to 50 nm, with a penalty of ~10% in the bandwidth. We observe that it is not possible to achieve the gain similar to one obtained using 2.5 times increase in ${L}_{{\text {OV}}}$ even after increasing the device width five times. However, the bandwidth reduces 30% at such width owing to an increase in the gate capacitances. [ABSTRACT FROM AUTHOR]

The impact of scaling of the base layer on the noise performance, spectral responsivity, and frequency response of Ge/Ge1–xSnx/Ge p-n-p heterojunction phototransistor (HPT) is presented and evaluated by simulation. The proposed structure consists of Ge1–xSnx alloy in the base layer, allowing extension of the photodetection to the mid-infrared (MIR) region, enabling photodetection over a wide range. This paper also includes the effect of Sn concentration and base bias voltage on the frequency performance of the HPT. In addition, various noise components and signal-to-noise ratio (SNR) are estimated as a function of base layer thickness and base resistance. The simulated results show that cutoff frequency (${f}_{T}$) and maximum frequency (${f}_{\text {max}}$) are not only strongly dependent on the base layer thickness but also on the Sn composition in the base layer and applied base-bias voltage. The results show that the proposed HPT provides higher ${f}_{T} >45$ GHz and SNR of >70 dB for the base layer thickness of 50 nm (with Sn = 9%) can be achieved. Therefore, the GeSn p-n-p HPT is promising for future fiber-optic telecommunication and MIR applications. [ABSTRACT FROM AUTHOR]

This paper proposes a strained Si-based single drift nano-mixed tunnel avalanche transit time (MITATT) oscillator capable of generating high RF power in the terahertz regime, inaccessible by conventional Si devices. The authors have developed a quantum modified classical drift-diffusion model to study the nanoscale properties of strained Si oscillator. The study reveals that 14.72-GW/m2 RF power could be generated from 0.715-THz strain-engineered Si oscillator. Such performance enhancement of the Si device is due to selective incorporation of trace amounts of Ge in the Si active region. This generates in-plane biaxial strain which in turn degrades the in-plane electron mobility, hence unsuitable for conventional MOSFETs. However, such strain remarkably enhances the out-of-plane mobility, and uniqueness of the current research is the utilization of in-plane strain to boost up the out-of-plane mobility depending on geometry and dimensions of the oscillator’s active region. The model incorporates parasitic series resistance and elevates junction temperature effects on terahertz properties of the device. Incorporation of the strained layer in the active region reduces the parasitic series resistance effect on high frequency properties of the oscillator. Validity of the developed model is established by comparing simulated data with the corresponding experimental observations. The authors have further studied photo irradiation effects on terahertz characteristics of the new class of devices. The structure-induced quantum confinement effect has made the Si-based active region to behave as a partially direct bandgap material, and therefore, a significant improvement is observed in optical sensitivity. To the best of the authors’ knowledge, this is the first report on strain-engineered asymmetrically doped Si/SiGe based avalanche photosensor in the high-frequency terahertz domain. [ABSTRACT FROM AUTHOR]

In this paper, we have reported a renovated silicon-based tunnel field-effect transistor (TFET) structure with a channel length of 21 nm. The proposed structure has been optimized and analytically modeled. The broken gate TFET (BG-TFET) shows very low ambipolar current, good subthreshold swing (SS) and ON-currents comparable to the contemporary structures of similar dimensions. The surface potential and the electric field inside the device are modeled by solving the 2-D Poisson’s equation. The drain current is also modeled based on Kane’s generation rate. The results obtained from the analysis are validated against Synopsys Sentaurus TCAD nonlocal tunneling model-based simulations. [ABSTRACT FROM AUTHOR]

This paper reports the fabrication of a broadband near-infrared response (vis-NIR) photodetector (PD) using Cu2SnS3 (CTS) quantum dots (QDs) as photoactive semiconductor material and graphene as a carrier transport medium. The QDs of earth abundant, nontoxic, and inexpensive CTS have been synthesized by solvothermal method, and the chemical vapor deposition (CVD) technique is used to synthesize few layers and monolayers of graphene. The fabricated CTS QDs/graphene/SiO2/Si PD demonstrated high values of responsivity (~110.089 A/W), detectivity ($\sim 1.25 \times 10^{{12}}\,\,\text {cm} \cdot \text {Hz}^{\text {1/2}} \cdot \text {W}^{-{1}}$), and quantum efficiency (~160.9) for broadband (vis-NIR) region due to high absorption coefficient of CTS QDs and very high mobility (~200 000 cm2/V–s) of graphene. The time-response analysis of PD was also performed under vis-NIR and ON and OFF time were found to be 10.2 and 11.34 s. [ABSTRACT FROM AUTHOR]

Self-heating in fully depleted silicon-on-insulator (FDSOI) metal–oxide–semiconductor field-effect transistors (MOSFETs) is experimentally studied using the gate resistance thermometry technique, in a wide temperature range from 300 down to 4.2 K. We demonstrate that below 160 K, the channel temperature increase ($\Delta {T}$) due to self-heating starts to deviate significantly from the linear variation with the dissipated power, leading to an apparent power dependent thermal resistance. This power dependence is interpreted in terms of temperature dependent thermal conductivity. The thermal resistance dependence on the active device temperature (${T}_{\text {Device}}$) indicates that the former one is mainly driven by the thermal conductivity of the oxide layer. Moreover, based on this dependence we reconstructed the channel temperature increase for each dissipated power and ambient temperature, and we found that the calculated values were in a good agreement with the experimental ones. Results indicate that even at low temperatures, thermal resistance does not depend significantly on the silicon channel thickness (ranging from 7 up to 24 nm), whereas the buried-oxide thinning (145 and 25 nm) strongly reduces the magnitude of the thermal resistance. Finally, this paper intends to fill the gap of experimental data concerning self-heating in advanced FDSOI transistors at low temperatures, revealing limitations and perspectives that should be taken into account for future work. [ABSTRACT FROM AUTHOR]

To continue with the scaling of high-performance transistors, alternate materials and device architectures are being explored as replacements for contemporary strained-silicon (s-Si) FinFETs. While III–V materials, such as In0.53Ga0.47As, offer higher electron mobilities and injection velocities than s-Si, emerging 2-D materials and nanowire (NW) device architectures promise better immunity to short-channel effects. In this paper, we present a detailed device-level performance comparison of s-Si, In0.53Ga0.47As, monolayer black phosphorus (BP), and WS2-based planar and multigate (Fin and NW) n-MOSFETs across three successive future technology nodes. The analysis incorporates both intrinsic device characteristics obtained from an advanced quantum mechanical simulation tool and the effect of nonidealities using a physics-based analytical model. The results indicate that 2-D materials, such as monolayer BP, offers higher ON currents than s-Si and In0.53Ga0.47As for planar device architectures. However, compared to modern s-Si and In0.53Ga0.47As Fin and NW FETs, monolayer BP and WS2 double-gate MOSFETs are reported to offer lower ON currents due to the smaller footprint at scaled technology nodes. [ABSTRACT FROM AUTHOR]

More and more attention has been paid to the heterogeneous semiconductor device based on the wafer-bonding method due to its high-quality wafer-bonded active layer. In this paper, we first theoretically study the dependence of the single-photon properties, including the single-photon detection efficiency (SPDE), dark count rate (DCR), and afterpulsing probability (AP), of the wafer-bonded Ge/Si single-photon avalanche photodiode (SPAD) on the interface state at the Ge/Si (hydrophilic reaction) and Si-Si (hydrophobic reaction or surface-activated method) wafer-bonded interface based on the Poisson statistics. It is found that the interface state density and the energy level position of the interface state significantly affect the linear-mode electric field distribution (avalanche probability), 3-dB bandwidth (dark carriers), gain (quantum efficiency), and effective transit time (trapped carriers), which in turn affect the DCR and the SPDE. Furthermore, the dependence of the AP on the avalanche charge and the interface recombination rate is clarified as well. It is expected that this paper may give guidance for the fabrication of high-performance SPAD. [ABSTRACT FROM PUBLISHER]

As dimension of bulk Si field-effect transistors scales down, novel techniques for impurity profile design at channel area are required because suppression of short-channel effects and improvement of on-state current is tradeoff in conventional ion implantation process. In this paper, we demonstrate p-type bulk Si fin field-effect transistors by using solid-source doping for better impurity profile in fin to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current. In this paper, impurity profiles in fin with two different kinds of anneal conditions after fin revelation (1000 °C 30 s and 1050 °C spike) are analyzed, and the better impurity profile at channel area is designed by 1000 °C 30-s anneal for better electrical characteristics. The anneal condition with the better impurity profile in fin showsmobility improvement at long gate length ( 1~\mu \textm ) and short gate lengths (60, 70, and 80 nm); subthreshold slope and transconductance are improved at the same time. With those results, we conclude that a fabrication process flow of p-type bulk Si fin field-effect transistors to weaken the tradeoff between suppression of short-channel effects and improvement of on-state current is established with 1000 °C 30-s anneal after fin revelation by using solid-source doping. At the same time, electrical characteristics variation is also suppressed in the case of 1000 °C 30-s anneal. [ABSTRACT FROM AUTHOR]

The susceptibility of conventional silicon p-channel MOS transistors to negative bias temperature instabilities (NBTIs) is a serious threat to further device scaling. One possible solution to this problem is the use of a SiGe quantum-well channel. The introduction of a SiGe layer, which is separated from the insulator by a thin Si cap layer, not only results in high mobilities but also superior reliability with respect to NBTI. In part one of this paper, we provide experimental evidence for reduced NBTI by thoroughly studying single traps in nanoscale devices. In this paper, we present detailed TCAD simulations and employ the four-state nonradiative multiphonon model to determine the energetical and spatial positions of the identified single traps. The found trap levels agree with the defect bands estimated in large-area devices. Our conclusions are also supported by the observation of similar activation energies for defects present in transistors of various device geometries. From the calibrated TCAD simulations data, an impressive boost of the time-to-failure for the SiGe transistor can be predicted and explained. [ABSTRACT FROM AUTHOR]

A new concept of vertical gallium nitride (GaN) Schottky barrier diode based on nanowire (NW) structures and the principle of dielectric REduced SURface Field (RESURF) is proposed in this paper. High-threading dislocation density in GaN epitaxy grown on foreign substrates has hindered the development and commercialization of vertical GaN power devices. The proposed NW structure, previously explored for LEDs offers an opportunity to reduce defect density and fabricate low cost vertical GaN power devices on silicon (Si) substrates. In this paper, we investigate the static characteristics of high-voltage GaN NW Schottky diodes using 3-D TCAD device simulation. The NW architecture theoretically achieves blocking voltages upward of 700 V with very low specific on-resistance. Two different methods of device fabrication are discussed. Preliminary experimental results are reported on device samples fabricated using one of the proposed methods. The fabricated Schottky diodes exhibit a breakdown voltage of around 100 V and no signs of current collapse. Although more work is needed to further explore the nano-GaN concept, the preliminary results indicate that superior tradeoff between the breakdown voltage and specific on-resistance can be achieved, all on a vertical architecture and a foreign substrate. The proposed NW approach has the potential to deliver low cost reliable GaN power devices, circumventing the limitations of today’s high electron mobility transistors (HEMTs) technology and vertical GaN on GaN devices. [ABSTRACT FROM PUBLISHER]

Direct conversion crystalline silicon X-ray imagers are used for low-energy X-ray photon (4–20 keV) detection in scientific research applications such as protein crystallography. In this paper, we demonstrate a novel pixel architecture that integrates a crystalline silicon X-ray detector with a thin-film transistor amorphous silicon pixel readout circuit. We describe a simplified two-mask process to fabricate a complete imaging array and present preliminary results that show the fabricated pixel to be sensitive to 5.89-keV photons from a low activity Fe-55 gamma source. This paper presented can expedite the development of high spatial resolution, low cost, direct conversion imagers for X-ray diffraction and crystallography applications. [ABSTRACT FROM PUBLISHER]

In this paper, a 1-Transitor (1-T) capacitorless dynamic random access memory (DRAM) using bandgap-engineered silicon-germanium Bipolar ionization metal oxide semiconductor field effect transistor (I-MOS) is investigated through numerical simulations. We have demonstrated the application of the proposed Si0.6Ge0.4 Bipolar I-MOS for realization of a 1-T capacitorless DRAM. The proposed device can achieve hysteresis at significantly lower drain voltages ( V\mathrm{LD} =0.45 V to V\mathrm{LU} =1.15 V), in comparison to the inversion mode device ( V\mathrm{LD} = 8 V to V\mathrm{LU} =11 V). In addition, the proposed 1-T capacitorless DRAM exhibits a wider hysteresis window ( \Delta \textV ) of the order ~700 mV and a sensing margin ( \Delta \textI ) of ~5 orders in comparison to the inversion mode based 1-T capacitorless DRAM. Moreover, the proposed 1-T capacitorless DRAM exhibits the retention time of ~750 msec and ~320 msec for T = 25 °C and T = 85 °C, respectively. The proposed 1-T capacitorless DRAM also shows nondestructive read and an extreme long-term endurance. Therefore, the results presented in this paper can provide an opportunity for future DRAM design in deep nanometer technology. [ABSTRACT FROM PUBLISHER]

Superjunction has arguably been the most creative and important concept in the power device field since the introduction of the insulated gate bipolar transistor (IGBT) in the 1980s. It is the only concept known today that has challenged and ultimately proved wrong the well-known theoretical study on the limit of silicon in high-voltage devices. This paper deals with the history, device and process development, and the future prospects of Superjunction technologies. It covers fundamental physics, technological challenges as well as aspects of design and modeling of unipolar devices, such as CoolMOS. The superjunction concept is compared to other methods of enhancing the conductivity of power devices (from bipolar to employment of wide-bandgap materials) to derive its set of benefits and limitations. This paper closes with the application of the superjunction concept to other structures or materials, such as terminations, superjunction IGBTs, or silicon carbide Field Effect Transistors (FETs). [ABSTRACT FROM AUTHOR]

A novel optically activated cascode gallium nitride (GaN) high-electron-mobility transistor (HEMT) is introduced and evaluated in this paper. Furthermore, optical triggering of GaN HEMT structures by cost-effective and high-power long-wavelength light sources is proposed for the first time. In electrical domain, GaN HEMTs suffer from being normally on devices, making it more complicated to design and implement gate drivers for these devices. In optical domain, GaN devices suffer from being triggered by low-power short-wavelength light sources, making them significantly more expensive and practically unprofitable. Therefore, a new optical cascode (OC) GaN HEMT is proposed in this paper to solve the problems of both electrical and optical domains. The structure of this OC GaN HEMT includes a high-power normally on (depletion mode) GaN HEMT in combination with a low-power optical switch in cascode configuration. This OC not only realizes an overall normally off (enhancementmode) structure, but also offers activationwith cost-effective long-wavelength optical sources. It also offers a single-biased configurationwithout the need for complicated electrical gate drivers. Unlike conventional electrically activated cascode GaN HEMT structures, which may be prone to electromagnetic interference noise due to the high-frequency switching operation, the optical link in this proposed scheme is immune to external noise. The results showa high-frequency switching capability of 1MHz for theOCGaN HEMT under a bias voltage of 600 V and a current of 10 A. Less voltage and current ringing are observed in the OC compared with the electrical alternative due to the elimination of gate controlling inductance introduced in the electrical cascode configuration. [ABSTRACT FROM AUTHOR]

This paper examines the fundamental reliability differences between n-p-n and p-n-p SiGe HBTs. The device profile, hot carrier transport, and oxide interface differences between the two device types are explored in detail as they relate to device reliability. After careful analysis under identical electrical stress conditions for n-p-n and p-n-p, the differences in activation energies for the damage of the oxide interfaces of the two devices is determined to be the primary cause for accelerated degradation seen in p-n-p SiGe HBTs. An analytical model has been adapted for simulating these aging differences between p-n-p and n-p-n devices. This paper has significant implications for predicting the degradation of complementary SiGe HBTs and even engineering future generations with well-matched n-p-n and p-n-p device-level reliability. [ABSTRACT FROM PUBLISHER]

The base series resistance is an important parameter for bipolar junction transistors and heterojunction bipolar transistor (HBTs). Although many methods have been proposed for its experimental determination, their results vary significantly. In this paper, the most widely used methods are reviewed and applied to SiGe HBTs of different technologies and generations including different device types, i.e. high-speed and high-voltage SiGe HBTs. The accuracy of the methods is evaluated by applying them to a sophisticated physics-based compact model, allowing to clearly detect and explain the causes for the observed inaccuracies or failures. The methods are then also applied to experimental data. In both cases, a large variety of device sizes have been investigated. This paper and its results provide insight into each method’s accuracy, its application limits with respect to a technology, device size, and operating range as well as its requirements in terms of equipment and extraction effort. [ABSTRACT FROM PUBLISHER]

Silicon heterojunction solar cells having semiconducting oxide-selective contacts can revolutionize the photovoltaic industry with the promise of low cost and high efficiency. In this paper, we have identified the potential design issues of silicon heterojunction cell using simulation. This paper compares two possible electron-selective oxides (TiO2 and ZnO) and two possible hole-selective oxides (CuAlO2 and NiO). The Fermi level in the oxide at the oxide/metal interface is pinned by the metal (its workfunction and eventual interface dipoles). We considered this effect, which determines the effective workfunction of the metal contact as opposed to the actual metal workfunction. Our simulation suggests that Fermi level pinning has significant impact on the device performance. We also considered different interface passivation effects and oxide dopings in our simulation. The simulation suggests that high doping in oxides is beneficial to counter balance the effect of poor surface passivation. This paper provides an extensive understanding of the design of Si heterojunction solar cell using band-engineered semiconducting oxide as the selective contact replacing highly doped emitter and back surface field. [ABSTRACT FROM PUBLISHER]

Tunnel FETs (TFETs) have been identified as the most promising steep slope devices for ultralow power logic circuits. In this paper, we demonstrate in-plane InAs/Si TFETs monolithically integrated on Si, using our recently developed template-assisted selective epitaxy approach. These devices represent some of the most scaled TFETs with dimensions of less than 30 nm, combined with excellent aggregate performance with average subthreshold swing (SS), of around 70 mV/decade combined with I\mathrm{\scriptscriptstyle ON} of a few \mu \textA / \mu \textm for |V\mathrm {\mathbf {DS}}| = |V\mathrm {\mathbf {GS}}| = 0.5 V. Here, we will discuss the device fabrication as well as the experimental electrical data. Extensive low temperature characterization and activation energy analysis is used to gain insights into the factors limiting device performance. Combined with the simulation study presented in part 2 of this paper, this will elucidate how traps are ultimately limiting the SS. [ABSTRACT FROM AUTHOR]

In this paper, we present extensive characterization of low-frequency noise in advanced silicon germanium heterojunction bipolar transistors. We demonstrate the extraction methodology of base and collector noise spectral densities for a wide range of transistor geometries. In addition to 1/ $f$ noise, generation–recombination (G–R) mechanisms are observed at low bias in the base current noise. Their existence is confirmed by Random Telegraph Signal (RTS) noise measurements. 1/ $f$ and G–R components are extracted from the base current noise spectra and their bias dependencies are studied. Finally, base current noise spectral densities measured at the same base current density in different geometries are compared to study the individual contribution of 1/ $f$ noise from the periphery as well as the intrinsic device. Part II of this paper will discuss the modeling aspects and noise correlation. [ABSTRACT FROM AUTHOR]

Thin-body self-aligned InGaAs MOSFETs are fabricated on a III-V-On-Insulator structure on a silicon active substrate (III-V-OIAS). The p-type Si active substrate acts as a back gate that can modulate the threshold voltage and other electrical characteristics of the device. This paper explores the physics behind this effect through 2-D simulations and comparison with experiments. In the off-state, we find that the application of a positive body-to-source ( V\mathrm{ bs} ) voltage increases the subthreshold swing but reduces drain-induced barrier lowering. The first effect is related to the electron profile and the location of the centroid of electron charge in the channel while the second is closely associated with the modulation of a depletion region in the silicon substrate. In the on-state, the series resistance is observed to improve under positive V\mathrm{ bs} due to the increased accumulation of electrons in the extrinsic portion of the device. In addition, the channel mobility exhibits a two-branch behavior in its dependence on the average vertical electric field in the channel. This is explained by the different interfacial scattering that takes place at the front and back channel surfaces. This paper highlights the tradeoffs involved in attempting to exploit the body bias in the operation of QW-MOSFETs in III-V-On-Insulator with active substrate. [ABSTRACT FROM PUBLISHER]

In this paper, we present a lateral injection enhanced insulated gate bipolar transistor (LIEGT) and investigate its mechanism. The LIEGT features a recessed trench at the cathode side of the drift region formed by LOCal oxidation of silicon (LOCOS) process. The recessed trench suppresses holes being extracted and enhances the electron injection, thus contributing to a very low loss in the ON-state. The ON-state voltage (${V}_{ \mathrm{\scriptscriptstyle ON}}$) of the LIEGT is reduced by 24% at the current density of 200 A/cm2 and the saturation current is 40% higher than that of the conventional lateral insulated gate bipolar transistor (LIGBT). The LIEGT exhibits an improved tradeoff between ${V}_{ \mathrm{\scriptscriptstyle ON}}$ and turnoff loss (${E}_{ \mathrm{\scriptscriptstyle OFF}}$). For the same ${V}_{ \mathrm{\scriptscriptstyle ON}}$ , the ${E}_{ \mathrm{\scriptscriptstyle OFF}}$ is decreased by 38% compared with that of the conventional LIGBT. [ABSTRACT FROM AUTHOR]

In this paper, the requirements of device cross section and aspect ratio (AR) are examined to facilitate steep switching in heavily doped 3-D multiple gate junctionless (JL) transistors. It is shown through well-calibrated simulations and physical insights that the sharp OFF-to- ON switching action is predominantly governed by the area of cross section (${A} _{\textsf {cross}}$) instead of the gate length. A 3-D JL architecture preferably oriented toward a planar topology, i.e., with wider fin and low AR, is conducive for steep switching as a greater bulk area is available for impact ionization. On the contrary, narrow vertical architectures with AR > 1 suppress ${A} _{\textsf {cross}}$ in the bulk and are less likely to support the steep current transition. Steep switching specific scaling methodology is showcased to attain a sharp increase in drain current with a sub-60 mV/decade swing in a tri-gate JL transistor along with an associated negative value of total gate capacitance. [ABSTRACT FROM AUTHOR]

Thin-film transistors (TFTs) fabricated using solution-processed zinc–tin-oxide (ZTO) semiconductor thin films as the channel layers are proposed in this paper. Effect of the ZTO annealing temperature on the TFT performance is studied. Significant reduction of oxygen-vacancy and chlorine residue contents in the ZTO semiconductor can be obtained when the annealing temperatures are 500 °C–700 °C. The ZTO semiconductor with the annealing process at 600 °C in air can give an optimal ZTO TFT having a low leakage current of 10−12 A and a high ${I}_{ \mathrm{\scriptscriptstyle ON}}/{I}_{ \mathrm{\scriptscriptstyle OFF}}$ ratio of 3 $\times \,\,10^{7}$. The subthreshold swing is 0.39 V/decade corresponding to an interface trap density of $1.2\times \,\,10^{12}\,\,$ cm−2eV−1. [ABSTRACT FROM AUTHOR]

In this paper, a new architecture based on an intentional misalignment between the core and shell gate is presented for the nanotube tunnel field-effect transistor (NT-TFET). The misaligned core gate overlaps with the source region and facilitates line tunneling in the core-gate–source overlapped region significantly increasing the band-to-band tunneling (BTBT) rate. Using the calibrated 3-D simulations, we show that the proposed misaligned (MG) NT-TFET outperforms the conventional NT-TFET both in terms of static as well as dynamic performance. The MGNT-TFET exhibits an increased ON-state current by nearly 11 times as compared to the conventional NT-TFET with an ultrasteep subthreshold slope (minimum point subthreshold swing of ~5 mV/dec and an average subthreshold slope of 15.5 mV/dec). The higher effective drive current also leads to an improved dynamic performance in the MGNT-TFET [ABSTRACT FROM AUTHOR]

In this paper, we propose a novel technique to overcome the conductance limitation in metal contacted single-walled carbon nanotubes (SWNTs)-based devices using metal nanoparticles (MNPs). Schottky barrier (SB) height at metal-SWNTs contact is believed to be the major contributor for this conductance limitation. Metal contacts with SWNTs are fabricated on a thermally grown SiO2/Si substrate using a conventional lithography process. The SWNTs are aligned between the metal electrodes using dielectrophoresis method. MNPs are introduced in the device using a small drop of MNP suspension to decorate the SWNTs. It is observed that the introduction of MNPs in the device reduces the SB height significantly. We found 0.34 eV reduction in SB height with silver (Ag) nanoparticles (NPs) and 0.15 eV with gold (Au) NPs. The proposed technique has improved the conductance in decorated SWNTs four times for Ag and Au NPs as compared to the bare SWNTs. Improvement in the conductance behavior of the SWNTs using MNPs enhances the sensitivity and switching speed of the devices, therefore, make it a promising alternative to silicon-based devices. [ABSTRACT FROM AUTHOR]