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Two $K_{u}$ - to V-band distributed amplifiers (DAs) based on nMOS and nMOS/pMOS gain stages and a distributed transceiver front end (DTFE) are presented for ultra-wideband power and low-noise amplification in a 45-nm RF CMOS silicon-on-insulator (SOI) technology. Supply scaling of gain stages through high-pass filter sections achieves high efficiency while maintaining a broadband 50- $\Omega $ match. The nMOS DA has a gain of 13 dB over a 3-dB bandwidth of 10–82 GHz and a minimum noise figure (NF) of 5.3 dB. The measured peak output power is 17.2 dBm with a peak power-added efficiency (PAE) of 17.4% at 50 GHz. The hybrid DA allows higher operating voltage and distortion cancelation of scaled pMOS devices to an achieve output power of 17.5 dBm with PAE of 20.2% and low third-order intermodulation and amplitude–phase nonlinearities. The DTFE utilizes time-domain duplexing to drive a shared antenna port for transmit (TX) and receive (RX) modes. It achieves TX gain of 11.7 dB from 12–76 GHz with peak output power of 17 dBm and PAE of 14.2%. RX gain is 9 dB from 11–77 GHz with a minimum NF of 6.2 dB. The 5-GHz wideband 16-QAM is demonstrated in the amplifier circuits for data rates exceeding 20 Gb/s. [ABSTRACT FROM AUTHOR]

This paper presents an explicit analysis of the bandwidth and port imbalance of a subquarter-wavelength transmission-line (t-line) transformer and verifies this with the design of a two-stage D-band power amplifier (PA). Series power combining techniques incorporate both stacked heterojunction bipolar transistors (HBTs) and power combining using an 8-way sub-quarter-wavelength t-line transformer above 100 GHz. The extremely compact power combining methodology leads to a small die area of 0.62 mm2 and a record 254-mW/mm2 output power per unit die area. The PA has been fabricated in a 90-nm silicon germanium BiCMOS technology and produces more than 21-dBm output power over the frequency range of 114–130 GHz with a peak output power of $160~{\mathrm{mW}}\approx 22~{\mathrm{ dBm}}$ at 120 GHz and a 3-dB small-signal bandwidth of 35 GHz. This output power is 32% higher than the highest prior art, while the chip area is 77% smaller. [ABSTRACT FROM AUTHOR]

This paper presents a reconfigurable dual Q- and W-band bidirectional amplifier and a V-band active circulator in a 45-nm CMOS silicon-on-insulator (SOI) technology. The circuits rely on reconfigurable feedback networks to manipulate the traveling wave along a transmission line. The dual Q- and W-band bidirectional amplifier operates at 40 and 81 GHz, with peak gain of more than 4.2 dB in all modes of operation. The V-band active circulator is reconfigurable to operate in four different modes of operation: clockwise, counter-clockwise, quasi-circulation, and as a thru between port 1 and port 2. The circulator is measured to have an insertion loss of 7.4 dB with isolation between any pair of isolated ports better than 18 dB from 62-75 GHz. The circuit technique proposed here can easily be adapted to operate at different millimeter-wave frequency bands. [ABSTRACT FROM AUTHOR]

This paper presents an analog circuit scheme to steer phased-array receivers in the direction of an incoming signal. The proposed circuit technique utilizes a coupled-oscillator array along with a coupled-phased-locked loop to auto-align an N-element receive array towards the direction of the incident RF signal. A four-element receiver array is implemented in 45-nm CMOS SOI process and achieves auto-steering range of \pm 35^\circ from broadside. A three-element version of the array demonstrates higher auto-steering angle covering \pm 70^\circ range. The receiver also performs signal demodulation for the incident modulated RF signal, allowing high-data rate communication. A 60-Mbps 64-QAM modulated RF signal is demodulated with error-vector-magnitude (EVM) less than 4% across the steering angle range. The chip area is 3.45 mm^2 including a pad frame with 30-mW/element power consumption. To the best of authors' knowledge, this is the first demonstration of an analog self-steering array in an integrated circuit. [ABSTRACT FROM AUTHOR]

This paper presents passive integrated circuits for millimeter-wave transmitters and receivers implemented in a 45-nm CMOS silicon-on-insulator (SOI) process. The advantages of SOI over bulk CMOS are discussed for millimeter-wave passive circuits. First, a single pole double throw (SPDT) switch demonstrates a measured insertion loss of less than 1.7 dB at 45 GHz and third-order intermodulation intercept point (IIP3) of 18.2 dBm. Second, a double-balanced passive in-phase/quadrature (I/Q) mixer exhibits a conversion loss of 8.35 dB at 44 GHz and IIP3 of 15.5 dBm. At a fixed IF of 200 MHz, the minimum I/Q gain and phase imbalance is 0.25 dB and 1.9^\circ. The passive mixer and SPDT switch results demonstrate a record minimum insertion loss and linearity performance for the passive millimeter-wave circuits. [ABSTRACT FROM AUTHOR]

Jitter limitations pose significant challenges for high-resolution and sampling-rate analog-to-digital converters (ADCs). This paper describes an integrate-and-sample (IAS) receiver suitable for use in an optical parametric photonic ADC. Rate-scalable photonic-sampling techniques provide low-jitter optical sampling and analog-to-digital conversion of the wideband signal up to 10 GHz and beyond. An 8-bit 2-GS/s IAS receive channel is described for a rate-scalable photonic ADC. Electronic measurements are shown for an RF tone and a photonic Gaussian pulse source and compared to simulations. A two-channel IAS array is fabricated in a 120-nm SiGe BiCMOS process and packaged onto a printed circuit board for integration into the photonic-sampling setup. A single 2-GS/s channel achieves a measured performance higher than 8.1 ENOB. The two-channel integrated circuit consumes 890 mA per channel from 5- and 2.5-V supplies and occupies an area of \ 1.6\times \ 2.0~\ mm^2. [ABSTRACT FROM AUTHOR]

A power amplifier (PA) topology is presented that incorporates a feedback network around the transistor to satisfy matching requirements. Circuit parameters can be tuned for small- and large-signal circuit operation. The PA is fabricated in a 120-nm SiGe BiCMOS process and performs from 36 to 41 GHz. The PA achieves a saturated output power of 23 dBm and a peak power-added efficiency of 20% at 38 GHz. This is the highest reported output power from a single PA at Q-band in silicon. [ABSTRACT FROM PUBLISHER]

Analytical techniques to determine the linearity and spur-free dynamic range (SFDR) for phased array receivers are presented. The proposed method eliminates the need for circuit-level simulation of intermodulation distortion in an N-element receiver by characterizing the array SFDR from the SFDR for a single receive channel. The analysis separates the relative impact of array factor, circuit architecture and channel linearity to assess the spatial sensitivity of the receiver to jamming signals. The proposed techniques are applied to a comparison of RF phase-shifting and LO phase-shifting receivers. RF phase-shifting architectures are shown to offer more uniform jammer rejection over the beam-scanning range given the same receiver linearity constraints. [ABSTRACT FROM AUTHOR]

A dual-channel CMOS distributed amplifier (DA) is proposed for a highly linear receiver front-end. Proper choice for the number of stages and cutoff frequency of the distributed circuit realizes isolation between amplifier channels. Analysis of the distributed circuit describes the role of reverse gain in minimum noise figure (NF) and intermodulation distortion. The chip is fabricated in a \0.13-\mu\ m CMOS process, occupies an area of \ 0.60 mm^2, and consumes 18 mW from a 1.2-V supply. Measurements of the DA show an NF of 5.7 dB, an output P1~{dB} of 4.9 dBm, and a forward gain of 9.6 dB at 24 GHz. [ABSTRACT FROM AUTHOR]

A millimeter-wave rotary-wave oscillator (RWO) is presented that hybridizes standing- and traveling-wave behavior. This paper presents an analysis of the phase noise of this RWO. The multiphase voltage-controlled RWO is implemented in a 0.12-\mu\ m SiGe BiCMOS process using only nMOS devices for the oscillator core. The measured frequency of operation is 45 GHz with 6.5% tuning range and has a phase noise of -\91 dBc/Hz at 1 MHz and -\112 dBc/Hz at 10 MHz. The power consumption of the oscillator core is 13.8 mW from a supply voltage of 1.2 V. [ABSTRACT FROM AUTHOR]

A high-frequency amplifier technique is introduced based on traveling-wave amplification. As opposed to distributing amplifiers to support traveling waves, the proposed technique amplifies forward traveling waves while attenuating backward traveling waves through a cascade of stages that share a single transmission line. The behavior of the cascaded constructive wave amplifier is analyzed in terms of gain, bandwidth, stability, and noise figure. The amplifier is demonstrated in a 0.12-μ m SiGe BiCMOS process with 12 cascaded amplification stages and achieves more than 26 dB of gain at 99 GHz with a 3-dB bandwidth of 13 GHz. The input and output return loss is better than 15 and 12 dB, respectively. The noise figure of the amplifier is 10.8 dB at 85 GHz. The output-referred P1 dB is -0.1 dBm and the amplifier consumes 113 mW, including current biasing. [ABSTRACT FROM AUTHOR]

High-speed digital signal integrity at data rates above 6 Gb/s is an obstacle to reliable serial link operation. Two signal integrity challenges include dispersion due to frequency-dependent losses and reflections created at impedance mismatches. Signal integrity analysis relies on time-domain simulation of pseudo-random data patterns. This paper explores a predictive method for interconnect eye closure caused by reflections at the transmitter and receiver and does not require extensive time domain simulation. Worst-case bounds on intersymbol interference and data-dependent jitter aid prediction for link budgets under channel variations. This method is applied to the design of a passive equalizer. [ABSTRACT FROM AUTHOR]

This paper describes the design of an integrated coupled-oscillator array in SiGe for millimeter-wave applications. The design focuses on a scalable radio architecture where multiple dies are tiled to form larger arrays. A 2 × 2 oscillator array for a 60-GHz transmitter is fabricated with integrated power amplifiers and on-chip antennas. To lock between multiple dies, an injection-locking scheme appropriate for wire-bond interconnects is described. The 2 × 2 array demonstrates a 200 -MHz locking range and 1 × 4 array formed by two adjacent chips has a 60-MHz locking range. The phase noise of the coupled oscillators is below -100 dBc/Hz at a 1-MHz offset when locked to an external reference. To the best of the authors' knowledge, this is the highest frequency demonstration of coupled oscillators fabricated in a conventional silicon integrated-circuit process. [ABSTRACT FROM AUTHOR]

We present a method for predicting data-dependent jitter (DDJ) introduced by a general linear time-invariant LTI system based on the system`s unit step response. We express the exact DDJ of a first-order system and verify the validity of the solution experimentally. We then propose a perturbation technique to generalize the analytical expression for DDJ. We highlight the significance of the unit step response in characterizing DDJ and emphasize that bandwidth is not a complete measure for predicting DDJ. We separate the individual jitter contributions of prior bits and use the result to predict the DDJ of a general LTI system. In particular, we identify a dominant prior bit that signifies the well-known distribution of deterministic jitter, the two impulse functions. We also show a jitter minimization property of high-order LTI systems. We verify our generalized analytical expression of DDJ for several real systems including an integrated CMOS 10-Gb/s trans-impedance amplifier by comparing the theory and measurement results. The theory predicts the jitter with as low as only 7.5% error. [ABSTRACT FROM AUTHOR]

Introduces coupled phase-locked hoops as novel circuits for phased-array antennas. Factors that determine the successful implementation of the technique; Theoretical limits of the hoops.

A 70-GHz two-element bidirectional frontend is demonstrated with linear coupled oscillators in a 90-nm silicon–germanium BiCMOS process. The transmitter has a measured peak output power of 7.2 dBm and a peak conversion gain of 14.5 dB while consuming 47 mA from a 1.8-V supply. The receiver has a peak conversion gain of 9.9 dB and a minimum noise figure of 8.6 dB with a nominal current consumption of 18 mA from a 1.5-V supply. The frontend is integrated with a two-element linear coupled oscillator array and achieves a maximum phase scanning of ±80°. [ABSTRACT FROM PUBLISHER]

An $E$ -band (71–86-GHz) bidirectional transceiver is presented in this paper. The time-division duplex architecture avoids transmit (TX)/receive (RX) switches through the use of transistor biasing in the signal path to minimize high-frequency loss. The low-noise amplifier (LNA) and power amplifier (PA) are combined into a wideband PA/LNA circuit, which alleviates the parasitic loading of each circuit through a wideband power combiner. The bidirectional transceiver circuit is implemented in 90-nm SiGe BiCMOS process. In TX mode, the bidirectional transceiver transmits a maximum saturated power of 11 dBm at 78 GHz with a 3-dB bandwidth from 71 to 86 GHz. In RX mode, the maximum 30.6-dB conversion gain and the minimum 6.6-dB noise figure are measured at 73 GHz. The whole RF frontend chip consumes 350.2- and 137.7-mW dc power in TX and RX modes, respectively, including all the RF, IF, and local oscillator amplifiers. The overall chip size is 1.5~\text {mm}\times 0.9 mm including pads. [ABSTRACT FROM AUTHOR]

This paper presents a dual-mode intermediate frequency (IF) signal processing circuit for pulse compression radar (PCR) and symbol recovery. A half-duplex architecture is proposed to support modulation and demodulation of PCR signals. For data communication, the modulator and the demodulator support up to 3-Gb/s QPSK signal. For range sensing, the proposed IF correlation technique supports 1.5-GHz bandwidth (BW) and 3/5/7-b Barker codes for 10-cm range resolution. The circuit includes a high-linearity switch, a modulator, a reconfigurable demodulator/correlator, and an in-phase and quadrature clock signal generator. This proposed system is fabricated with 90-nm CMOS, and each channel can be configured to operate from 200 Mb/s to 1.5 Gb/s with different Barker codes. The maximum power consumption is 54 mW with 1.5-GHz BW (10 cm) in range sensing mode and 49 mW at a rate of 3 Gb/s in data communication mode. [ABSTRACT FROM PUBLISHER]

A channel-selecting low-noise amplifier (CS-LNA) with blocker filtering is presented for a SAW-less diversity path receiver (RX) in frequency-division duplexing cellular systems. A hybrid N-path bandpass filter/band-reject filter (BPF/BRF) feedback network is applied to the LNA to create close-in reject bands around the passband to suppress transmit leakage and improve the out-of-band (OOB) input-referred third-order intercept point (IIP3). Control of the frequency and depth of the reject bands is demonstrated with analysis and simulation. A gm2{\mathchar"702D}gm3 cancellation linearization is applied to improve the in-band (IB) linearity. Adaptive LO swing and silicon-on-insulator (SOI) thick-oxide devices are demonstrated to improve the power-handling capability. The proposed CS-LNA is implemented in 32-nm CMOS SOI and operates from 0.4 to 6 GHz with the maximum rejection larger than 60 dB and power-handling capability up to 17 dBm. The prototype demonstrates an OOB IIP3 of 36 dBm and IB IIP3 of 10 dBm at 1 GHz. To the authors’ knowledge, this is the highest blocker rejection, power-handling capability, linearity, and the widest tuning range for an LNA with tunable filtering. [ABSTRACT FROM PUBLISHER]

Quadrature oscillators (QOs) based on parallel or series coupling mechanisms produce ambiguous phase relationships between the coupled oscillators. Deterministic mode selection is presented and analyzed for a series-coupled LC quadrature oscillator (LC-QO) and leveraged to increase the tuning range of the QO. Series-coupled LC-QOs have been implemented in a 90-nm CMOS technology. Measured results show a frequency tuning range of 94% for a center frequency of 1.3 GHz, 60% for the oscillator operating at 3.7 GHz, and 52% for the oscillator operating at 4.4 GHz. [ABSTRACT FROM PUBLISHER]

A tunable N-path filter with more than one decade tuning range is demonstrated to address transmit (TX) leakage in a surface-acoustic-wave-less diversity path receiver for frequency-division duplexing cellular systems. The proposed filter simultaneously creates a reject band and passband anywhere from 0.2 to 3.6 GHz to suppress TX leakage while minimizing insertion loss of the receive signal and is implemented in 45-nm CMOS silicon-on-insulator. Measurements show the 3-dB bandwidth of the passband is greater than 80 MHz with an independently tunable reject band, providing the ultimate rejection is from 33 to 41 dB while the passband insertion loss is between 2.6 dB and 4.3 dB over the tuning range. The proposed filter offers 29-dBm out-of-band (OOB) third-order input-intercept power (IIP3) and 22-dBm in-band (IB) IIP3 with a 10-dBm blocker 1-dB compression point (B1dB). To the authors’ knowledge, this is the highest B1dB, IB IIP3, and OOB IIP3 for a CMOS tunable filter. [ABSTRACT FROM PUBLISHER]

The analysis and implementation of a dual-band direct-conversion millimeter-wave transmitter is presented. The proposed dual-band modulator uses high-impedance loads at two frequencies for the local oscillator driving amplifiers and power amplifier (PA) pre-amplifiers. To correct the amplitude and phase imbalance of the in-phase and quadrature channels at Q- and W-bands, the paper suggests a digitally controlled quadrature error correction stage to finely calibrate these errors and lower the error vector magnitude (EVM) without increasing the baseband digital-to-analog converter resolution. The transmitter is fabricated in 0.12- μm silicon-germanium BiCMOS process and occupies an area of 5.5 mm2. At 45-GHz carrier frequency, error correction improves the sideband suppression ratio (SSR) by 10 dB at 2.4-MHz IF frequency. The EVM is lowered from 3.21% to 2.38% for a 64-QAM constellation at a 2.4-Ms/s symbol rate. At 94-GHz carrier frequency, the SSR is improved from 24 to 41 dBc at 2.4-MHz IF frequency, and the EVM is lowered by more than 1% for a 16-QAM constellation at 3-Ms/s symbol rate. A dual-band PA breakout measurement indicates the peak power-added efficiency of 15% with 14-dBm maximum saturated power (Psat) at 43 GHz and 9-dBm Psat at 82 GHz is achieved. [ABSTRACT FROM AUTHOR]

This paper presents a pulse-compression radar baseband analog signal processing integrated in a silicon process for low cost and power dissipation. The analog signal-processing circuitry exhibits the autocorrelation properties of the polyphase codes, maximizes the sensitivity and resolution of a pulse radar system, and alleviates speed and resolution requirements of the analog-to-digital converter (ADC) via an analog correlator. The circuitry includes a two-stage variable gain amplifier (VGA) for high dynamic range, a correlator/integrator circuit, a comparator, and offset calibration circuits. The differential 6-bit VGA is designed to adaptively track the Friis path loss through rapid change of the VGA gain and offset calibration, relaxing the dynamic range requirements of the correlator. The measured performance shows a VGA gain variation of 52 dB and a VGA group-delay imbalance of 50 ps over 64 states. The high-speed pulse compression/correlation is performed in analog current domain and the speed requirement on the ADC is reduced by a factor equal to the duty cycle lowering the ADC power consumption. The chip is fabricated in a 90-nm process, wire bonded on the FR4 printed circuit board, and tested with a Stratix IV field-programmable gate-array board to evaluate the system performance for different radar polyphase codes. [ABSTRACT FROM AUTHOR]

This article reports signal processing and circuit techniques for direct RF signal modulation. A pulse-encoded transition (PET) technique is introduced to reduce undesired harmonic distortion (HD) and adjacent channel leakage ratio (ACLR) generated by the direct RF modulation. To enable PET RF switching, two variations of a high-power, stacked-FET switch modulator, an 8- and 12-device stack, are designed in 45-nm silicon on insulator (SOI) CMOS. The switch design uses a tapering design to significantly improve power handling with minimal impact to switching speed. The modulators have $P_{1\,{\mathrm{ dB}}} $ values between 34 and 39 dBm while demonstrating a modulation bandwidth of nearly 500 MHz with a 1-GHz carrier. The input referred third order intercept point (IIP3) is between 46 and 61 dBm. Additionally, ACLR measurements of up to −50 dBc are demonstrated using the proposed PET technique at 30-dBm output power. To the best of our knowledge, this is record power handling and ACLR for a CMOS switch. [ABSTRACT FROM AUTHOR]

The dynamic range of a radio-over-fiber (RoF) link is fundamentally limited by the linearity of electro-optic modulators. Silicon photonic (SiP) processes offer significant potential for integration, but the plasma dispersion effect impacts the realizable spur-free dynamic range (SFDR). This article analyzes the underlying source of nonlinearity in SiP Mach–Zehnder modulator (MZM) and demonstrates fundamental limitations on intermodulation distortion. A SiGe low-noise distributed driver is co-designed for the SiP MZM to linearize and extend the bandwidth over which the SFDR remains high. The RoF transmitter achieves 1–20 GHz bandwidth and an SFDR of 109 dB $\cdot $ Hz2/3 at 11 GHz. To the best of our knowledge, this is the highest SFDR demonstrated for a SiP technology without incorporating predistortion. [ABSTRACT FROM AUTHOR]

This paper demonstrates generalized code-selective filters for code-pass and code-reject signal processing at RF. A code-reject scheme using a quarter-wave ($\lambda /4$) impedance transformation is also demonstrated to overcome tradeoffs of insertion loss (IL) and linearity compared to series band-reject $N$ -path filters. A 45-nm CMOS SOI implementation consumes a power of 9.32 mW from 1 to 1.8-V supplies at the frequency of 0.35–1.1 GHz and the chip area is 1.73 mm2. The measured transmit rejection is up to 22.6 dB with 4-dB IL. The in-band third-order-intercept point (IIP3) is up to 22.6 dBm and noise figure (NF) of 4–6 dB depending on the applied codes. [ABSTRACT FROM AUTHOR]

CMOS RF switches support watt-level RF output power while enabling signal processing with high speed. Typically, RF FET switches offer a tradeoff between a power handling and modulation bandwidth. This paper investigates the cause of compression in a FET switch, and the analysis suggests the optimization of the gate driving impedance for a stacked-FET switch. A design methodology is presented to realize watt-level power handling with high fractional bandwidth (FBW). The measurements demonstrate a BPSK modulator that can handle up to 10 W with wide FBW. The high-power, low-insertion loss, and high-modulation bandwidth demonstrate record performance. [ABSTRACT FROM AUTHOR]

This paper presents the first phased array transceiver operating from 71 to 86 GHz using injection-locked oscillators (ILOs) for phase shifting. A folded-cascode ILO is proposed to extend the locking range of an array of oscillators. Frequency multiplication covers a 10-GHz tuning range with 23-dB power gain. Each ILO path covers more than ±300° and exhibits low amplitude variation with respect to phase shift range (<1 dB) and excellent isolation and amplitude error (<0.5 dB) between array elements. A wideband, bidirectional RF front end delivers 10-dBm maximum output power with more than 20-dB conversion gain over the 3-dB bandwidth in the transmit (TX) mode and a minimum 9.5-dB noise figure with more than 20-dB conversion gain in the receive (RX) mode. Low phase noise is demonstrated in the ILO approach over the phase tuning range with −112 dBc/Hz at 1-MHz offset and phase noise variation for different phase shift states under 2.5 dB, corresponding to less than 2° phase error. Array patterns demonstrate the wide scan range, and dynamic measurements show that the transmitter supports up to 6-Gb/s data rate with 256 QAM. The chip has $3.4\times2.1$ mm2 area implementing in the 90-nm BiCMOS technology and consuming 386.4 mW in the TX mode and 286 mW in the RX mode per element. [ABSTRACT FROM AUTHOR]

A 10-GHz outphasing modulator is implemented in a 45-nm CMOS silicon-on-insulator process. The modulator is designed to provide high linearity and can operate at high data rates by using 256-QAM while maintaining low error vector magnitude (EVM). Four high-speed 10-bit digital-to-analog converters (DACs) are integrated with dual in-phase and quadrature upconverters. To deliver high output power to an off-chip power amplifier, stacked field-effect transistor current buffers are used to isolate the modulator from the load and mitigate device breakdown. As a result, this modulator delivers 23 dBm to a differential 100-\Omega load. The high-resolution DACs provide a fine control of the phase between the outphased signals and support more than 60 dB of dynamic range and power steps smaller than 1 dB over the entire output power range. The outphasing modulator demonstrates an EVM of 2.2% at 80 Mbit/s and an EVM of 3.4% at 1.1 Gbit/s for 256-QAM. To our knowledge, this is the first demonstration of an outphasing modulator operating above 1 Gb/s. [ABSTRACT FROM PUBLISHER]

This paper reports the generation, amplification, and radiation of modulated signals at 45 GHz using a single-chip CMOS power amplifier coupled to a 2\, \times \,2 antenna array. Using digital predistortion, complex constellations were demonstrated for wide modulation bandwidth, which allows high data rates to be transmitted in a spectrally efficient manner. After predistortion, a 98-MS/s 1024-QAM signal with peak-to-average power ratio of 7 dB was demodulated with an error vector magnitude of 1.3%. The measured equivalent isotropically radiated power was 26.2 dBm. The corresponding average RF power produced by the CMOS chip, considering a simulated antenna gain of 12 dB, was 14.2 dBm. [ABSTRACT FROM PUBLISHER]

This paper reports 45-GHz power amplifier (PA) arrays implemented in 45-nm CMOS silicon-on-insulator, coupled to antenna arrays to enable free-space power combining. A single CMOS chip (2.5\,\times\,4.5 \mm^2) containing eight-unit PAs was developed and its output was fed to a 2\,\times\,2 array of differentially fed patch antennas on a printed circuit board. This array provided an equivalent isotropic radiated power (EIRP) of 40 dBm at 45 GHz with 28 dBm of total RF power generated by the chip. A larger array, composed of four CMOS chips and feeding a 2\,\times\,8 array of antennas, was shown to deliver an EIRP of 50 dBm at 45 GHz, while generating a total RF power of 33 dBm together with an antenna array gain of 17 dB. The dc power consumptions for the \2\,\times\,\2 and the 2\,\times\,8 arrays were 4.9 and 18 W, respectively, with estimated peak power-added efficiencies of 13.5% and 10.7%. [ABSTRACT FROM PUBLISHER]

This paper presents a reconfigurable mixed-signal-processing circuit for high-speed pulse compression radar (PCR). Mixed-signal design techniques incorporate calibration and adaptation to improve the performance of a PCR receiver. Adaptive bandwidth PCR is an important feature for maximizing the dynamic range of a low-power radar system. The baseband signal processor includes a variable gain amplifier, 4-bit digital-to-analog converter, high-speed analog correlator, passive integrator, a 4-bit flash analog-to-digital converter, and a multi-range delay-locked loop. This proposed system is fabricated in 90-nm CMOS and can be configured to work from 50 Mb/s to 1 Gb/s with 2/3/5/7-bit Barker codes. The proposed calibration techniques improve the sidelobe reduction to 15.6 dB at 1 Gb/s. The total power consumption is 42 mW at the peak rate of 1 Gb/s for 15-cm range resolution. [ABSTRACT FROM PUBLISHER]

Stacked field-effect transistor (FET) CMOS millimeter-wave power amplfiers (PAs) are studied with a focus on design of appropriate complex impedances between the transistors. The stacking of multiple FETs allows increasing the supply voltage, which, in turn, allows higher output power and a broader bandwidth output matching network. Different matching techniques for the intermediate nodes are analyzed and used in two-, three-, and four-stack single-stage Q-band CMOS PAs. A four-stack amplifier design achieves a saturated output power greater than 21 dBm while achieving a maximum power-added efficiency (PAE) greater than 20% from 38 to 47 GHz. The effectiveness of an inductive tuning technique is demonstrated in measurement, improving the PAE from 26% to 32% in a two-stack PA design. The input and output matching networks are designed using on-chip shielded coplanar waveguide transmission lines, as well as metal finger capacitors. The amplifiers were implemented in a 45-nm CMOS silicon-on-insulator process. Each of the amplifiers occupies an area of 600 \mum\,\times\,500 \mum including pads. [ABSTRACT FROM AUTHOR]

The performance of high-efficiency millimeter-wave (mm-wave) power amplifiers (PAs) implemented in a 45-nm silicon-on-insulator (SOI) process is presented. Multistage class-AB designs are investigated for Q- and W-bands and a push–pull amplifier is investigated at Q-band. The Q-band, class-AB PA achieves a saturated output power of 15 dBm and power-added efficiency (PAE) of 27% from a 2-V supply. The W-band, class-AB PA achieves a saturated output power of 12.4 dBm and PAE of 14.2% from a 2-V supply. The performance demonstrates the high efficiency possible for mm-wave PAs in a SOI process. [ABSTRACT FROM PUBLISHER]