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Reliability is an important consideration during semiconductor technology development, which ensures that the performances of devices, circuits, and systems are maintained over a specified period of time, leading to successful products. Device reliability is at the core of overall product reliability, which continues to remain an important area of research and has attracted the attention of IEEE Transactions on Electron Devices (T-ED) authors and readers throughout the years. Device reliability can be classified into two broad areas: gradual drift of device performance over time or sudden failure, and both are of importance for logic, memory, RF, and power devices. Different aspects of device reliability are usually reported, such as the development of electrical or physical characterization methods, investigation and modeling of a particular phenomenon, impact of material and processes on reliability, and development of reliability tolerant technologies. [ABSTRACT FROM AUTHOR]

In this paper, we present a comprehensive reviewand discussion of the state-of-the-art device technology and application development of GaN-on-Si power electronics. Several device technologies for realizing normally off operation that is highly desirable for power switching applications are presented. In addition, the examples of circuit applications that can greatly benefit from the superior performance of GaN power devices are demonstrated. Comparisonwith other competingpower device technology, such as Si superjunction-MOSFET and SiC MOSFET, is also presented and analyzed. Critical issues for commercialization of GaN-on-Si power devices are discussed with regard to cost, reliability, and ease of use. [ABSTRACT FROM AUTHOR]

GaN power switching transistors featuring MIS- and MOS-gate structures are highly preferred over the Schottky-gate counterpart, because of suppressed gate leakage, enlarged gate swing, and more scalable threshold voltage. Nevertheless, MIS-/MOS-gate GaN devices are confronted with stability and reliability challenges, which arise from interface traps at the critical dielectric/III-nitride interface, as well as bulk traps inside the gate dielectric including border traps near the critical interface. In this work, we present several key techniques toward reliable MIS-/MOS-gate GaN power devices, including advanced interface engineering technology, gate structure optimizations for high-performance/stability normally-off GaN power transistors, and long-lifetime gate dielectric technology. Schematic cross sections of GaN-based MIS-HEMT and MOS-channel-HEMT. [ABSTRACT FROM AUTHOR]

Effective interface engineering techniques in III-nitride heterojunction power devices, aiming at yielding high VTH stability in insulated-gate devices and suppressed current collapse in high-voltage switching operation, are of critical significance to enhance device performance and reliability. In this work, we present an interface enhancement technology featuring in situ low-damage NH3/Ar/N2 pre-gate plasma treatment prior to the ALD-Al2O3 deposition for high-performance III-nitride MIS-HEMTs. It is manifest that this technology can effectively remove the native oxide while forming a monocrystal-like nitridation interfacial-layer (NIL) on the III-nitride surface. The Al2O3(NIL)/GaN/AlGaN/GaN MIS-heterostructures with high-quality interface exhibit well-behaved electrical characteristics, including a small subthreshold swing of ∼64 mV/dec, a small hysteresis of ∼0.09 V, tiny f/T dispersions in the C- V characteristics, and low interface trap density of ∼1 × 1012-6 × 1012 cm−2eV−1. Cross-sectional TEM micrograph of the Al2O3/III-nitride gate stack with a monocrystal-like nitridation interfacial-layer (NIL). [ABSTRACT FROM AUTHOR]

III-N devices are suitable for high power RF/microwave amplifier, high temperature electronics, and power switches applications, and the peripheral mixed-signal electronics with sensing, protection, and control functions could provide optimized performance, increased functionality, and enhanced reliability. This paper addresses the technology to discuss the technology options of implementing III-N mixed-signal circuits, and then reviews the recent progress in the expansion of design library, based on monolithically integrated enhancement/depletion (E/D)-mode AlGaN/GaN HEMTs on GaN-on-silicon substrates. An integrated GaN proportional-to-absolute-temperature (PTAT) voltage source. [ABSTRACT FROM AUTHOR]

Due to the rapid advances taking place in the development and application of GaN electronics, there is an immediate need to take cognizance of the recent technological improvements and bring the potential and opportunities that exist in the area to a wider device community. The primary goal of this special issue is, therefore, to put together works in different aspects, including modeling, design, technology, characterization and applications so that this special issue will not only be of great archival value but also attract new researchers into this area for Digital Object Identifier 10.1109/TED.2013.2278653 further accelerating the application of III-N devices in building reliable, cheaper, and high-performance electronic systems. The papers collected in this special issue have been grouped into six topics. They are: 1) Fabrication and characterization of GaN-based devices. 2) High power GaN HEMTs for power switching applications. 3) High speed GaN HEMTs for RF applications. 4) Reliability and parasitic issues in GaN HEMTs. 5) Simulation-based development of GaN HEMTs devices. 6) GaN-based low noise amplifiers and gate drive circuits. [ABSTRACT FROM AUTHOR]

III-nitride heterostructure-based metal–insulator–semiconductor high-electron-mobility transistors (MIS-HEMTs), compared with Schottky and p-GaN gate HEMTs, have demonstrated significant potential in the next-generation high-power electronic devices due to their exceptional gate reliability. This study presents a comprehensive investigation of threshold voltage (VTH) instability in III-nitride heterostructure-based MIS-HEMTs, with a specific emphasis on the interfaces of the multi-heterostructures. Two widely studied amorphous materials, namely, Al2O3 and SiNx, have been extensively examined as primary gate insulators in GaN-based MIS-HEMTs. To efficiently remove native oxides from the (Al)GaN surface, a novel in situ high-temperature remote plasma pretreatment (RPP) technique has been developed. This technique involves sequential application of NH3/N2 plasmas on the (Al)GaN surface before depositing the gate insulators using plasma-enhanced atomic layer deposition. The remarkable RPP process has proven to be a highly effective method for revealing atomic steps on the GaN surface, irrespective of whether the surface has undergone oxidation or etching processes. To further enhance the interface quality and potentially reduce bulk traps in the gate insulator, optimization of deposition temperature and post-deposition annealing conditions have been explored. Additionally, an electron-blocking layer, such as SiON, is incorporated into the MIS-HEMTs to prevent electron injection into bulk traps within the insulator. Novel characterization techniques including constant-capacitance and isothermal-mode deep-level transient spectroscopy have also been developed to explore the failure mechanisms in MIS-HEMTs. These techniques allow for the differentiation between bulk traps in the GaN epitaxy and those present within the gate insulators. This in-depth physical understanding provides valuable insights into the sources of failure in GaN-based MIS-HEMTs. [ABSTRACT FROM AUTHOR]

Improvement of the AlGaN/GaN high-electron mobility transistor's (HEMT's) off -state breakdown voltage is achieved by implanting ^19\F^+ ions at an energy of 50 keV and dose of \1 \times \10^12\ \cm^-2 under the gate region using \BF3 as the source. The charge state of the implanted fluorine ions changes from positive to negative in the AlGaN/GaN structure because of fluorine's strong electronegativity. The negative-charged fluorine ions at the back side of the two-dimensional electron gas can raise the energy barrier of the GaN buffer layer under the channel, effectively blocking the current injected from the source to the high-field region of the GaN channel when the HEMT is biased at off-state. The source-injected electrons, if not blocked, could flow to the high-field region and initiate a premature three-terminal off-state breakdown in a conventional AlGaN/GaN HEMT. A 38% improvement of the three-terminal off-state breakdown voltage and 40% improvement of the power figure-of-merit VBD-off^2/Ron are achieved in the enhanced back barrier HEMT. [ABSTRACT FROM AUTHOR]

AlGaN/GaN high-electron mobility transistor's (HEMT's) off-state breakdown is investigated using drain-current injection techniques with different injection current levels. Competitions between the source leakage and gate leakage, pure leakage and impact ionization, and source- and gate-injection-induced impact ionization during the drain-injection measurement are discussed in detail. It was found that the breakdown originates from the source/gate leakage at low drain injection levels but is dominated by source/gate-induced impact ionization process at high drain injection currents. The source-induced impact ionization usually precedes the gate-induced impact ionization in low-gate leakage devices, resulting in a premature three-terminal off-state breakdown. We also found that the gate-bias value affects the breakdown voltage in the conventional three-terminal off-state breakdown I-V measurement and should be carefully considered. [ABSTRACT FROM AUTHOR]

In this article, a second-order dual-band bandpass filter is designed. The filter consists of two dual-band resonators connected by a dual-band admittance inverter. The dual-band resonator unit is made of two shunt stubs that coordinately produce two resonances. A novel dual-band quarter-wavelength line acts as the admittance inverter, providing suitable admittance transformations. To verify the design concept, a filter working at 2 and 5 GHz is devised and fabricated on Rogers' RO3006 printed circuit boards. In addition, the dual-band filter is connected with a bandstop filter to suppress the unwanted spurious response. © 2008 Wiley Periodicals, Inc. Microwave Opt Technol Lett 50: 1184–1187, 2008; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.23326 [ABSTRACT FROM AUTHOR]

In this paper, a compact computer-aided design (CAD)-oriented frequency-independent equivalent-circuit model, taking the skin effect, proximity effect, and substrate effect into consideration, is presented for the edge-suspended coplanar waveguide (ESCPW) on lossy silicon substrate. The ESCPWs exhibit the benefit of reduced loss, while avoid the reliability issues that are associated with the suspended coplanar waveguides. The model shows good agreement with the measured insertion loss and the extracted RLGC line parameters up to 25 GHz. With the model, the relationship between physical perimeters of the ESCPWs and the electrical characteristics is also investigated. Moreover, cross-coupling between adjacent ESCPWs with common ground is characterized and modeled. [ABSTRACT FROM AUTHOR]

We report several types of coplanar waveguide tri-section stepped-impedance resonator (SIR) structures that offer further size reduction compared to the conventional two-section SIRs. In addition, the tri-section SIRs provide flexibility of introducing effective capacitive coupling to the ground lines for realizing slow-wave structures. The slow-wave effect can be used to implement more compact bandpass filters. The principles of achieving size reductions using tri-section SIRs are described and confirmed by simulation results. To demonstrate the effectiveness of the proposed tri-section SIRs in size reduction, the tri-section SIRs with slow-wave effects were implemented in a two-pole directly coupled bandpass filter and a fourth-order quasi-elliptic bandpass filter with reduced size. The measured results matched well with the theoretical prediction. [ABSTRACT FROM AUTHOR]

In this paper, we present the detailed fabrication process, high-frequency characterization, and modeling of through-wafer copper-filled vias ranging from 50- to 70-μm-in diameter on 400-μm-thick silicon substrates. The high aspect ratio via-holes were fabricated by carefully optimizing the inductively coupled plasma deep reactive ion etching process. The high aspect ratio via-holes are completely filled with copper using a bottom-up electroplating approach. The fabricated vias were characterized using different resonating structures based on which the inductance and resistance of the filled via-holes are extracted. For a single 70-μm via, the inductance and resistance are measured to be 254 pH and 0.1 Ω, respectively. In addition, the effect of the physical arrangement and distribution in multiple-via configurations on the resulting inductance is also evaluated with double straightly aligned quadruple and diagonally aligned quadruple vias. Physical mechanisms of the dependence was depicted by electromagnetic simulation. An equivalent-circuit model is proposed and model parameters are extracted to provide good agreement. [ABSTRACT FROM AUTHOR]

A study was performed to characterize an optimum return trajectory for a sailplane after a rope-break failure during an aerotow launch procedure. The performance of an SGS 1-26E sailplane was simulated using the equations of motion for quasi-steady flight in a time-stepping routine and published aerodynamic polar data. A gradient-based optimization algorithm was implemented using the simulated trajectory considering the glide velocity, bank angles, and runway offset angle to determine the minimum rope-break altitude from which a successful return could be theoretically produced. The SGS 1-26E sailplane was used in a flight-test campaign for empirical turn modeling and validation of the performance simulation. The minimum altitude where a return trajectory and downwind runway landing could be successfully completed after a rope-break event was observed to be 76.4 ft above ground level. A headwind and crosswind presence was observed to decrease the minimum rope-break altitude with increasing wind velocity up to a critical value, after which rope-break altitudes began to increase. These minimum rope-break altitudes serve as a theoretical indication that safe trajectories can be performed at lower failure altitudes than the commonly practiced decision altitude of 200 ft for certain wind conditions. [ABSTRACT FROM AUTHOR]

Ultrathin oxides (UOs) and ultrathin nitrides (UNs) play a crucial role in forming lattice-mismatched semiconductor heterostructures that are fabricated by using semiconducting grafting approach. The grafting approach has shown its great potential to realize GaN-based heterojunction bipolar transistors by fulfilling the missing high-performance p-type nitrides with other p-type semiconductors. A handful of UO and UN dielectrics readily available by atomic layer deposition (ALD) satisfy the requirements of double-sided surface passivation and quantum tunneling for semiconductor grafting. Due to the states existing between the UO or UN conduction band and that of the GaN, the ALD deposited UO or UN layer can generate significant effects on the surface band-bending of GaN. Understanding the band parameters of the interface between UO or UN and c-plane Ga-face GaN can guide the selection of interfacial dielectrics for grafted GaN-based devices. In this study, we performed x-ray photoelectron spectroscopy measurements to obtain the band-bending properties on c-plane, Ga-face GaN samples coated by different ALD cycles of ultrathin-HfO2 or ultrathin AlN. The valence band spectra of GaN coated with ultrathin-ALD–Al2O3, ALD–HfO2, or PEALD–AlN/ALD–Al2O3 were further analyzed to calculate the valence and conduction band offsets between the ALD dielectrics and the Ga-face GaN under different thicknesses and post-deposition annealing conditions of the dielectrics. [ABSTRACT FROM AUTHOR]

Benzocyclobutene (BCB), a low-k, photosensitive, easily patterned material is used as the interfacing layer that isolates the passive components from the lossy, low-resistivity silicon. Its performance is further improved by reducing the conductive loss with an electroplated and highly-conductive metal, namely, copper. Standard 50-Ω microstrip lines and a microstrip-transmission-line-based microwave filter, exhibiting insertion losses of 0.8 dB and 1.1 dB at 10 GHz, respectively, are demonstrated. © 2004 Wiley Periodicals, Inc. Microwave Opt Technol Lett 40: 9–11, 2004; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.11271 [ABSTRACT FROM AUTHOR]

In this work, we manifest that the epitaxial structure for p-GaN gate high-electron-mobility transistor is a versatile platform to develop electronics for operating in an extremely wide temperature range (X-WTR) from 2 to 675 K, with comprehensive X-WTR studies on device operation and circuit behaviors. The key enabler for the high-temperature operation is the wide bandgap that substantially suppresses the thermal excitation of the intrinsic carrier. However, for the low-temperature side, the two-dimensional electron and hole gas (2DEG and 2DHG) channels at the heterojunctions are formed by the temperature-insensitive polarization fields, which free the carriers from freezing out. The monolithically integrated GaN n-FET, p-FET, and the resultant complementary circuits are, therefore, shown to operate in X-WTR. [ABSTRACT FROM AUTHOR]

In this work, AlN polarization-enhancement interlayer (AlN-PEL) is adopted to enhance two-dimensional hole gas (2DHG) density in a p-GaN/AlN-PEL(∼2 nm)/AlGaN(<6 nm)/GaN heterostructure, aiming at monolithic integration of p/n-channel field effect transistors (p-FETs) on GaN-on-Si substrate. Owing to the strong built-in polarization of the AlN-PEL, high density 2DHG over 2.3 × 1013 cm−2 with good immunity to thermal freeze out effect is realized. Assisted by a two-step gate trench etching process, enhancement-mode (E-mode) buried-channel GaN p-FETs with temperature independent ON-resistance RON, and ON/OFF current ratio ION/IOFF (>108), have been fabricated. The fabricated p-FETs also deliver thermally stable subthreshold swing as well as threshold voltage Vth, and smaller Vth shift than that of p-FETs without the AlN-PEL, which is primarily due to enhanced 2DHG confinement by the AlN-PEL. The proposed structure is an attractive platform for monolithic integration of GaN-based logic and power devices for cryogenic applications as low as 10 K. [ABSTRACT FROM AUTHOR]

A dual-gate superjunction insulated gate bipolar transistor (IGBT) (DG-SJ-IGBT) is proposed and studied with numerical TCAD simulations. The new structure utilizes the superjunction structure as a controlling port for the strength of conductivity modulation inside the IGBT, so that a low VON is obtained by a strong conductivity modulation during ON-state and a near-unipolar turn-off is achieved by removing the minority carriers before the turn-off event. For this purpose, the p-pillar in the DG-SJ-IGBT is connected to the p-body using a built-in p-channel MOSFET. The primary gate and the auxiliary gate (i.e., gate of p-MOSFET) are controlled by two separate driving signals. In the IGBT’s ON-state, the p-MOSFET disconnects the p-pillar, enabling full conductivity-modulated bipolar conduction and a consequent low VON. As a well-known issue, conductivity modulation is accompanied by significant additional turn-off loss (EOFF). To overcome this issue, the DG-SJ-IGBT takes advantage of the p-pillar which extends through the entire drift region. Before the IGBT’s turn-off event, the p-MOSFET electrically grounds the p-pillar to the p-body. The grounded p-pillar serves as a hole extractor, suppresses the minority carrier density throughout the depth of the drift region, and brings the device into a near-unipolar conduction mode. Thus, a near-unipolar turn-off can be obtained, resulting in a low EOFF. [ABSTRACT FROM AUTHOR]

The p-GaN/AlGaN/GaN heterostructure, predominantly epitaxially grown on large-scale silicon wafers, has been widely used for producing consumer power switching devices and recently manifested favorable for developing GaN-based complementary devices and circuits. This work investigates the hole distribution and transport in this structure based on wide-temperature-range (20–600 K) Hall measurements and TCAD simulations. It is revealed that the p-channel thereof is composed of the bulk holes in the p-GaN and the two-dimensional hole gas (2DHG) at the p-GaN/AlGaN interface, and both substantially contribute to the lateral p-type conduction at room temperature. Their complementary temperature responses lead to conductivity enhancement at both high- and low-temperature regimes. The high-density (1.2 × 1013 cm−2) 2DHG is formed owing to the polarization-induced potential well and the ionization of the Mg acceptors that thermally diffused into the barrier during the epi-growth. Such ionized Mg acceptors would partially deplete the two-dimensional electron gas (2DEG) at the access region in the n-channel side where the p-GaN is removed and result in a trade-off between the carrier density of 2DHG and 2DEG. [ABSTRACT FROM AUTHOR]

A physical insight into the capture and emission behavior of interface/oxide states in a GaN-based metal-oxide-semiconductor (MOS) structure is of great importance to understanding the threshold voltage (VTH) instability in GaN power transistors. A time-dependent VTH shift in Ni/Al2O3/AlGaN/GaN MOS-HFETs (heterojunction field-effect transistors) and a distribution of Al2O3/III-nitride interface states (Dit) were successfully characterized by constant-capacitance deep level transient spectroscopy. It is found that in situ remote plasma pretreatments in plasma-enhanced atomic-layer-deposition could suppress Dit (EC-ET > 0.4 eV) down to below 1.3 × 1012 cm−2 eV−1. Under high applied gate bias (e.g., VG > 8 V), tunnel filling of oxide states in the Al2O3 dielectric comes into play, contributing to remarkable VTH instability in the MOS-HFETs. The tunnel distance between the 2D Electron Gas (2DEG) channel and oxide states ET,ox in the Al2O3 dielectric decreases from 3.75 to 0.82 nm as VG increases from 2 to 8 V. A further increase of VG to 11 V makes the Fermi level approach ET,ox (EC − ET ∼ 1.62 eV), which may enable direct filling. High electric field induced tunnel filling of gate oxide states could be an assignable cause for VTH instability in normally-OFF III-nitride MOS-HFETs. [ABSTRACT FROM AUTHOR]

Surface functionalization of the dangling-bond-free MoS2, WSe2, and other TMDs (transition metal dichalcogenides) is of large practical importance, for example, in providing nucleation sites for the subsequent high-k dielectric integration. Of the surface functionalization methods, the reversible O or N atom adsorption on top of the chalcogen atoms is most promising. However, hazards such as severe oxidation or nitridation persist when the adsorption coverage is high. An in situ characterization technique, which can be integrated with the surface functionalization and dielectric deposition chamber, becomes valuable to enable the real-time monitoring of surface adsorption conditions. Raman spectroscopy, as a nondestructive characterization method without vacuum requirement, is a strong candidate. By utilizing first-principles calculations, Raman spectra of single-layer MoS2 and WSe2 with various O/N adsorption coverages are studied. The calculations suggest that the low-coverage O/N adsorbates will act as perturbations to the periodic lattice and activate the acoustic-phonon Raman scatterings. While high-coverage adsorptions will further activate and intensify the optical-phonon Raman scatterings of previously silent A2u and E1g modes, due to the breaking of reflection symmetry in the z direction, new phonon modes associated with the adatom oscillations are also introduced. All these pieces of evidence, together with the peak shifts of previously active A1g and E2g¹ modes, suggest that in situ resonant Raman spectroscopy is capable of providing important information to quantify the O/N adsorption coverage and can be used as a valuable real-time characterization technique to monitor and control the surface functionalization conditions of MoS2 and WSe2. [ABSTRACT FROM AUTHOR]

Wide bandgap III‐nitride (III‐N) power switching transistors are capable of delivering superior performance for next‐generation energy‐efficient and compact power conversion systems. Owing to suppressed gate leakage and enlarged gate swing, III‐N insulatedgate devices are highly preferred over the conventional Schottkygate counterparts for high‐voltage power switches. Meanwhile, surface passivation with dielectric deposited in the gate–drain access region is necessary to allievate the surface‐state induced current collapse in high‐voltage switching operation. Therefore, effective interface engineering techniques for III‐N devices are of critical significance to enhance threshold‐voltage stability and dynamic performance. Chen et al. (pp. 1059–1065) present an interface enhancement technology featuring in situ low‐damage NH3/Ar/N2 pre‐gate plasma treatment prior to the Al2O3 gatedielectric deposition. This technology can effectively remove the native oxide while forming a monocrystal‐like nitridation interfaciallayer (NIL) with Al–N bonds on the III‐N surface, enabling the realization of high‐performance and high‐stability III‐N insulatedgate devices. The Al2O3(NIL)/GaN/AlGaN/GaN MIS heterostructures with high‐quality interface exhibit record electrical characteristics, including a steep subthreshold swing of ∼64 mV/dec, a small hysteresis of ∼0.09 V, tiny f/T‐dispersions in the capacitance– voltage characteristics, and low interface trap density. [To honour the laureates of the Nobel Prize in Physics 2014, the cover of this pss (a) issue shows a specially designed pss logo assembled from blue nitride LEDs (courtesy of Armin Dadgar, Technical University of Magdeburg)]. [ABSTRACT FROM AUTHOR]

A normally-off SiC-JFET/GaN-HEMT cascode device is recently proposed, featuring a cascode configuration that incorporates a high-voltage (HV, e.g., 1200 V) silicon-carbide (SiC) junction field effect transistor (JFET) delivering the HV blocking capability and a low-voltage (LV) enhanced-mode (E-mode) gallium-nitride (GaN) high electron mobility transistor (HEMT) providing the normally-off gate control. This all-wide-bandgap device exhibits superior thermal stability and high switching speed compared to its counterparts, e.g., the SiC/Si cascode device. In this article, we study short-circuit (SC) characteristics of a 1200-V/80-mΩ SiC/GaN cascode device by considering the interactions between the SiC and GaN devices. The single-event SC withstand time (SCWT) of the demonstrated SiC/GaN cascode device is tested to be ∼3 μs under a dc-bus voltage (Vdc) of 600 V when the turn-on gate voltage (VG-on) is set to 5 V. The SC failure occurs due to the formation of hot spots induced by thermal-runaway leakage currents inside the SiC JFET. The SCWT of the cascode device could be improved by applying a moderate VG-on (e.g., SCWT = ∼6.5 μs at VG-on = 3.5 V under v dc = 600 V) without affecting the on-state resistance (r on). However, it is identified that current oscillations tend to be triggered during the SC period when VG-on is too low (e.g., lower than 3 V). The oscillation behavior is attributed to the energy stored in the interconnection parts between the SiC and GaN devices. The harmful oscillations could be suppressed by applying higher VG-on, which drives the SiC JFET into low-transconductance mode by modulating the drain-to-source voltage (VDS-G) of the LV GaN HEMT. [ABSTRACT FROM AUTHOR]

A 650-V/84-mΩ normally-off GaN/SiC cascode device is demonstrated with systematic static and dynamic characterizations. The cascode device features a low-voltage enhancement-mode (E-mode) gallium nitride (GaN) high electron mobility transistor (HEMT) to enable normally-off gate control, and a 650-V normally-on silicon carbide (SiC) JFET provides the high-voltage blocking capability. The GaN/SiC cascode device exhibits many application-desired behaviors, including reverse conduction capability, avalanche breakdown capability, thermally stable threshold voltage, low input/output capacitances, no dynamic RON degradation, and negligible dynamic VTH shift. In addition, a customized double-pulse test board is built to evaluate the switching performance of this cascode device and other 650-V SiC-based power devices. This cascode device adopting low-voltage GaN HEMT has low QG×RON and exhibits excellent switching performance. The switching losses (EON and EOFF) are much smaller than that of the 650-V Si/SiC cascode device and comparable to that of the state-of-the-art 650-V SiC MOSFETs. [ABSTRACT FROM AUTHOR]

The rat surgical anterior cruciate ligament transection (ACLT) model is commonly used to investigate intra‐articular osteoarthritis (OA) therapies, and histological assessment is often the primary outcome measure. However, histological changes do not always correlate well with clinical outcomes. Therefore, this study evaluated functional outcomes in the rat surgical ACLT model and compared intra‐articular injection volumes ranging from 20 to 50 μl. Unilateral ACLT was surgically induced and static weight‐bearing, mechanical allodynia, motor function, and gait were assessed in four groups of male, Sprague‐Dawley rats (n = 6 per group). Intra‐articular injections of 20 µl Dulbecco's phosphate‐buffered saline (DPBS), 50 µl DPBS, or 50 µl of synthetic biomimetic boundary lubricant were administered once weekly for 3 weeks postoperatively. Structural changes were evaluated histologically at 20 weeks. Rat cadaver knees were injected with 20, 30, 40, or 50 µl of gadolinium solutions and were imaged using magnetic resonance imaging (MRI). Static weight‐bearing, mechanical allodynia, and gait parameters in ACLT groups revealed differences from baseline and naïve controls for 4 weeks post‐ACLT; however, these differences did not persist beyond 6 weeks. Different intra‐articular DPBS injection volumes did not result in functional or histological changes; however, peri‐articular leakage was documented via MRI following 50, 40, and 30 µl but not 20 µl gadolinium injections. Statement of clinical significance: Differences in functional parameters were predominantly restricted to early, postoperative changes in the rat surgical ACLT model despite evidence of moderate histologic OA at 20 weeks. Injection volumes of 20–30 µl are more appropriate for investigating intra‐articular therapies in the rat knee. [ABSTRACT FROM AUTHOR]

A cost-effective engineered bulk silicon (EBUS) substrate technology is presented, featuring p-n junction implemented on bulk Si substrates using mainstream ion implantation and thermal annealing processes. Standard p-GaN/AlGaN/GaN heterostructures are successfully grown on the EBUS substrate and used to fabricate 200-V enhancement-mode p-GaN gate HEMTs. By creating deep trenches in the EBUS substrate to isolate the local P+ silicon regions underneath the high-side (HS) and low-side (LS) power switches, adverse effects (e.g., back-gating and dynamic ON-resistance degradation) in the use of conventional bulk Si substrate are all eliminated. The mechanism of crosstalk suppression in the GaN-on-EBUS platform is revealed in comparison with conventional GaN-on-Si platform and verified by a series of designed tests. [ABSTRACT FROM AUTHOR]

Our previously reported structures of calpain bound to its endogenous inhibitor calpastatin have motivated the use of aziridine aldehyde-mediated peptide macrocyclization toward the design of cyclic peptides and peptidomimetics as calpain inhibitors. Inspired by nature's hint that a β-turn loop within calpastatin forms a broad interaction around calpain's active site cysteine, we have constructed and tested a library of 45 peptidic compounds based on this loop sequence. Four molecules have shown reproducibly low micromolar inhibition of calpain-2. Further systematic sequence changes led to the development of probes that displayed increased potency and specificity of inhibition against calpain over other cysteine proteases. Calculated Ki values were in the low micromolar range, rivaling other peptidomimetic calpain inhibitors and presenting an improved selectivity profile against other therapeutically relevant proteases. Competitive and mixed inhibition against calpain-2 was observed, and an allosteric inhibition site on the enzyme was identified for a noncompetitive inhibitor. [ABSTRACT FROM AUTHOR]

Strict and repeated lockdowns have caused public fatigue regarding policy compliance and had a large impact on several countries' economies. We aimed to evaluate the effectiveness of a soft lockdown policy and the strategy of active community screening for controlling COVID-19 in Taiwan. We used village-based daily confirmed COVID-19 statistics in Taipei City and New Taipei City, between May 2, 2021, and July 17, 2021. The temporal Gi* statistic was used to compute the spatiotemporal hotspots. Simple linear regression was used to evaluate the trend of the epidemic, positivity rate from community screening, and mobility changes in COVID-19 cases and incidence before and after a level three alert in both cities. We used a Bayesian hierarchical zero-inflated Poisson model to estimate the daily infection risk. The cities accounted for 11,403 (81.17%) of 14,048 locally confirmed cases. The mean effective reproduction number (Re) surged before the level three alert and peaked on May 16, 2021, the day after the level three alert in Taipei City (Re = 3.66) and New Taipei City (Re = 3.37). Mobility reduction and a lower positive rate were positively associated with a lower number of cases and incidence. In the spatiotemporal view, seven major districts were identified with a radial spreading pattern from one hard-hit district. Villages with a higher inflow degree centrality among people aged ≥ 60 years, having confirmed cases, specific land-use types, and with a higher aging index had higher infection risks than other villages. Early soft lockdown policy and detection of infected patients showed an effective strategy to control COVID-19 in Taiwan. [ABSTRACT FROM AUTHOR]

The high-speed superiority of GaN power devices with silicon-based peripheral circuits is not yet fully leveraged, mainly due to the parasitic inductance of interconnections. In this article, we demonstrate a GaN-based gate driver with an overcurrent (OC) protection circuit and an undervoltage lockout (UVLO) circuit on a p-GaN gate power HEMT platform. The gate driver features a rail-to-rail output voltage, suppressed gate ringing, and tunable driving speed, all of which are highly desired in high-efficiency and high-speed GaN power systems. To offer timely but reliable protections, the OC protection and UVLO circuit are designed with reference to the switching speed and the threshold voltage of GaN power devices. The OC protection is implemented with a separated sensing branch and blanking time controller, and the response time to an OC event is reduced to 10 ns after the blanking time. The UVLO circuit has a fixed hysteresis of 0.5 V, and its threshold voltage is especially tailored for the GaN integrated circuits. [ABSTRACT FROM AUTHOR]

Although the gallium nitride (GaN) high-electron-mobility transistor/silicon carbide (SiC) junction field-effect transistor (JFET) cascode device exhibits certain performance advantages over the SiC metal–oxide–semiconductor field-effect transistor (MOSFET), its robustness in harsh operating conditions is unknown. In this work, the short-circuit (SC) robustness of 650-V GaN/SiC cascode devices is characterized, analyzed, and compared with that of several mainstream SiC MOSFETs. GaN/SiC cascode devices exhibit competitive SC capability. Different failure modes are observed: thermal runaway in the SiC JFET of the cascode device and gate-to-source breakdown in the SiC MOSFET. The difference is associated with the configuration of the dielectric above SiC in the JFET and the source pad layout. According to the waveforms in SC events, failure spots, and thermal simulation results, a thermal runaway in the SiC JFET is attributed to the positive feedback between the drain leakage current and the junction temperature in the local area (hotspot) without the source pad on the top. The SC withstand time of the cascode device can be extended by reduction of the active area without the source pad. [ABSTRACT FROM AUTHOR]

In this article, the impacts of the off-state gate bias (VGS,OFF) on dynamic on-resistance (RON) are systematically investigated in commercial Schottky-type p-GaN Gate high-electron-mobility transistors. Double-pulse tester and pulsed I–V system are adopted to evaluate the dynamic RON with various off-state gate and drain bias (VDS,OFF) under hard- and soft-switching conditions. More negative VGS,OFF can aggravate the dynamic RON degradation under both soft- and hard-switching, especially when switching with a high VDS,OFF. The impacts of VGS,OFF on switching transients and off-state stress are investigated separately to reveal the underlying mechanisms, which are found to be associated with the generation and movements of holes. The off-state gate bias of the voltage-driving scheme needs to be carefully considered according to the identified mechanisms in terms of dynamic on-resistance degradation. [ABSTRACT FROM AUTHOR]

Enhancement-mode (E-mode) p-channel gallium nitride (GaN) field-effect transistors (p-FETs) are essential components for GaN-based complementary logic circuits. For the ease of integration with n-FETs, they could be fabricated on the commercial p-GaN gate high-electron-mobility-transistor (HEMT) platform, on which the two-dimensional electron gas at the AlGaN/GaN hetero-interface is completely depleted in as-grown epi-structures. However, under the gated region where p-GaN is recessed and depleted at thermal equilibrium, a parasitic electron channel (PEC) could appear at the AlGaN/GaN interface. This Letter reports experimental investigations on the PEC with specifically designed structures, confirming that the PEC does exist but imposes limited impacts on electrical characteristics of p-FETs. When connected with an external contact, the PEC could act as a back gate to modulate the overlaying p-channel. If isolated from external contacts, which is the case of p-FETs under normal operations, electrons in the PEC would redistribute under the active region of p-FETs in the horizontal direction (i.e., parallel to the surface) under different biases but are mostly confined near the AlGaN/GaN interface in the vertical direction (i.e., perpendicular to the surface). [ABSTRACT FROM AUTHOR]

We report GaN high-electron-mobility transistors (HEMTs) with a thick (7.7 µm) GaN buffer on a Czochralski low resistivity Si (LRS) substrate. The GaN HEMTs exhibit high performance for both radio-frequency (RF) amplification and power conversion. The thick GaN buffer was grown by means of vacancy engineering, delivering a low dislocation density of ∼1.6 × 108 cm−2, contributing to suppressed RF signal coupling to the lossy Si substrate and a high vertical voltage blocking capability. For RF performance, GaN HEMTs with a 650 nm gate exhibit an fT/fMAX value of 25.1/32.3 GHz and a maximum output power POUT of 2.2 W/mm at 4 GHz with a drain voltage VDS of 20 V, which is comparable with the performance of RF GaN HEMTs on a high-resistivity silicon substrate without the existence of the field plate. For power performance, the vertical breakdown voltage of the wafer is 1160 V, and the three-terminal lateral breakdown voltage is 885 V in a GaN HEMT with a gate-to-drain distance of 8 µm. The thick GaN layer on the LRS substrate scheme thus provides a compelling platform for monolithic integration of high-performance RF devices and high-voltage power devices. [ABSTRACT FROM AUTHOR]

In this work, a deliberate etching-based top-down approach is proposed to fabricate the GaN nanorod (NR) Schottky barrier diode (SBD). As a key step during the fabrication, the impact of the wet-etching process on device performance is systematically studied. By virtue of the reduced surface states at the sidewall, the performance of NR SBD with the wet-etching process is substantially improved, delivering a forward turn-on voltage of 0.65 V, a current density of ∼10 kA/cm2 at 3 V, an ideality factor of 1.03, an ON/OFF current ratio of ∼1010, and no severe current collapse, along with a reverse breakdown voltage of 772 V. [ABSTRACT FROM AUTHOR]

Recently, a GaN reverse-conducting high-electron-mobility transistor (RC-HEMT) has been demonstrated. The RC-HEMT features built-in distributive Schottky contacts, which provide a low-loss freewheeling path. The RC-HEMT offers the same functionality as an HEMT/Schottky barrier diode (SBD) pair, but consumes much less chip area, thus its ${R}_{ \mathrm{\scriptscriptstyle ON}}$ (ON-resistance $\times $ total device width) is significantly reduced. Theoretically, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT can approach that of an HEMT. In practice, due to certain geometry limitations, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of an RC-HEMT lies between an HEMT/SBD pair and a single HEMT. This work investigates the factors that influence ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT using both experimental measurements and numerical simulations. It is found that ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is strongly affected by the geometry of the source and channel regions, where HEMT sections and SBD sections are interdigitally distributed. With coarse patterning of these regions, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of the RC-HEMT is close to the HEMT/SBD pair. Through proper geometry scaling, ${R}_{ \mathrm{\scriptscriptstyle ON}}$ of RC-HEMT is reduced and approaches that of HEMT. [ABSTRACT FROM AUTHOR]

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoHLED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The detrapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance Ron and/or threshold voltage Vth of the HEMT. The results show that the recovery processes of both dynamic Ron and threshold voltage Vth of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs. [ABSTRACT FROM AUTHOR]

In this work, by using an on-chip integrated Schottky-on-heterojunction light-emitting diode (SoHLED) which is seamlessly integrated with the AlGaN/GaN high electron mobility transistor (HEMT), we studied the effect of on-chip light illumination on the de-trapping processes of electrons from both surface and bulk traps. Surface trapping was generated by applying OFF-state drain bias stress, while bulk trapping was generated by applying positive substrate bias stress. The detrapping processes of surface and/or bulk traps were monitored by measuring the recovery of dynamic on-resistance Ron and/or threshold voltage Vth of the HEMT. The results show that the recovery processes of both dynamic Ron and threshold voltage Vth of the HEMT can be accelerated by the on-chip SoH-LED light illumination, demonstrating the potentiality of on-chip hybrid opto-HEMTs to minimize the influences of traps during dynamic operation of AlGaN/GaN power HEMTs. [ABSTRACT FROM AUTHOR]

This article was originally published online on 27 December 2023 with an error in the affiliation. The affiliation appears correct above. All online versions of this article were corrected on 4 April 2024.By Yingjie Wang; Sen Huang; Qimeng Jiang; Xinhua Wang; Zhongchen Ji; Jie Fan; Haibo Yin; Ke Wei; Xinyu Liu; Qian Sun and Kevin J. ChenReported by Author; Author; Author; Author; Author; Author; Author; Author; Author; Author; Author [Extracted from the article]

The short circuit (SC) behavior of a newly developed GaN-HEMT/SiC-JFET cascode device is investigated in this work. The reverse leakage current through the drain-side PN junction (IR) of the SiC JFET under SC conditions is measured simultaneously during the SC event. IR of the SiC JFET increases to 6.4 A at the end of a 5-μs nondestructive SC pulse. The increase of IR during the SC pulse induces a turning point in the SC current waveform and a dramatic negative threshold voltage shift (>30 V) in the SiC JEFT, resulting in high transient drain-to-source voltage in the GaN HEMT. The underlying mechanism is associated with the increase of local potential in the P-type layer of the SiC JFET with inevitable spread resistance (RSPD). It is suggested that reducing RSPD can improve SC capability and high IR should be considered in SC failure mechanism analysis and the design of external gate resistance of the SiC JFET. [ABSTRACT FROM AUTHOR]

Background: Anaplastic thyroid cancer (ATC) is a rare cancer with poor prognosis and few treatment options. The objective of this study was to investigate new immune-associated therapeutic targets by identifying ATC-derived, human leukocyte antigen (HLA) class II-presenting peptides. One protein that generated multiple peptides in ATC was chondroitin sulfate-proteoglycan-4 (CSPG4), a transmembrane proteoglycan with increased expression in multiple aggressive cancers, but not yet investigated in ATC. Methods: We applied autologous peripheral blood T cells to ATC patient-derived xenografted mice to examine whether ATC induces a tumor-specific T cell response. We then identified peptide antigens eluted from the HLA-DQ complex in ATC patient-derived cells using mass spectrometry, detecting abundant CSPG4-derived peptides specific to the ATC sample. Next, we analyzed the surface expression level of CSPG4 in thyroid cancer cell lines and primary cell culture using flow cytometry. In addition, we used immunohistochemistry to compare the expression level and localization of the CSPG4 protein in ATC, papillary thyroid cancer, and normal thyroid tissue. We then investigated the correlation between CSPG4 expression and clinicopathological features of patients with thyroid cancer. Results: We found that ATC tissue had a high level of HLA-DQ expression and that the patient's CD4+ T cells showed activation when exposed to ATC. By eluting the HLA-DQ complex of ATC tissue, we found that CSPG4 generated one of the most abundant and specific peptides. CSPG4 expression at the cell surface of thyroid cancer was also significantly high when determined by flow cytometry, with the majority of ATC cell lines exhibiting ∼10-fold higher mean fluorescence intensity. Furthermore, most ATC patient cases expressed CSPG4 in the cytoplasm or membrane of the tumor cells. CSPG4 expression was correlated with tumor size, extrathyroidal extension, and intercellular adhesion molecule-1 (ICAM-1) circumferential expression. CSPG4 mRNA overexpression was associated with worse overall survival in patients with ATC and poorly differentiated thyroid cancer. Conclusions: CSPG4 expression is significantly elevated in aggressive thyroid cancers, with a strong correlation with a poor prognosis. The vast number of HLA-DQ eluted CSPG4 peptides was identified in ATC, demonstrating the potential of CSPG4 as a novel immunotherapeutic target for ATC. [ABSTRACT FROM AUTHOR]

Short circuit (SC) capability of 650-V Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) under single and repetitive tests is characterized in this article. The investigated devices exhibit strong capability under a single SC test, but weak capability under repetitive SC tests with a bus voltage of 400 V and a gate drive voltage of 6 V. The failure mechanism under repetitive SC tests is revealed through electrothermal simulation and microscale failure spot analysis. Thermal fatigue cracks are formed due to the high temperature spike and local temperature fluctuations in the narrow GaN channel and buffer layers, leading to weak repetitive SC capability. The unique heat confinement effect in the GaN layer plays an important role in the formation of high temperature spike and fatigue cracks. The withstand time in a single SC test is several hundred microseconds due to fast drain current drop that results from high temperature and, to a lesser degree, the dynamic threshold voltage shift during the SC transient. The device failure in a single-event SC test is related to heat diffusion to a wider region. Some guidelines are proposed for handling and improving the repetitive SC capability. [ABSTRACT FROM AUTHOR]

The surface of the p-GaN layer in Schottky-type p-GaN gate high-electron-mobility transistors (HEMTs) can be reinforced with enhanced immunity to hot electron bombardment by reconstructing the surface region of p-GaN into GaON. The surface region of p-GaN is treated by remote oxygen plasma and subsequently annealed at 800 °C, thereby becoming a thin crystalline gallium oxynitride (GaON) layer that will be in direct contact with the Schottky metal. The GaON exhibits a lower valence band maximum energy than that of the p-GaN, which leads to a higher Schottky barrier at the metal/GaON interface to holes and, thus, greatly suppresses the forward gate leakage. More importantly, with higher thermodynamic stability and a larger bandgap of ∼4.1 eV, the GaON reinforces the susceptible metal/p-GaN interface against the hot electrons and, thus, substantially enhances the long-term gate reliability of p-GaN gate HEMTs under forward bias stress. The high-temperature thermal process is indispensable for the surface reconstruction, without which the plasma oxidation only reduces the gate leakage but fails to prolong the time-dependent gate breakdown lifetime. [ABSTRACT FROM AUTHOR]

Background: Sentinel physician surveillance in communities has played an important role in detecting early signs of epidemics. The traditional approach is to let the primary care physician voluntarily and actively report diseases to the health department on a weekly basis. However, this is labor-intensive work, and the spatio-temporal resolution of the surveillance data is not precise at all. In this study, we built up a clinic-based enhanced sentinel surveillance system named "Sentinel plus" which was designed for sentinel clinics and community hospitals to monitor 23 kinds of syndromic groups in Taipei City, Taiwan. The definitions of those syndromic groups were based on ICD-10 diagnoses from physicians. Methods: Daily ICD-10 counts of two syndromic groups including ILI and EV-like syndromes in Taipei City were extracted from Sentinel plus. A negative binomial regression model was used to couple with lag structure functions to examine the short-term association between ICD counts and meteorological variables. After fitting the negative binomial regression model, residuals were further rescaled to Pearson residuals. We then monitored these daily standardized Pearson residuals for any aberrations from July 2018 to October 2019. Results: The results showed that daily average temperature was significantly negatively associated with numbers of ILI syndromes. The ozone and PM2.5 concentrations were significantly positively associated with ILI syndromes. In addition, daily minimum temperature, and the ozone and PM2.5 concentrations were significantly negatively associated with the EV-like syndromes. The aberrational signals detected from clinics for ILI and EV-like syndromes were earlier than the epidemic period based on outpatient surveillance defined by the Taiwan CDC. Conclusions: This system not only provides warning signals to the local health department for managing the risks but also reminds medical practitioners to be vigilant toward susceptible patients. The near real-time surveillance can help decision makers evaluate their policy on a timely basis. [ABSTRACT FROM AUTHOR]

In this article, the coupling coefficients of the coupled-resonator filters are extracted using the genetic algorithms (GA). To demonstrate the feasibility of the proposed method, filters with different orders and different characteristics are tested. In all cases, the parameters of these filters can be efficiently identified without any a priori knowledge. © 2011 Wiley Periodicals, Inc. Int J RF and Microwave CAE, 2011. [ABSTRACT FROM AUTHOR]

The ON-resistance and its temperature dependence of the high electron mobility transistor (HEMT)-compatible lateral field-effect rectifier (L-FER) are investigated. Three types of transfer length method (TLM) patterns are utilized to extract the temperature-dependent electrical parameters of the resistance model. The technique presented in this paper delivers a direct and simple methodology for the investigation of the temperature dependence of the ON-resistance in the L-FER. The simulated output characteristics of the L-FER are in good agreement with the experimental results. [ABSTRACT FROM AUTHOR]

GaN smart power chip technology has been realized using a GaN-on-Si HEMT platform, featuring monolithically integrated high-voltage power devices and low-voltage peripheral devices for mixed-signal functional blocks. In particular, this brief presents the imperative analog functional block-voltage reference generator for smart power applications with wide-temperature-range stability. The circuit is capable of proper functions within a wide temperature range from room temperature up to 250 °C, illustrating the unique advantage of the wide-bandgap GaN in high-temperature operation. The voltage reference generator was designed with an AlGaN/GaN HEMT and Schottky diodes, and the devices were operated in the subthreshold regime to obtain low power consumption. The voltage reference generator achieved an average drift of less than 0.5 mV/°C and can be used as a reference voltage in various biasing and sensing circuits. [ABSTRACT FROM AUTHOR]

Abstract: We report detailed results on the temperature dependence and thermal stability of the planar-integrated enhancement/depletion-mode (E/D-mode) AlGaN/GaN high-electron mobility transistors (HEMTs). Compared to the standard mesa etching technique, the plasma treatment can achieve the same device isolation results. The E/D-mode HEMTs and the corresponding digital integrated circuits fabricated by the planar process exhibit stable operation from room temperature up to 350°C. No degradation in device performance was observed after a 140-h thermal stress at 350°C, implying excellent thermal stability of the planar process. The direct-coupled FET logic inverter, realized by planar-integration of E/D-mode HEMTs, presents larger noise margins (NMS) at high temperatures than the previously reported work, demonstrating promising potential for GaN-based high-temperature digital ICs. The NM improvement can be attributed to the higher threshold voltage and the improved gate turn-on voltage of the E-mode HEMTs that is achieved with larger plasma treatment dose. [Copyright &y& Elsevier]

The threshold voltage (VTH) of an enhancement-mode Schottky-type p-GaN gate high-electron-mobility transistor (HEMT) is found to have a special dependence on the drain bias. The device commonly requires higher gate voltage to switch on the transistor from a high-drain-voltage off-state than what is expected from the static device characteristics. The reason behind the dynamic VTH has been proved to be the floating p-GaN layer, where charges could be stored and further influence VTH under different drain bias. In this article, a SPICE-compatible equivalent circuit model is presented according to the structure of Schottky-type p-GaN gate HEMTs. It features a floating node to imitate the charge storage process within the gate stack. Compared to conventional models, the proposed model could accurately predict the dynamic VTH characteristics and switching behaviors of power electronics circuits, where Schottky-type p-GaN gate HEMTs are deployed as power transistors. The phenomena related to the dynamic VTH, including the disappearance of Miller plateau, the overestimated false-turn-on problem, and the higher reverse conduction loss are evaluated with a half-bridge circuit and the merits of the proposed model are verified. [ABSTRACT FROM AUTHOR]

A physical-based analytical model for on-chip inductors is developed. A ladder structure is used to model the skin and proximity effects in metal lines. The substrate electric and substrate magnetic losses are accurately modeled by RC and RL ladder structures, respectively. The effective inductance reduction due to the eddy current in the lossy silicon substrate at high frequency is modeled by a negative mutual inductance between the inductor and the substrate. All the model parameters can be calculated from the layout and process parameters. On-chip inductors with different geometries and substrate resistivities were fabricated for the verifications. The measured results are in very good agreement with the proposed model. This generic model can be applied to various substrate resistivities; thus, it is suitable for different technologies. This model can facilitate the design and optimization of on-chip inductors for RF IC applications. [ABSTRACT FROM AUTHOR]