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A novel stepped oxide hetero-material gate trench power MOSFET with three sections in the gate, consisting of an [N.sup.+] poly gate sandwiched between two [P.sup.+] poly gates, and of different gate oxide thicknesses is proposed. The features result in reduced switching delays and improved breakdown voltage, thereby enhancing the performance of the power MOSFET.

Several experiments are conducted to explain the impact of the biaxial tensile strain on the Coulomb scattering mobility in the inversion layer of the biaxially strained-silicon (Si) pMOSFETs. The hole mobility limited by substrate-impurity Coulomb scattering is shown to get degraded because of the biaxial tensile strain.

An enhancement of an existing approximation to the solution of a key transcendental equation in symmetric double-gate metal-organic field-effect transistors (DGFETs) is described. The enhancement has increased the numerical robustness of the original approximation of surface potential while causing no loss in computational efficiency.

A geometry-scalable parasitic deembedding technique for on-wafer S-parameter measurements of silicon MOSFETs is presented. The developed method is observed to be accurate, area efficient, and time saving for evaluating the intrinsic characteristics of silicon-based devices.

The stress simulation with the three-dimensional (3-D) boundary effects and their impact on the transistor performance are described. The ultrahigh compressive stress contact-etching-stop layer (CESL) stressor, SiGe source-drain (S/D) stressor with high Ge concentration and optimal design in device dimensions has achieved the high-performance pFET.

Early-stage hot-electron generation has injected electrons into the shallow trench isolation (STI) edge above the drift region that has caused the linear-region drain current to increase in the first moment of the stress of P-LDMOS transistors. The studies have shown that the amount of current increase has depended on the distance from the maximum impact ionization generation rate point to the STI.

The device operation of the Charge Sheet Superjunction (CSSJ), whose specific on-resistance for a given breakdown voltage is even lower than those of a Superjunction (SJ), is described. A simple analytical model is developed for the drain-source capacitance of the CSSJ MOSFET, which can also be used for SJ MOSFET.

An analytic channel-potential-based non-charge-sheet model for long-channel symmetric double-gate (DG) MOSFETs with smooth transition between partially and full depleted (PD and FD) operation modes is described. The model has helped in understanding the DG MOSFET device physics, which has provided a physics-based DG MOSFET compact modeling framework for circuit simulation.

Analytical models of subthreshold current and slope for asymmetric four-terminal double-gate (DG) MOSFETs are described, which can be used for studying the subthreshold characteristics with asymmetry in gate oxide thickness, gate material work function and gate voltage. The results have shown excellent match with simulations by using MEDICI.

The impact of strain on negative bias temperature instability (NBTI) is assessed by studying devices with polycrystalline-Si/SiON as well as deposited metal gate/high-[kappa] and FUSI/high-[kappa] gate stacks. The studies have shown that there is no degradation of intrinsic NBTI behavior due to process-induced strain.

The mobility and dielectric quality of MOSFETs with 1-nm Equivalent Oxide Thickness (EOT) grown on substrates with different crystallographic orientations, (100) and (110), are studied. The results have shown that the high-[kappa] quality is independent of the Si-substrate orientation and is controlled by dielectric and metal gate deposition.

The high-performance strained NMOSFETs featuring metallized (NiSi) source/drain extension (M-SDE) are examined to understand the extrinsic source/drain series resistance ([R.sub.SD]) impacts and identify the next key technology enabler. The results showed that the spacing between metallized extension and gate electrode edge plays an important role in [R.sub.SD] reduction and could significantly affect the electrical characterization of M-SDE NMOSFETs.

The development of a new trench power MOSFET with strained-Si channel that provides lower on-resistance than the conventional trench MOSFET is presented. The graded strained accumulation region that supports the confinement of carriers near the trench sidewalls has improved the field distribution in the mesa structure to provide a better damage immunity during inductive switching.

The design of the compact model of junction current in dynamically depleted silicon-on-insulator (SOI) MOSFETs is reported. The newly developed model is suitable for the unification of surface-potential-based compact partial depletion (PD) and full depletion (FD) SOI MOSFET models.

An electron-beam-evaporated praseodymium oxide layer in a high-oxygen-flow environment during the gate-dielectric-layer formation is used to study the AlGaN/GaN metal-oxide-semiconductor (MOS-HEMTs). The high-performance electron-beam-evaporated [Pr.sub.2][O.sub.3] high-l AlGaN/GaN MOS-HEMTs are found to be suitable for high-volume production due to its in situ insulator and metal-gate deposition in the same chamber.

The biaxial tensile strained Si MOSFETs are used to examine the effects of strain on the gate oxide reliability and also understand their physical origins. The results showed that the subband-structure modulation due to strain strongly impact the gate oxide reliability of MOSFETs, leading to enhanced Si-H bond breaking.

The analytical solutions of Poisson's equation verified with device simulation are used to study the sensitivity of gate-all-around (GAA) nanowire (NW) to process variations compared with multigate devices. The GAA NW has shown better immunity to channel thickness variation than multigate devices due to its inherently superior surrounding gate structure.

The experimental studies on the carrier transport in gate-all-around (GAA) silicon nanowire transistors (SNWTs) are reported. The results obtained demonstrated the potential of the device as an alternative device structure for near-ballistic transport from top-down approach.

An extensive numerical study of simple structured unipolar accumulation-type metal-oxide-semiconductor field - effect transistor (AMOSFET) using silicon nanowires (NWs) is reported. The results have showed that the performance of the high-quality transistor depends on attaining controlled source and drain-region lengths, whose values depend on the contact-barrier height and doping, and a required minimum gate-region length.

The development, analytical expressions of electrostatic potential and charges for newly designed analytic model for the nanowire MOSFETs (NWFETs) with Ge/Si core/shell structure is described. The device physics of the developed model could be used for developing a compact model for the NWFETs with Ge/Si core/shell heterostructure for circuit design and simulation.

The development of a silicon-based nanowire FET (SNWT) compact model for circuit simulation and its applicability for a wide range of SNWT doping concentrations and dimensions is reported. The performance and application of the model in circuit simulation is demonstrated by implementing it in circuit simulators by verilog-A.

An improved channel resistance method using iterative procedure for extraction of effective channel length and source/drain series resistance in ultrashort-channel MOSFETs is described. This method takes into account the degradation in mobility in shorter channel devices and by compensating for the mobility in long channels a more accurate effective channel length and source/drain series resistance is obtained.

The mercury-probe configuration, called the HgFET, is a version of the Pseudo-MOSFET and a recent innovation with the advantage of well-defined source and drain areas. It is highlighted that the HgFET characterization of SOI (silicon-on-insulator) wafers is very sensitive to the surface condition of the Si surface.

The advantages of using elevated S/D formed on oxide shallow trench isolation are studied in detail.Design guideline and potential performance gain with S/D-on-insulator (SDOI) structure is discussed and it is shown that a significant increase in device performance can be achieved by careful optimization of the SDOI structure.

An analysis of the silicon-on-nothing (SON) transistors showed that they operate in full depletion with very low interface coupling coefficient. A new three-interface model that was developed is described.

A new architecture for a vertical MOS transistor that incorporates a dielectric pocket (DP) for suppression of short-channel effects and bulk punch-through, is proposed. The advantages that the DP brings are also outlined.

For high-performance and low-cost 0.15 um CMOS technology, simultaneous doping of n-poly gate as well as p-poly gate using source/drain implantation is proposed. Using the transmission electron microscopy, and high-resolution x-ray diffraction spectroscopy, the degree of active damage by doubled source/drain implantation dose are investigated.

Strained layer Si(sub 0.7)Ge(sub 0.3) pMOSEFTs were fabricated and it exhibited enhanced hole mobility up to 35 percent higher for a SiGe device with 3-nm-thick Si-cap and lower 1/f noise compared to Si surface channel pMOSFETs. The 1/f noise in the investigated devices is dominated by mobility fluctuation noise and found to be lower in the SiGe devices.

The first replacement (Damascene) metal gate pMOSFETs fabricated with Ni/TaN, Co/TaN stacked electrode is presented. The results demonstrates that a low temperature anneal (300 degree) can improve the device performance.

The silicon thickness dependence of low field electron mobility in ultrathin silicon-on-insulator (UT-SOI) MOSFETs operated both in single- and double- gate mode is investigated. The model for phonon scattering was rediscussed and a model for the scattering induced by silicon thickness fluctuations was developed.

A new approach to model nonquasi-static (NQS) effects in a MOSFET in a small-signal situation is presented. The derivation of small-signal model, based on the large-signal model, is also discussed.

A new nonquasi-static (NQS) model for the MOSFET is presented which is derived from physics and only relies on the very basic approximation needed for a charge-based model. In order to derive the model, a popular variational technique named Galerkin's Method is used.

An extensive numerical modeling of double-gate, nanoscale silicon n-metal oxide semiconductor field effect transistors (MOSFETs) with ultrathin intrinsic channels connecting bulk, highly doped electrodes are carried out.

A program to numerically simulate quantum transport in double gate metal oxide semi conductor field effect transistors (MOSFETs) is described. Along with the program, some examples of the use of nanoMOS for 10 nm double gate MOSFETs are presented.

The MOSFET with the superjunction (SJ) structure offering remarkable advantages over the conventional SJ structure is proposed and demonstrated. The high-voltage power semi-SJ MOSFET is very effective for reduction of power dissipation due to low on-resistance and soft recovery body diode.

A new partial silicon-on-insulator (SOI) formation technology and the associated RF LDMOSFET device structure on silicon bulk substrate are described. The technology assists in the reduction of drain/substrate parasitics and leakage current for devices fabricated on bulk substrate.

The fabrication of a fully-depleted (FD) silicon-on-insulator (SOI) CMOSFET on 20-nm-thick silicon-on-insulator (SOI) layer is described. The advanced cobalt salicide technology is used for the fabrication.

Computer simulations of various silicon-on-insulator (SOI) MOSFETs with double and triple-gate structures and gate-all-around devices are described. Result recommend Pi-gate device for future nanometer MOSFET applications.

The hot-carrier degradation of the 1/f -noise behavior of n- and p-MOS transistors under typical bias conditions for analog and RF operation are investigated. The consequences for reliability assurance by measures of circuit design are described.

The effects of wave function penetration into the gate-oxide on modeling of gate capacitance in deep submicron p-MOSFETs on (100) silicon are calculated. Results indicate more pronounced penetration effects in p-MOS devices.

Fabrication of a trench lateral power MOSFET with a trench bottom source contact (TLPM/S) is done and compared with the equivalent TLPM with a trench bottom drain contact (TLPM/D). Due to reduced Miller capacitance, the TLPM/S exhibits excellent switching performance, and is approximately 50% faster than the equivalent TLPM/D.

Non-uniform and steep dopant profiles in poly-gate result in built-in electric field effects and potential drops in the gate region. To overcome the problems, high doped gates with less dopant gradient in the poly-gate can be the most appropriate solution.

The model is based on inelastic trap-assisted tunneling (ITAT) mechanism combined with a semi-empirical direct tunneling current model. The result simulated by the ITAT model shows good agreement with the experimental results.

The model helps to develop a new extraction technique for the recombination lifetime in the silicon film. The model also describes drain current overshoots induced when turning on the transistor gate.

By using nonequilibrium Green's function formalism a fully quantum mechanical simulation of an ultrashort channel is presented. The doping of source and drain plays an important role for ballistic MOSFETs.

Hole tunneling can be used to project the electrical oxide thickness scaling limit of the oxynitride/oxide gate stack dielectrics used in p-MOSFETs. The validity of the model is verified by the excellent agreement between the simulated and experimental results.