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The physical effects that must be included in an accurate model of a silicon-controlled rectifier are discussed and compared with those for bipolar transistors. There are key differences in the modeling of the intrinsic silicon resistances and current gain for the two devices. Proper modeling of the underlying physics results in a compact model that is applicable over a wide range of current levels and is scalable. [ABSTRACT FROM AUTHOR]

A scalable compact model for SCR-based electrostatic discharge (ESD) protection devices is presented. This model captures the effect that layout spacing has on SCR characteristics, such as holding voltage and trigger current. The model also captures both the delayed turn-on of the SCR, which results in large voltage overshoots during fast rise-time ESD events and the charge removal mechanisms that underlie the turn-off transient. Bias and time dependences of SCR on-resistance are captured with a resistance model that accounts for self-heating. [ABSTRACT FROM AUTHOR]

Abstract: A model is presented for external latchup. The effects of spacing, temperature, supply voltage and layout are captured in the model. The model shows a good fit to measurement results from two different technologies, RF-CMOS and SmartMOS. [Copyright &y& Elsevier]

The reliability of very thin gate oxide under electrostatic discharge-like pulse stress is investigated. Time-dependent dielectric break- down of gate oxide with thicknesses ranging from 2.2 to 4.7 nm is characterized down to the nanosecond lime regime. The l/E model best fits the time-to-breakdown data. Self-heating does not need to be incorporated into the time-to-breakdown model. The oxide trap generation rate is a function of the stress pulse-width for nanosecond and microsecond stress pulses. [ABSTRACT FROM AUTHOR]

We present an easy-to-use, simulator-independent compact model of a vertical npn transistor suitable for ESD circuit simulation. In addition to including high-current and breakdown effects, we also model accurately the small-signal off-state impedance of the device using s-parameter measurements, for inclusion in RF circuit simulations. Experimental results are provided for silicon and SiGe npn transistors. [Copyright &y& Elsevier]

Presents information on a study which performed a detailed examination of hot-carrier-induced degradation in metal-oxide-semiconductor field-effect transistors. Experimental procedure; Results and discussion.

Discusses stress-induced leakage current (SILC) as a result of inelastic rather than elastic trap-assisted tunneling. Thickness dependence at high fields; Use of SILC measurements; Leakage current conduction mechanism; Models of SILC; SILC as a scaling limitation.

Presents an analytic model of the direct tunneling current in metal-oxide-semiconductor devices as a function of oxide field. Modeling of the low-field roll-off; Field dependencies of the sheet charge, electron impact frequency on the interface and field probability; Modified approximation used.

The article focuses on the study of the data driven reliability focused on hard disk drives of data centers. It mentions that reliability is a concern in hardware design. It mentions that telemetry and data storage technologies have enabled diagnostic sensor arrays to be embedded in the hardware systems. It mentions that system designers collect sensor data streamed from operational devices.

This work presents a model for multi-finger MOSFETs operating under ESD conditions. It is a distributed model that can reproduce the effect of layout geometry on trigger voltage, on-state resistance, and non-uniform turn-on of device fingers. A three-terminal transmission line pulsing technique enables model parameter extraction. Analysis of measurement data and TCAD simulation reveals that self-heating is not uniform across the device, and this affects the relation between on-state resistance and the number of fingers. With self-heating incorporated, the model correctly reproduces the device I–V curve up to high current levels. [ABSTRACT FROM AUTHOR]

This work advances the application of neural ordinary differential equations (ODEs) to circuit modeling. Prior works primarily utilized the recurrent neural network (RNN), which is a specific type of neural ODE. In this work, the capability of neural ODEs to represent different types of circuits is studied. Stability conditions are presented, both for neural ODEs in a standalone configuration and for neural ODEs with feedback connections, and practical techniques to impose the stability constraints during training are demonstrated. Based on the theoretical and experimental results, this work provides guidance as to when and how an accurate and stable neural ODE circuit model can be generated. [ABSTRACT FROM AUTHOR]

This paper presents a methodology to construct an equivalent circuit model of a packaged integrated circuit mounted on a field-induced charged device model electrostatic discharge tester. Circuit simulation is used to obtain the full-component current and voltage distributions. This paper focuses on predicting overvoltage stress at power domain crossing circuits. [ABSTRACT FROM PUBLISHER]

Radio frequency and broad-band I/O circuit designers may compensate for the capacitance, of electrostatic discharge (ESD) protection elements by designing them into tuned resonators or matched filters, thereby requiring that the protection device capacitance have a high quality factor (Q). In this paper, we explore several ESD protection device options, focusing on improvement in Q. We show that surrounding a grounded-gate nMOS transistor with a deep trench increases its Q, while adding a trigger circuit decreases it. We also show that SiGe diodes are preferred over SiGe n-p--n devices. A detailed analysis of experimental results is provided. [ABSTRACT FROM AUTHOR]

We demonstrate that narrow-band tuned circuits may be used for ESD protection of RF inputs, and a figure of merit for optimization of these circuits is presented. The performance of the ESD-protected RF circuit is dependent on the quality factor of the ESD device, and various protection devices are evaluated in this work. Record-breaking human body model (HBM) protection levels, exceeding 5 kV, have been achieved without significantly degrading the RF performance at 5 GHz. Broadband circuit protection is also addressed. [Copyright &y& Elsevier]

To enable accurate system-level electrostatic discharge (ESD) simulation, this article applies statistical learning to obtain I/O port models of the victim integrated circuits (ICs). A quasi-static I–V model derived using kernel regression can capture the circuit board dependency of the behavior observed at the I/O pin, regardless if there is snapback. The non-parametric kernel model can be reduced to a system-specific parametric model, which has smaller requirements for computing time and memory. In some cases, transient system-level ESD simulation may require the IC model to replicate the dynamic behavior of the nonlinear circuit. A recurrent neural network is demonstrated to be a suitable model in such cases. This article provides a detailed RNN training flow for IC pin modeling, and presents a Verilog-A implementation of the RNN for use with Simulation Program with Integrated Circuit Emphasis (SPICE)-type simulators. [ABSTRACT FROM AUTHOR]

The article reports that The Center for Advanced Electronics through Machine Learning, or CAEML, is an IndustryUniversity Cooperative Research Center (IUCRC) supported by the National Science Foundation. The IUCRC program supports pre-competitive research that is of high interest to industry. CAEML's research mission is to utilize machine learning for the design of optimized microelectronic circuits and systems and to increase the efficiency of electronic design automation.

Presents an electromigration reliability diagnosis tool (iTEM) for complementary metal oxide semiconductor (CMOS) very-large scale integration (VLSI) circuits. Temperature effect on electromigration reliability; Block diagram of iTEM; Results of electrothermal timing simulation.

Reliability is an important consideration during semiconductor technology development, which ensures that the performances of devices, circuits, and systems are maintained over a specified period of time, leading to successful products. Device reliability is at the core of overall product reliability, which continues to remain an important area of research and has attracted the attention of IEEE Transactions on Electron Devices (T-ED) authors and readers throughout the years. Device reliability can be classified into two broad areas: gradual drift of device performance over time or sudden failure, and both are of importance for logic, memory, RF, and power devices. Different aspects of device reliability are usually reported, such as the development of electrical or physical characterization methods, investigation and modeling of a particular phenomenon, impact of material and processes on reliability, and development of reliability tolerant technologies. [ABSTRACT FROM AUTHOR]

A practical approach for the compact modeling of electrostatic discharge (ESD) protection devices, using the behavioral language Verilog-A, is presented. Models of the NMOS transistor, the vertical n-p-n transistor, the diode, and the resistor have been developed, suitable for circuit-level simulation. Large-signal and small-signal models are provided for transient and alternating current (ac) simulation, respectively. A self-heating model is included for accurate simulation of the device ON-resistance under transient high-current conditions. [ABSTRACT FROM AUTHOR]

This paper presents a methodology for the efficient modeling of substrate noise coupling. A closed-form Green's function for nonuniformly doped substrates is employed with the correct singular characteristics. A novel global surface impedance matrix scheme is introduced to efficiently model nonuniformly doped wells, channel stop implants, and buried layers. Layout, device, and netlist extractors are developed so as to integrate our boundary element method (BEM) solver with commercial layout and circuit simulation tools. [ABSTRACT FROM AUTHOR]