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In this paper, architecture of a Real-Time Cellular Neural Network (CNN) Processor (RTCNNP-v2) is given and the implementation results are discussed. The proposed architecture has a fully pipelined structure, capable of processing full-HD 1080p@60 (1920 \times 1080 resolution at 60 Hz frame rate, 124.4 MHz visible pixel rate) video streams, which is implemented on both high-end and low-cost FPGA devices, Altera Stratix IV GX 230, and Cyclone III C 25, respectively. Many features of the architecture are designed to be either pre-synthesis configurable or runtime programmable, which makes the processor extremely flexible, reusable, scalable, and practical. [ABSTRACT FROM AUTHOR]

This paper presents a tracking and detection engine for 2 \times 2 spatial-multiplexing multiple-input multiple-output orthogonal frequency division multiplexing (MIMO-OFDM) systems under highly time-selective fading channels. A recursive least-squares (RLS) adaptive algorithm is adopted to track time-varying channel frequency response. Besides, iterative MIMO signal detection is used, including inter-carrier interference (ICI) cancellation, to enhance system performance. To avoid error propagation in the decision-directed RLS adaptation, ordered-selection mechanism and signal strength criteria are incorporated so that more reliable detection results can be selected for calculating channel statistics. The scheduling strategies and hardware reduction techniques are proposed for implementation of the computation-intensive RLS adaptive algorithm and ICI cancellation. This baseband processor has been fabricated in 90 nm CMOS technology and has 1023K gates. At the nominal operating frequency of 15.36 MHz, it provides throughput of 76.8 Mbps with 64-QAM up to 240 Km/hr. For constellation of 16-QAM and QPSK, the mobility of 360 Km/hr is supported. The power consumption is 11.8 mW at 0.7 V supply voltage. The operating frequency can be raised up to 103 MHz to offer 515 Mbps throughput with power consumption of 202 mW at 1.2V. [ABSTRACT FROM AUTHOR]

This paper presents a novel multi-standard digital low-IF receiver, which provides low-power low-complexity, flexible and robust performance for short distance communication applications. Over the various incoming data rates and carrier frequencies, the corresponding symbol timing is recovered by the \mmb\Sigma\Delta modulated frequency divider from fractional-N synthesizer, and the carrier frequency offset is calibrated by direct digital synthesizer generated intermediate frequency. The proposed digital receiver is fully integrated with 130 nm CMOS technology, occupying 0.83 mm^2 area with 4.5 mW. Through the verification in an FPGA, the measurement results show a great potential in flexible and cost oriented applications. [ABSTRACT FROM AUTHOR]

This paper presents a rotational phase frequency detector (RPFD) for reference-less clock and data recovery circuit (CDR). The proposed RPFD changes the bang-bang phase detector (BBPD) characteristic from a bidirectional phase detection to an unilateral phase detection for capturing clock frequency. The phase-and-frequency lock loop (PFLL) locks the clock frequency and the clock phase alternatively. The single-loop CDR replaces the dual-loop CDR so as to eliminate the noise contribution from the frequency lock loop (FLL). This proposed design is fabricated in TSMC mixed-signal 1P9M 90-nm standard CMOS process with overall die size of 0.71-mm^2. With input 10-Gb/s data of a 2^31-1 PRBS, the CDR tracks free running clock over the capture range of 1.48 GHz and locks in the acquisition time of 20 \mus. At the same time, the peak-to-peak jitters show only 5.0 ps in the recovered clock and exhibits 15.11 ps in the recovered data. The measured chip consumes 92 mW with 1.0-V supply voltage. [ABSTRACT FROM PUBLISHER]

This paper describes a delta-sigma modulator with a new feedback topology in combination with the recently proposed two-step residue-discharging quantizer. Instead of using a single digital-to-analog converter (DAC) with a large number of levels, a mixed-mode DAC is presented which takes advantage of the two-step nature of the quantizer. Hence, only one feedback DAC, which is associated with the coarse bits (MSBs), is required for the modulator and LSBs are fed back as a time-modulated pulse (TMP). Therefore, high quantization resolution is achieved without increasing the front-end DAC complexity. Additionally, a new data weighted averaging (DWA) technique is proposed which not only suppresses the mismatch between the unit elements of the MSB DAC, but also aims to average out the gain error between the MSB and LSB DACs. Therefore, the possible quantization noise leakage is drastically reduced. Detailed mathematical models as well as comprehensive simulation results are provided to prove the efficiency of the proposed structure. [ABSTRACT FROM AUTHOR]

This paper presents a bit reversal circuit for continuous-flow parallel pipelined FFT processors. In addition to two flexible commutators, the circuit consists of two memory groups, where each group has P memory banks. For the consideration of achieving both low delay time and area complexity, a novel write/read scheduling mechanism is devised, so that FFT outputs can be stored in those memory banks in an optimized way. The proposed scheduling mechanism can write the current successively generated FFT output data samples to the locations without any delay right after they are successively released by the previous symbol. Therefore, total memory space of only N data samples is enough for continuous-flow FFT operations. Since read operation is not overlapped with write operation during the entire period, only single-port memory is required, which leads to great area reduction. The proposed bit-reversal circuit architecture can generate natural-order FFT output and support variable power-of-2 FFT lengths. [ABSTRACT FROM AUTHOR]

The high leakage power due to process nodes scaling down has been one of the critical issues in CMOS circuits, especially the sleep power critical systems. The conventional retention CMOS register based approaches cannot fully address the high standby energy issue in long time standby systems. The recent non-volatile Flip-Flop (nvFF) based approaches may achieve zero sleep power consumption, but still face the challenges of high saving power and area overhead, and low data reliability. This paper presents a new resistive Non-Volatile Memory (NVM) based circuit architecture with zero leakage power dissipation. It stores the states of the registers in the localized spin-torque-transfer magnetic random access memory (STT-MRAM) array through scan chains, which has reduced by more than 20% sleep energy than conventional nvFF schemes, and saved by more than 99.8% sleep energy compared to the retention CMOS register based approaches when the sleep time is longer than 1 s. Moreover, the proposed pipelined quad-phase saving scheme maximizes the saving speed, while reduces the peak saving current. [ABSTRACT FROM AUTHOR]

A 14 bit 500 MS/s current-steering digital-to-analog converter (DAC) was designed and fabricated in 0.13 \mum CMOS process. For traditional wide-band current-steering DACs, the spurious-free dynamic range (SFDR) is limited by nonlinear distortions from the code-dependent load variations and the code-dependent switching glitches. They are analyzed in this paper and mitigated by the proposed complementary switched current sources (CSCS) and time-relaxed interleaving digital- random-return-to-zero (TRI-DRRZ), respectively. The proposed techniques are fabricated and measured, with an SFDR of 84.8 dB at 11 MHz signal frequency and 73.5 dB at 244 MHz. The DAC consumes 299 mW from a mixed power supply of 1.2 V and 2.5 V with an active area of 1.85\times 0.65\ mm^2. [ABSTRACT FROM AUTHOR]

This paper presents a new ADC architecture called partially active flash ADC. A 10 GS/s 6 b four-way time-interleaved ADC prototype in 65 nm CMOS demonstrated that this new ADC architecture offers better power efficiency than traditional ADC architectures in the \geq10 GS/s speed range. Various considerations towards high-speed ADC designs are discussed including a proposed source-follower based boot-strap track-and-hold circuit to reduce input kickback and improve the ADC bandwidth. Also discussed is the generation and skew calibration of the four-phase clocks for the interleaved channels to improve the ADC effective resolution at high input frequencies. By deriving the four-phase clocks from a Nyquist frequency input clock through pass gates, accurate timing skew calibration is achieved through a simple duty-cycle correction. Measured SNDR is 34.3 dB at low input frequencies and 32.0 dB at the Nyquist input frequency. The ADC including the input clock buffer consumes 83 mW with a FOM of 197 fJ/cs. [ABSTRACT FROM AUTHOR]

This paper describes a fully-integrated 77-GHz ultra-wideband pseudo-random noise (PRN) radar transceiver in a Silicon-Germanium technology. The transceiver is equipped with a programmable pseudo-random binary sequence (PRBS) generator, which is realized in a current-mode logic topology and can be operated with a clock rate of up to 4.25 GHz to enable a range resolution of 3.5 cm. The signal generation unit is simplified by including a frequency multiplier to create a 76.5-GHz carrier signal from a single 4.25-GHz input, that is also used as a clock for the PRBS generator. The transceiver achieves a phase noise of -105.3 dBc/Hz at 1-MHz offset frequency, a transmit output power of 6.2 dBm, a receive gain of 24 dB and an input-referred 1-dB compression point of -14 dBm. Track&hold circuits included in the receive path allow the use of a sub-sampling technique to reduce the IF data rate down to 1 MHz. Radar measurements with two PRN transceivers with different primitive polynomials were done concurrently to show a fundamental function of the programmable PRBS generator. Radar measurements with the PRN and the frequency-modulated continuous-wave (FMCW) principles show comparable results and the PRN radar proves to be a real alternative to the FMCW radar. [ABSTRACT FROM AUTHOR]

This paper describes a 10-Gb/s clock-and-data recovery (CDR) with a background optimum loop-bandwidth calibrator. The proposed CDR automatically achieves the minimum-mean-square error between jittery input data and the recovered clock signal by adjusting the bandwidth of a CDR using Kalman filtering theory. A testchip is fabricated in a 0.11 \mum CMOS process and the adaptive optimum loop-bandwidth calibrator is implemented via an off-chip micro controller unit. The testchip recovers clock and data with a bit error rate of less than 10^-13 while consuming 82 mW at 10-Gb/s. [ABSTRACT FROM AUTHOR]

A battery-powered aerial microrobotic System-on-Chip (SoC) has stringent weight and power budgets, which requires fully integrated solutions for both clock generation and voltage regulation. Supply-noise resilience is important yet challenging for such SoC systems due to a non-constant battery discharge profile and load current variability. This paper proposes an adaptive-frequency clocking scheme that can tolerate supply noise and improve performance when implemented with an integrated voltage regulator (IVR). Measurements from a ‘brain’ SoC, implemented in 40 nm CMOS, demonstrate 2\times performance improvement with adaptive-frequency clocking over conventional fixed-frequency clocking. Combining adaptive-frequency clocking with open-loop IVR extends error-free operation to a wider battery voltage range (2.8 to 3.8 V) with higher average performance. [ABSTRACT FROM AUTHOR]

A 10.4-16-Gb/s reference-less and baud-rate clock and data recovery (CDR) circuit with a one-tap speculative decision feedback equalizer (DFE) is presented. The quarter-rate CDR circuit uses a pattern-based phase detector (PD) and the proposed FD. This wide-range FD is composed of a coarse FD and a fine FD (FFD) which share the same front-end comparators with the PD and the DFE. Thus, no extra comparators are required. In addition, by monitoring the drift direction of five samples on the five-bit data patterns, the FFD performs an error-free operation within a frequency error of 7.7%. Therefore, the CDR has a robust FD-to-PD transition. By using the proposed FD, this CDR circuit not only achieves a wide frequency capture range of 43%, but also has a short frequency settling time of $680~\mu \text{s}$. This CDR circuit is fabricated in 40-nm CMOS technology and occupies an active area of 0.1004 mm2. The total power of the receiver is 39.9mW at 16 Gb/s, and the calculated energy efficiency is 2.49pJ/b. [ABSTRACT FROM AUTHOR]

In this work, we report the portable NMR system which provides solutions to the existing problems in miniature CMOS NMR systems. First, a higher IF of 50 kHz is achieved by exploiting separate frequencies for sample excitation and LO, thereby having higher immunity to 1/f noise. The proposed phase detector circuit aligns the experiment trigger with the constant phase difference between two frequencies. It maintains the constant RX output phase in every experiment, allowing the direct signal averaging without extra phase correction. In addition, 40X faster RX recovery with RX BW switching enables the signal acquisition with the dead time of 10 $\mu \text{s}$. Fast settling improves the acquisition sensitivity. Lastly, a frequency calibration method based on signal peak detection is proposed. Combining the techniques with the fully integrated NMR transceivers, the system demonstrates the NMR experiments to measure the decaying time constant of less than 100 $\mu \text{s}$. Furthermore, NMR diffusion experiments are performed with the echo spacing of $0.2\sim 8$ ms. [ABSTRACT FROM AUTHOR]

This paper presents a power and area efficient approach to embed a continuous-time linear equalizer (CTLE) within a clock and data recovery (CDR) circuit implemented in 65-nm CMOS. The merged equalizer/CDR circuit achieves full-rate operation up to 28 Gb/s while drawing 104 mA from a 1-V supply and occupying 0.33 mm2. Current-mode-logic (CML) circuits with shunt peaking loads using customized differential pair layout are used to maximize circuit bandwidth. To minimize the area penalty, differential stacked spiral inductors (DSSIs) are employed extensively. A novel and practical methodology is introduced for designing DSSIs based on single-layer inductors provided in foundry process design kits (PDK). The DSSI design increases the inductance density by over 3 times and the self-resonance frequency by 20% compared to standard single-layer inductors in the PDK. The measured BER of the recovered data by the CDR is less than 10-12 at 27 Gb/s for 211-1 400 mV PP pseudo-random binary sequence (PRBS) as input data. The measured rms jitter of the recovered clock and data are 1.0 and 2.6 ps, respectively. The CDR is able to lock to inputs ranging from 26 to 28 Gb/s with 29-1 PRBS pattern. Measurement results show that with the equalizer enabled, the CDR can recover a 26-Gb/s 27-1 PRBS data with BER ≤ 10-12 after a channel with 9-dB loss at 13 GHz. [ABSTRACT FROM AUTHOR]

This paper embeds a “phase-reset” scheme into a bang-bang clock and data recovery (CDR) to periodically realign the clock phase to the data rising edge using a gated-VCO. This reduces both the CDR lock time and bit errors during pull-in, while increasing the CDR capture range. The CDR is fabricated in 65-nm CMOS, operates at 8-11 Gb/s, and demonstrates a 9 × increase in capture range. The CDR consumes 84 mW during lock, and 48 mW in steady state. [ABSTRACT FROM AUTHOR]

Energy storage technology is becoming more and more important in today's environmentally conscious society. In the conventional method of directly charging a capacitor under a constant power supply voltage, the amount of energy dissipation is the same as the energy stored in the capacitor. In this paper, we propose the stepwise charging of a capacitor by consecutively changing the duty ratio of the DC-DC down converter. In N step charging, the energy dissipation is reduced to one Nth when compared with the conventional direct charging. The reduction of the dissipated energy is verified by SPICE simulations and by breadboard experiments, through which an energy reduction of one fourth and one eighth is confirmed from the measured power supply currents in four and eight step charging, respectively. [ABSTRACT FROM PUBLISHER]

To meet the evolving data rate requirements of emerging wireless communication technologies, many parallel architectures have been proposed to implement high throughput turbo decoders. However, concurrent memory reading/writing in parallel turbo decoding architectures leads to severe memory conflict problem, which has become a major bottleneck for high throughput turbo decoders. In this paper, we propose a flexible and efficient VLSI architecture to solve the memory conflict problem for highly parallel turbo decoders targeting multi-standard 3G/4G wireless communication systems. To demonstrate the effectiveness of the proposed parallel interleaver architecture, we implemented an HSPA+/LTE/LTE-Advanced multi-standard turbo decoder with a 45 nm CMOS technology. The implemented turbo decoder consists of 16 Radix-4 MAP decoder cores, and the chip core area is 2.43 mm^2. When clocked at 600 MHz, this turbo decoder can achieve a maximum decoding throughput of 826 Mbps in the HSPA+ mode and 1.67 Gbps in the LTE/LTE-Advanced mode, exceeding the peak data rate requirements for both standards. [ABSTRACT FROM AUTHOR]

Clock gating is very useful for reducing the power consumed by digital systems. Three gating methods are known. The most popular is synthesis-based, deriving clock enabling signals based on the logic of the underlying system. It unfortunately leaves the majority of the clock pulses driving the flip-flops (FFs) redundant. A data-driven method stops most of those and yields higher power savings, but its implementation is complex and application dependent. A third method called auto-gated FFs (AGFF) is simple but yields relatively small power savings. This paper presents a novel method called Look-Ahead Clock Gating (LACG), which combines all the three. LACG computes the clock enabling signals of each FF one cycle ahead of time, based on the present cycle data of those FFs on which it depends. It avoids the tight timing constraints of AGFF and data-driven by allotting a full clock cycle for the computation of the enabling signals and their propagation. A closed-form model characterizing the power saving per FF is presented. It is based on data-to-clock toggling probabilities, capacitance parameters and FFs' fan-in. The model implies a breakeven curve, dividing the FFs space into two regions of positive and negative gating return on investment. While the majority of the FFs fall in the positive region and hence should be gated, those falling in the negative region should not. Experimentation on industry-scale data showed 22.6% reduction of the clock power, translated to 12.5% power reduction of the entire system. [ABSTRACT FROM AUTHOR]

Previous research results showed that UHF passive CMOS RFID tags had difficulty to achieve sensitivity less than -20~dBm. This paper presents a dual-channel 15-bit UHF passive CMOS RFID tag prototype that can work at sensitivity lower than -20~dBm. The proposed tag chip harvests energy and backscatters uplink data at 866.4-MHz (for ETSI) or 925-MHz (for FCC) channel and receives downlink data at 433-MHz channel. Consequently, the downlink data transmission does not interrupt our tag from harvesting RF energy. To use the harvested energy efficiently, we design a tag chip that includes neither a regulator nor a VCO such that the harvested energy is completely used in receiving, processing, and backscattering data. Without a regulator, our tag uses as few active analog circuits as possible in the receiver front-end. Instead, our tag uses a novel digital circuit to decode the received data. Without a VCO, the design of our tag can extract the required clock signal from the downlink data. Measurement result shows that the sensitivity of the proposed passive tag chip can reach down to -21.2~dBm. Such result corresponds to a 19.6-m reader-to-tag distance under 36-dBm EIRP and 0.4-dBi tag antenna gain. The chip was fabricated in TSMC 0.18-\mum CMOS process. The die area is 0.958 mm \times 0.931mm. [ABSTRACT FROM AUTHOR]

This paper discusses a supply noise sensitivity problem of the gated ring oscillator (GRO) based time-to-digital converter (TDC) in all-digital phase-locked loops (ADPLLs) and presents a power supply rejection ratio (PSRR) enhancing method. A replica supply noise monitoring circuit is designed to track supply noise and enable feed-forward error cancellation for high PSRR TDC design. A prototype ADPLL with the proposed self-monitored TDC is implemented in 65 nm CMOS to evaluate the supply noise sensitivity of the TDC in the frequency domain. Intermodulation spur generation problem due to noise coupling is also addressed and demonstrated in hardware. The experimental results show that the proposed method effectively suppresses supply noise induced spurs at the output of the ADPLL, achieving the PSRR of 27 dB and 38 dB with 1 MHz supply noise and 5 MHz intermodulation noise respectively. [ABSTRACT FROM AUTHOR]

This paper presents the Band-Reject Nested-PLL (BRN-PLL) scheme that simultaneously improves filtering of a noisy input signal and relaxes the requirements for the loop bandwidth. As the architecture employs a modified PLL as a divider of another PLL, a stability analysis is presented to demonstrate suitable operation. The BRN-PLL close-to-carrier output noise is dominated by the PFD/CP of the inner PLL and the far-from-carrier output noise is dominated by the LO of the outer PLL. The PFD/CP noise can be reduced by approximately 20 dB when the output is disconnected from the VCO during idle states, and a low noise floor is achieved using a passively biased double-switching pair LC VCO. Additionally, to maintain lower integrated phase noise, the proposed scheme uses a high-Q MEMS-based VCO to effectively smoothen the transition of the response between the two dominant noise sources. Absolute figures equal to -105 dBc/Hz at 1 kHz and -155 dBc/Hz at 10 MHz are measured from a 104 MHz clock-cleaner. [ABSTRACT FROM PUBLISHER]

This paper extends the analysis of the effectiveness of Leakage Power Analysis (LPA) attacks to cryptographic VLSI circuits on which circuit level countermeasures against Differential Power Analysis (DPA) are adopted. Security metrics used for assessing the DPA-resistance of crypto core implementations, such as the minimum number to disclosure (MTD) and the asymptotic correlation coefficient, have been extended to the case of LPA. The LPA-resistance has been evaluated in terms of MTD as a function of the on chip noise. Noise variances up to 10000 times greater than the signal variance have been taken into account and LPA attacks have been successfully executed for all the logic styles under analysis using less than 100000 measurements. Moreover the role of process variations has been investigated through extensive Monte Carlo simulations in order to evaluate their impact on the leakage model for the logic styles under analysis. Results show that LPA attacks can be successfully carried out on the different anti-DPA logic styles even in presence of process variations. To the best of our knowledge, this work proves for the first time the effectiveness of LPA attacks in a real scenario where on chip noise and process variations are taken into account. [ABSTRACT FROM AUTHOR]

A single-cycle tree-based 64-bit binary comparator with constant-delay (CD) logic realized in a 65-nm, 1-V CMOS process is presented in this paper. Unlike dynamic logic yet domino-compatible, CD logic predischarges the output to logic “0” and conditionally makes a transition to logic “1” through the critical-path CLK PMOS transistors for an NMOS transistor network. The constant delay (regardless of the fan-in) feature makes it up to 2\times faster than a dynamic logic gate during the D-Q mode for a complex logic such as a two-bit binary comparator. The proposed comparator's architecture is divided into two stages, where the first stage adapts a novel tree comparator structure specifically designed for static logic to achieve low-power consumption and the second stage utilizes CD logic to realize high performance without sacrificing the overall energy efficiency. At 1-V supply, the proposed comparator's measured delay is 167 ps, and has an average power and a leakage power of 2.34 mW and 0.06 mW, respectively. At 0.3-pJ iso-energy or 250-ps iso-delay budget, the proposed comparator with CD logic is 20% faster or 17% more energy-efficient compared to a comparator implemented with just the static logic. [ABSTRACT FROM AUTHOR]

This paper presents a novel approach to develop pipelined fast Fourier transform (FFT) architectures for real-valued signals. The proposed methodology is based on modifying the flow graph of the FFT algorithm such that it has both real and complex datapaths. The imaginary parts of the computations replace the redundant operations in the modified flow graph. New butterfly structures are designed to handle the hybrid datapaths. The proposed hybrid datapath leads to a general approach which can be extended to all radix-2^n based FFT algorithms. Further, architectures with arbitrary level of parallelism can be derived using the folding methodology. Novel 2-parallel and 4-parallel architectures are presented for radix-2^3 and radix-2^4 algorithms. The proposed architectures maximize the utilization of hardware components with no redundant computations. The proposed radix-2^3 and radix-2^4 architectures lead to low hardware complexity with respect to adders and delays. The N-point 4-parallel radix-2^4 architecture requires 2(log16N-1) complex multipliers, 2log2N real adders and N complex delay elements. [ABSTRACT FROM PUBLISHER]

This paper presents a temperature sensor based on a frequency-to-digital converter with digitally controlled process compensation. The proposed temperature sensor utilizes ring oscillators to generate a temperature dependent frequency. The adjusted linear frequency difference slope is used to improve the linearity of the temperature sensor and to compensate for process variations. Furthermore, an additional process compensation scheme is proposed to enhance the accuracy under one point calibration. With one point calibration, the resolution of the temperature sensor is 0.18^\circC/LSB and the maximum inaccuracy of 20 measured samples is less than \pm 1.5^\circC over a temperature range of 0^\circC\sim \ 110^\circC. The entire block occupies 0.008 \ mm^2 in 65 nm CMOS and consumes 500 \muW at a conversion rate of 469 kS/s. [ABSTRACT FROM PUBLISHER]

This paper presents a novel method to perform inner product computation based on the distributed arithmetic principles. The input data are represented in the residue domain and are encoded using the thermometer code format while the output data are encoded in the one-hot code format. Compared to the conventional distributed arithmetic based system using binary coded format to represent the residues, the proposed system using the thermometer code encoded residues provides a simple means to perform the modular inner products computation due to the absence of the 2^n modulo operation encountered in conventional binary code encoded system. In addition, the modulo adder used in the proposed system can be implemented using simple shifter based circuit utilizing one-hot code format. As there is no carry propagation involved in the addition using one-hot code, while the modulo operation can be performed automatically during the addition process, the operating speed of the one-hot code based modulo adder is much superior compared to the conventional binary code based modulo adder. As inner product is used extensively in FIR filter design, SPICE simulation results for an FIR filter implemented using the proposed system is also presented to demonstrate the validity of the proposed scheme. [ABSTRACT FROM PUBLISHER]

In this work, the design methodology of the relaxation oscillator with the post-processing trimming option for frequency and temperature coefficient is presented. A novel oscillator core is introduced, which ensures good control linearity and insensitivity to CMOS variations of the output frequency as a prerequisite for frequency and temperature calibration. The proposed oscillator operates at 2 MHz and consumes typically about $I_{DD}=97.8\,\,\mu \text{A}$ at the nominal temperature of 42.5°C and nominal supply voltage of $V_{DD}=1.8$ V. The oscillator is verified experimentally with 10 samples manufactured in 180 nm CMOS process, each covering an area of 0.075 mm2. The frequency and temperature calibration was performed based on the two-point temperature measurements, resulting in a significant improvement in frequency stability. The temperature calibrated oscillator has a temperature variation ±0.30% in the temperature range from −40°C to 125°C, and the variation with the power supply ±0.07% in the supply range from 1.62 V to 1.98 V. [ABSTRACT FROM AUTHOR]

A double-conversion, noise-cancelling receiver architecture is presented that consists of a double-layer mixer-first branch and two quadrature-modulated LNTA branches. The two layers of passive mixing in the mixer-first branch up-convert the low-pass, baseband impedance and create concurrent, narrowband impedance matching at (FLO ± FIF), as well as concurrently receive signals around these two RF carriers while rejecting spurious responses without using any IF filters. To improve the noise performance, quadrature-modulated LNTA branches are incorporated to allow frequency-translational, noise cancellation for better receiver sensitivity. Double conversion is achieved in the LNTA branches by periodically varying the LNTA transconductance and current-mode, passive mixing. A generalized, linear time-varying (LTV) analysis of the receiver is presented and verified with behavioral-model simulation results. [ABSTRACT FROM AUTHOR]

Incremental delta-sigma data converters are useful in applications where one ADC is needed to digitize multiple channels. They can be realized using single- or multi-bit feedback. In both cases, the use of FIR feedback is beneficial in terms of improving the modulator’s linearity, reducing the quantizer’s complexity, and mitigating the effects of clock jitter (in a continuous-time realization). In the incremental mode, however, the maximum stable amplitude of the ADC is severely impacted by FIR feedback. The reasons behind this are examined, and techniques that mitigate this problem are given. Circuit simulations of an example fourth-order single-bit incremental modulator with an eight-tap FIR DAC are given to illustrate the efficacy of the theory. [ABSTRACT FROM AUTHOR]

In this article, we introduce a fractional-N all-digital phase-locked loop (ADPLL) architecture based on a single LC-tank, featuring an ultra-wide tuning range (TR) and optimized for ultra-low area in 10-nm FinFET CMOS. Underpinned by excellent switches in the FinFET technology, a high turn-on/off capacitance ratio of LC-tank switched capacitors, in addition to an adjustable magnetic coupling technique, yields almost an octave TR from 10.8 to 19.3GHz. A new method to compensate for the tracking-bank resolution can maintain its quantization noise level over this wide TR. A new scheme is adopted to overcome the metastability resolution problem in a fractional-N ADPLL operation. A low-complexity TDC gain estimator reduces the digital core area by progressive averaging and time-division multiplexing. Among the published fractional-N PLLs with an area smaller than 0.1mm2, this work achieves an rms jitter of 725fs in an internal fractional-N mode of ADPLL’s phase detector (2.7–4.825GHz) yielding the best overall jitter figure-of-merit (FOM) of −232dB. This topology features small area (0.034mm2), wide TR (56.5%) and good supply noise rejection (1.8%/V), resulting in FOMs with normalized TR (FOMT) of −247dB, and normalized TR and area (FOMTA) of −262dB. [ABSTRACT FROM AUTHOR]

Dynamic power is a major source of power dissipation for high speed designs. Domain isolation methodology is a recently-proposed technique for reducing dynamic power based on controlling the evaluation phase of dynamic logic (toggling control). This work demonstrates some design issues in the domain isolation methodology and explains why it is inefficient with pipelined systems. We propose fixes for its identified issues, which enables using the toggling control with pipelined systems in a more efficient way. A novel flow named “Power Reduction Flow” is proposed for reducing dynamic power of digital circuits. Our flow uses novel design analytical methods, novel “Dynamic Logic Modifier Flow”, and novel “Dynmic Logic Area Validation Flow” for reducing dynamic power with conditionally improving performance. The new design analytical methods are based on probability theory, SystemVerilog covergroups, and digital circuit modeling. A new event type perspective is also proposed to analyze designs to reduce dynamic power in them. Experimental results using TSMC 65 nm and low supply voltages show up to 59% power reduction compared to the original traditional techniques with improving circuit’s performance by 3× of its original maximum operating frequency at the cost of an extra 12.3% increase in area. [ABSTRACT FROM AUTHOR]

State-of-the-art TDCs can have a precision close to one picosecond, for which reason clock instability is starting to be one of the most significant factor limiting the precision. This paper provides methods to estimate clock jitter induced error by phase noise PSD measurements. Due to the different noise processes of the power-law model, convergence problems might restrict the time domain conversion of clock instabilities. Since time interval measurement corresponds to measuring the first difference of phase error, the convergence problems cannot be completely avoided as is usually done when characterizing frequency instabilities in time domain by measuring the 2nd differences of the phase error. This issue is addressed by taking into account the finite observation window of the phase error. Also a simple PSD measurement technique is introduced to provide an estimate of the jitter due to noise floor with an unknown bandwidth. Spurious tones in the phase noise PSD are also shown to have a significant impact on the precision of a TDC. The results are confirmed by several measurements done with a time-to-digital converter having a 1-ps precision. [ABSTRACT FROM PUBLISHER]

In typical direct radio frequency (RF) sampling receivers, the sample clock jitter results in SNR degradation on received signals that increases log linearly with RF signal frequency. De-jittering received signals is computationally expensive, especially for wideband communications signals, because the induced jitter on received signals varies as a function of RF signal frequency. This paper considers a reconfigurable direct RF receiver (RDRFR) that has a stair-step jitter pattern as a function of RF signal frequency. The RDRFR uses a two-stage sampling circuit. In the first stage, the RF input is bandpass filtered and pulse sampled without quantizing the signal. The discrete-time analog signal is then interpolated with a continuous time low-pass filter, then sampled and quantized by a traditional analog-to-digital converter. With this two-stage sampling circuit, the induced signal jitter from the RF sampling is identical for all in-band signals and is the same to within an integer scale factor for all signals, in-band or out-of-band. This key circuit property means that it is possible to remove jitter with very low computational complexity in the RDRFR. Furthermore, this result can be exploited to improve system performance with non-ideal anti-alias filters by identifying non-desired signals caused by out-of-band leakage. [ABSTRACT FROM PUBLISHER]

In this paper we present a fixed window level crossing sampling analog to digital convertor for bio-potential recording sensors. This is the first proposed and fully implemented fixed window level crossing ADC without local DACs and clocks. The circuit is designed to reduce data size, power, and silicon area in future wireless neurophysiological sensor systems. We built a testing system to measure bio-potential signals and used it to evaluate the performance of the circuit. The bio-potential amplifier offers a gain of 53 dB within a bandwidth of 200 Hz–20 kHz. The input-referred rms noise is 2.8 \muV. In the asynchronous level crossing ADC, the minimum delta resolution is 4 mV. The input signal frequency of the ADC is up to 5 kHz. The system was fabricated using the AMI 0.5 \mum CMOS process. The chip size is 1.5 mm by 1.5 mm. The power consumption of the 4-channel system from a 3.3 V supply is 118.8 \muW in the static state and 501.6 \muW with a 240 kS/s sampling rate. The conversion efficiency is 1.6 nJ/conversion. [ABSTRACT FROM PUBLISHER]

Flexible and reconfigurable architectures have gained wide popularity in the communications field. In particular, reconfigurable architectures for the physical layer are an attractive solution not only to switch among different coding modes but also to achieve interoperability. This work concentrates on the design of a reconfigurable architecture for both turbo and LDPC codes decoding. The novel contributions of this paper are: i) tackling the reconfiguration issue introducing a formal and systematic treatment that, to the best of our knowledge, was not previously addressed and ii) proposing a reconfigurable NoC-based turbo/LDPC decoder architecture and showing that wide flexibility can be achieved with a small complexity overhead. Obtained results show that dynamic switching between most of considered communication standards is possible without pausing the decoding activity. Moreover, post-layout results show that tailoring the proposed architecture to the WiMAX standard leads to an area occupation of 2.75 mm^2 and a power consumption of 101.5 mW in the worst case. [ABSTRACT FROM PUBLISHER]

In this paper, we show the relationship between the pull-in range of a linear phase-locked loop (PLL) and the current mismatch of the charge pump that controls the frequency of the oscillator in the PLL. We evaluate the pull-in range of the PLL based on a nonlinear behavioral model of the pull-in process with three types of phase detectors. We introduce the mismatch error to the charge pump current in the PLL and study the impact of this error on the pull-in range. We also apply the mismatch error to a nonlinear differential equation that describes the loop dynamics of the PLL and calculate the pull-in range under this mismatch condition. We validate the limitations of the pull-in range due to the current mismatch by a numerical simulation with MATLAB. [ABSTRACT FROM PUBLISHER]

This paper presents a novel die-to-die clock synchronization method that is independent of the inter-die wire delay. Through a 2-Phase All-Digital Delay Locked Loop (2P-DLL) and a Dual Locking Mechanism (DLM), this method can be used to maintain a global clock signal between two dies in a 3-D IC, and thereby enabling the synchronous 3-D IC design methodology. Unlike previous designs, ours does not need to replicate the delay of the inter-die clock wire. This property can make our scheme more adaptive to various 3-D technologies and more robust to PVT variation. Such a method has several other benefits. For example, it can accommodate the ever-increasing process variation easily through its silicon tracking ability. Simulation results indicate that it can support clock signals running up to 2.8 GHz. Silicon measurements of a test chip in a 90 nm CMOS technology show that the phase error can be locked constantly to less than 9.6 ps at a clock frequency of 600 MHz, with a peak-to-peak jitter of 9.778 ps and a power consumption of only 1.8 mW. [ABSTRACT FROM PUBLISHER]

In this paper, we present a reconfigurable SIMT multi-core processor with a shared memory for mobile ray tracing. The proposed processor addresses two issues of SIMT architecture: branch divergence of concurrently executed threads and contention in a shared memory. Performance degradation due to the branch divergence is reduced by dividing a wide SIMT datapath into several narrow SIMT cores that execute independent threads asynchronously. The contention in a shared memory caused by the multiple SIMT cores is alleviated by introducing a new time-division multiplexing (TDM) scheme using multi-phase clocks. The SIMT cores send their requests to a shared memory sequentially not concurrently by synchronizing the SIMT cores with multi-phase clocks to hide arbitration delays. The processor achieves the same datapath utilization as 4-wide SIMT which has been widely used by CPU-based ray tracers while its area remains 68% of the 4-wide SIMT. As a result, the performance normalized to area is improved by 26% compared to previous work with negligible overheads (2.6% for area and 1% for power consumption). The chip was fabricated in 90 nm CMOS technology, and it contains 2.3 M logic gates and 19.3 KB SRAM. It consumes 221 mW at 100 MHz with Vdd=1.2~V. [ABSTRACT FROM PUBLISHER]

This paper presents a time-to-digital converter (TDC) architecture capable of reaching high-precision and high-linearity with moderate area occupation per measurement channel. The architecture is based on a coarse counter and a couple of two-stage interpolators that exploit the cyclic sliding scale technique in order to improve the conversion linearity. The interpolators are based on a new coarse-fine synchronization circuit and a new single-stage Vernier delay loop fine interpolation. In a standard cost-effective 0.35 \mum CMOS technology the TDC reaches a dynamic range of 160 ns, 17.2 ps precision and differential non-linearity better than 0.9% LSB rms. The TDC building block was designed in order to be easily assembled in a multi-channel monolithic TDC chip. Coupled with a SPAD photodetector it is aimed for TCSPC applications (like FLIM, FCS, FRET) and direct ToF 3-D ranging. [ABSTRACT FROM AUTHOR]

This paper describes a 20 Gb/s receiver with a DLL-based CDR, which uses a proposed Ping-Pong delay line (PPDL) in order to ameliorate the limited operating range problem of the DLL. The unlimited phase shifting algorithm with the PPDL extends the tracking range of the DLL-based CDR. The PPDL correlates two variable delay lines and swaps each other whenever one of them reaches its operational limit. The chip occupies 0.24 mm^2 in 65 nm CMOS process. The power efficiency of the data transfer is 8.46 mW/Gb/s. The measured jitter of the 5 GHz clock is 1.125 psrms and the data eye opening is 0.613UI. [ABSTRACT FROM AUTHOR]

This paper proposes a 2.7 Gb/s referenceless transceiver with weighted PFD for frequency detection of random signals. A single loop referenceless CDR is also proposed to overcome the disadvantages of a dual loop CDR. The ANSI 8b/10b encoder & decoder with the scrambler, the serializer & de-serializer, and the output driver with pre-emphasis are included in the proposed transceiver architecture for DisplayPort v1.1a. The jitter of the generated clock at the Tx PLL is 3.28 psrms at 2.7 Gb/s with 1.2 V supply. The eye opening of the transmitter output with 3 m cable is 0.54 UI. The measured jitter of the recovered clock at the CDR is 1.57 psrms, and BER is less than 10^-12. The receiver consumes 23 mW at 2.7 Gb/s with 1.2 V supply. The CDR core and transceiver occupy 0.07 mm^2 and 0.94 mm^2, respectively, in a 0.13 \mum 1P8M CMOS process. [ABSTRACT FROM AUTHOR]

This paper proposes multiplexer-flip-flops (MUX-FFs) to be a high-throughput and low-cost solution for serial link transmitters. We also propose multiplexer-latches (MUX-Latches) that possess the logic function of combinational circuits and storing capacity of sequential circuits. Adopting the pipeline with MUX-FFs, which are composed of cascaded latches and MUX-Latches, many latch gates for sequencing can be removed. Analysis and simulation results show that an 8-to-1 serializer in the pipeline topology with MUX-FFs reduces 52% gate-count compared to that in the traditional pipeline topology. To verify the functions of the proposed design, two chips are implemented with the proposed 4-to-1 MUX-FF and 8-to-1 serializer with MUX-FFs in 90 nm CMOS technology. The measured results show that the MUX-FF and the proposed serializer with MUX-FFs are almost bit-error-free (with BER <; 10-12 ), operating at up to 6 Gbits/s and 12 Gbit/s, respectively. [ABSTRACT FROM PUBLISHER]

This paper presents a 5.4-Gb/s clock and data recovery circuit using a seamless loop transition scheme which has minimal phase noise degradation. The proposed scheme enables the CDR circuit to change the operation mode without output phase noise degradation or stability problems. A modified half-rate linear phase detector reduces the phase error between the data and clock. A tested chip is manufactured using 0.13-μm CMOS technology. The rms jitter of the proposed CDR circuit is 5.98 ps-rms, which is 2.61 ps lower than the CDR circuit with the conventional scheme. The measured power dissipation is 138 mW with output drivers and an embedded 2:1 MUX at 5.4-Gb/s data rate. [ABSTRACT FROM PUBLISHER]

Analog discrete-time finite-impulse-response (FIR) filters have been used as equalizers in digital communication receivers. For high speed applications, an FIR equalizer can be implemented using parallel sample-and-holds (S/Hs) and time-interleaved equalizer channels. Mismatches among the parallel S/Hs degrade the equalizer performance. This paper addresses mismatches of DC offsets, gain errors, sample-time errors, and bandwidths in the S/Hs. It is shown that having a different set of adapted coefficients in each equalizer channel can reduce the effects of mismatches. Simulation results are presented for different communication channels. [ABSTRACT FROM PUBLISHER]

Flying-Adder direct period synthesis is an emerging frequency synthesis technique. It is a mixed-signal technology that directly constructs the output clock period based on a multi-inputs reference. Owing to its open loop style and the usage of Time-Average-Frequency, this technique bears two important features: fine frequency resolution and instantaneous response. Although it has been used in commercial products for over a decade, the important issue associated with design/layout mismatch among its multi-inputs has not been studied in depth. In this paper, through a 55 nm Flying-Adder implementation, the cause of the mismatch is investigated. A mismatch model is created. Based on the model, the mismatch's impact is studied both in time and frequency domain. The experimental data from the chip is used to verify the observations from the analysis. Some useful insights are summarized in the end which will be useful in guiding future designs for commercial products. This study could also be helpful in developing a general theory for this problem. [ABSTRACT FROM PUBLISHER]

In modern CMOS processes, soft errors and metastability are two prominent failure mechanisms. Radiation induced single event upsets, or soft-errors, have become a dominant failure mechanism in sub-100 nm CMOS memory and logic circuits. The effects of metastability have also becoming increasingly significant in high-speed applications implemented in nanometric processes. In this paper the design trade-offs for flip-flops between performance, soft-error robustness and metastability are described. Soft-error robust flip-flops are implemented based on both the DICE cell and the Quatro cell. SPICE simulations are used to characterize the transient performance and metastability robustness, and device level simulations were performed to quantify the soft-error robustness. The flip-flops were fabricated in the TSMC 40 nm process and radiation measurements were performed at several test facilities. The Quatro flip-flop showed improved soft-error robustness and metastability when compared with a reference D flip-flop and a DICE flip-flop. [ABSTRACT FROM PUBLISHER]

This paper presents a new stage-sharing technique in a discrete-time (DT) 2–2 MASH delta-sigma (\Delta \Sigma) ADC to reduce the modulator power consumption and chip die area. The proposed technique shares all active blocks between the two stages of the modulator. The 2–2 MASH modulator utilizes the second-order Chain of Integrators with Weighted Feed-forward Summation (CIFF) and the Cascade of Integrators with Distributed Feedback Branches (CIFB) architectures for the first and second stages, respectively. Using the proposed technique, the second integrator and the adder op-amps of the modulator first stage are shared with the first and second integrator op-amps of the second stage. In addition to the stage-sharing scheme, other changes are introduced to improve the modulator dynamic range (DR) and power dissipation. Measurement results show that the modulator designed in a 0.13∼\mum CMOS technology achieves 75 dB SNDR over a 5 MHz signal bandwidth with a clock frequency of 130 MHz, while dissipating less than 9 mW analog power. [ABSTRACT FROM AUTHOR]

This paper presents a 4-GHz all-digital fractional-N PLL with a low-power TDC operating at low-rate retimed reference clocks, a compensator preventing big phase-error downfalls, and a loop settling monitor. Two retimed reference clocks, nCKR and pCKR, are employed in the TDC to estimate the fractional phase error between the low-rate reference and high-rate oscillator clocks. Applying the retimed reference clocks does not only reduce a dynamic power in its delay chain, but simplify a fractional phase-error correction. The phase-error compensator is introduced to avoid big phase-error downfalls caused by large output glitches originating from a high-speed accumulator. In addition, a loop-settling monitor is invented to allow the DCO operation mode to be shifted seamlessly and fast. By consuming 9.6 mW, the ADPLL achieves -97∼dBc in-band phase noise, - 38∼dBc/Hz integrated noise, and 740 ns settling time. [ABSTRACT FROM AUTHOR]

This paper presents a high-throughput FFT processor for IEEE 802.15.3c (WPANs) standard. To meet the throughput requirement of 2.59 Giga-samples/s, radix-16 FFT algorithm is adopted and reformulated to an efficient form so that the required number of butterfly stages is reduced. Specifically, the radix-16 butterfly processing element consists of two cascaded parallel/pipelined radix-4 butterfly units. It facilitates low-complexity realization of radix-16 butterfly operation and high operation speed due to its optimized pipelined structure. Besides, a new three-stage multiplier for twiddle factor multiplication is also proposed, which has lower area and power consumption than conventional complex multipliers. Moreover, a conflict-free multibank memory addressing scheme is devised to support up to 16-way parallel and normal-order data input/output. Without needing to reorder the input/output data, this scheme helps a high-throughput design result. Equipped with those new performance-boosting techniques, overall the proposed radix-16 FFT processor is area-efficient with high data processing rate and hardware utilization efficiency. The EDA synthesis results show that whole FFT processor area is 0.93∼\ mm^2, and the power consumption is 42 mW with 90 nm process. The SQNR performance is 57 dB with 12-bit wordlength implementation. [ABSTRACT FROM AUTHOR]