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This paper analyzes the high-temperature long-term stability of ohmic contacts on p-type gallium nitride (p-GaN). The contributions of the ohmic contacts and semiconductor material degradation are separated by adopting the transmission line method (TLM). Before stress, the current-voltage (I-V) curves measured at the pads of the TLMs showed a linear shape, indicating a good ohmic behavior of the contacts. Thermal treatment at 250 °C was found to induce the worsening of the electrical characteristics of the contacts: identified degradation modes consist of a shift of the I-V curves toward higher voltages and strong nonlinearity of the characteristics around zero. This paper shows that the high-temperature instabilities of ohmic contacts on p-GaN are related to the interaction between the device surface and the plasma-enhanced chemical vapor deposition SiN passivation layer. Hydrogen contained in the passivation layer is supposed to play an important role in the degradation process: the interaction with the acceptor dopant at the metal/semiconductor interface induces the decrease of the effective acceptor concentration. As a consequence, both the ohmic contact characteristics and the semiconductor sheet resistance are worsened. [ABSTRACT FROM AUTHOR]

This paper presents a circuit-compatible compact model for the intrinsic channel region of the MOSFET-like single-walled carbon-nanotube field-effect transistors (CNFETs). This model is valid for CNFET with a wide range of chiralities and diameters and for CNFET with either metallic or semiconducting carbon-nanotube (CNT) conducting channel. The modeled nonidealities include the quantum confinement effects on both circumferential and axial directions, the acoustical/optical phonon scattering in the channel region, and the screening effect by the parallel CNTs for CNFET with multiple CNTs. In order to be compatible with both large- (digital) and small-signal (analog) applications, a complete transcapacitance network is implemented to deliver the real-time dynamic response. This model is implemented with an HSPICE. Using this model, we project a 13 times CV/I improvement of the intrinsic CNFET with (19, 0) CNT over the bulk n-type MOSFET at the 32-nm node. The model described in this paper serves as a starting point toward the complete CNFET- device model incorporating the additional device/circuit-level nonidealities and multiple CNTs reported in the paper of Deng and Wong. [ABSTRACT FROM AUTHOR]

In this paper, we report on the possibility of using particle-based Monte Carlo (MC) techniques to incorporate all relevant quantum effects in the simulation of semiconductor nanotransistors. Starting from the conventional MC approach within the semiclassical Boltzmann approximation, we develop a multisubband description of transport to include quantization in ultrathin-body devices. This technique is then extended to the particle simulation of quantum transport within the Wigner formulation. This new simulator includes all expected quantum effects in nanotransistors and all relevant scattering mechanisms, which are taken into account the same way as in Boltzmann simulation. This paper is illustrated by analyzing the device operation and performance of multigate nanotransistors in a convenient range of channel lengths and thicknesses to separate the influence of all relevant effects: Significant quantization effects occur for thickness smaller than 5 nm and wave-mechanical-transport effects manifest themselves for channel length smaller than 10 nm. We also show that scattering mechanisms still have an important influence in nanoscaled double-gate transistors, both in the intrinsic part of the channel and in the resistive lateral extensions. [ABSTRACT FROM AUTHOR]

In this paper, a universal and computationally efficient subthreshold model for sub-100-nm nonuniformly doped channel MOSFET has been presented. The model incorporates drain-induced barrier lowering effect by means of the short-channel depletion width parameter d, which is evaluated using the voltage doping transformation method. The model can accurately predict the following: 1) surface potential; 2) electric field; 3) threshold voltage; and 4) subthreshold slope, for various lateral as well as transverse channel-engineered structures such as retrograde, graded channel, lightly doped drain (LDD), halo, and pocket implant technology for sub-100-nm channel length. In this paper, we have also proposed a novel device architecture incorporating the benefits of asymmetric halo and LDD doping. The analytical results have been verified by ATLAS 2-D device simulation software. [ABSTRACT FROM AUTHOR]

This paper presents accurate analytical models to calculate the electrostatic gate capacitance of 1-D field-effect transistors (FETs) with multiple cylindrical conducting channels. Gate capacitance Cgg is decomposed into three major components: 1) capacitance Cgc between the gate and the parallel cylindrical conducting channels (the number of channels ≥ 1) in dual-layer dielectric materials; 2) outer fringe capacitance Cof between the gate and the source/drain cylinder conductors; and 3) coupling capacitance Cgtg between the adjacent gates. A realistic planar-gate structure with high-k gate dielectric material is considered in this paper, including the screening effect of the parallel conductors and different dielectric materials on capacitance. An accuracy of 10% is achieved from the analytic models, compared with the values that were simulated by 3-D numerical field solvers. Using a simple analytical expression for the gate delay that includes the parasitic capacitance and screening of multiple parallel conducting channels, this paper also shows that both increasing the number of channels per gate and reducing the gate height are effective ways to improve device speed. [ABSTRACT FROM AUTHOR]

In this paper, the influence of a 10-nm-thick silicon-dioxide layer, as a passivation or as a gate insulation, on the performance of heterojunction field-effect transistors (HFETs) and metal-oxide-semiconductor HFETs (MOSHFETs), based on an undoped AlGaN/GaN heterostructure on a SiC substrate, was investigated. Channel-conductivity results yield a nearly 50% increase of mobility in the MOSHFET samples compared to the unpassivated HFETs. This increase of the transport properties of the MOSHFET channel is confirmed by a similar 45% increase of the cutoff frequency, from 16.5 to 24 GHz. Hall measurements, however, show a 10% decrease of the mobility in the heterostructure with a SiO2 top layer. In this paper, the superior performance of the MOSHFET transistor, in contradiction to the Hall results, is attributed to the screening of the Coulomb scattering of the charged surface defects by the gate-metallization layer. [ABSTRACT FROM AUTHOR]

This paper presents a systematic analytical model development for a sub-45-nm gate length double gate tunnel FET (DG TFET) and assessment of the tunneling current based on classical model under asymmetric circumstances with the ambipolar characteristic. Performance analysis of the tunneling current for a sub-45-nm gate length TFET is performed using Kane’s model by considering high doping in the source and drain regions keeping the channel region low doped. The model explains the variation of tunneling current with the change in oxide thickness under symmetric front and back gate voltages with 5 eV metal work function. The variation in tunnel current is also analyzed for the change in channel thickness under symmetric front and back gate voltages for symmetric oxide thickness. The increase in tunneling current for channel thickness scaling under asymmetric operation of the DG TFET is also efficiently captured by the developed model. The model is compared and verified with Sentaurus TCAD for all bias conditions and good agreement has been achieved. [ABSTRACT FROM PUBLISHER]

This paper presents the frequency and output power characteristics of oscillators in the graphene tunneling FETs (GTFET) technology. In order to acquire these characteristics, the practical operating conditions of GTFET oscillators are carefully analyzed, and then, the device parameters are simplified to an equivalent circuit and the I/V large signal model is approximated by a compact form. Expressions for the maximum oscillation frequency, maximum output power, and the relationship between frequency and power are given combing the equivalent circuit and the simplified model. In addition, the key device parameters that can be used to improve the performance of a GTFET oscillator are also discussed. [ABSTRACT FROM PUBLISHER]

In this paper, based on a full intrinsic–extrinsic model for symmetric doped double-gate MOSFET, we analyze the impact of FinFET gate resistance over the inverter and ring oscillator performance. It is shown that, when the total number of fins remains constant, the propagation delay can be improved thanks to the multifinger configuration that translates into the gate resistance reduction. Furthermore, the fin spacing in addition to source/drain fin extension reduction are of primary importance to improve the digital circuit performance. [ABSTRACT FROM PUBLISHER]

In this paper, we have developed a model for the surface potential and the drain current of a dual-material double-gate (DMDG) junctionless FET (JLFET) transistor. A finite-differentiation method has been used to decompose the 2-D Poisson’s equation into two 1-D equations, which allows the modeling of the DMDG structure as two individual single-material double-gate JLFETs. The two 1-D models are then combined using appropriate boundary conditions to provide a simple solution to the complex 2-D Poisson’s equation. The proposed model has been verified for different values of doping concentration ( ND ), oxide thickness ( T\mathrm{ ox} ), and channel thickness ( T\mathrm{ si} ) against the numerical simulations. [ABSTRACT FROM AUTHOR]

This paper proposes an analytical 2-D model for the channel potential and threshold voltage of double-gate junctionless FETs with a vertical Gaussian-like doping profile. The 2-D Poisson equation has been solved by using the evanescent-mode analysis to obtain the potential distribution function in the channel. The position of the conduction path also has been modeled to calculate the potential at different positions of the conduction path. The validity of the proposed 2-D potential and threshold voltage models is shown by comparing the results with the simulation data obtained by a 2-D TCAD ATLAS device simulator. [ABSTRACT FROM AUTHOR]

Dielectrically modulated tunnel FET (DMTFET)-based biosensors show higher sensitivity but lower subthreshold current compared with their dielectrically modulated FET counterpart. In this context, the effect of use of silicon–germanium (SiGe) source and n+-pocket-doped channel is investigated with the help of extensive device-level simulations. This paper explores the underlying physics of germanium composition variation in the source region, and doping concentration variation in n+-pocket region, from the perspective of biomolecule conjugation. The effects of source bandgap and tunneling length over the band-to-band tunneling component have been analyzed, and, subsequently, the sensing performance of DMTFETs has been estimated. The results show that SiGe-source DMTFET has significant superiority over n+-pocket DMTFET for attaining higher subthreshold current level while retaining acceptable sensitivity. Such sensitivity-current optimization has been studied for different gate and drain biases, and the suitable biasing range of operation has been indicated. In addition, the relative efficiency of SiGe source and n+-pocket-doped channel has been studied under different biomolecule sample specifications. Finally, the influence of trap-assisted tunneling on DMTFET sensing performance has been analyzed, and the comparative role of SiGe source and n+ pocket has also been indicated in this context. [ABSTRACT FROM AUTHOR]

We demonstrate in this paper a fast and simple method for evidencing and classifying the ambipolar response of tunneling-based field effect transistors in pull-down (nFET-like) and pull-up (pFET-like) modes. This technique enables to unequivocally determine whether carrier injection on either side of the device occurs via band-to-band-tunneling or single carrier tunneling through a Schottky barrier. It was applied to Silicon On Insulator (SOI) and SiGeOI tunnel FETs, which were fabricated to be nominally identical, yet showed a discrepancy of several orders of magnitude in ON-state current. The electrostatic analysis of their respective ambipolar signature revealed that the high-drive-current devices were in fact operating like Schottky barrier FETs in the pull-up mode due to a silicidation defect occurring only on the n-doped side. These new findings bring about a reassessment of previously published results in terms of on current—-subthreshold swing tradeoff perspectives for nanowire SiGe pTFETs. On the other hand, the resulting unintended asymmetrical device geometry suggests a possible route to fabricating Schottky barrier FETs with reduced parasitic leakage. [ABSTRACT FROM AUTHOR]

Switching behavior in electron–hole bilayer tunnel FETs is known to be unaffected by the subthreshold swing limitation of 60 mV/decade imposed by thermal injection, due to the band-to-band tunneling phenomena on which they rely. However, in this paper, we show that, once parasitic lateral tunneling processes are suppressed by means of heterogate configurations, a new physical limitation arises at the onset of tunneling in this type of transistors, resulting from the interplay between field-induced quantum confinement and asymmetric concentrations of electrons and holes inside the channel. We demonstrate that this limitation comes from the fact that, regardless of the band profile sharpness, the tunneling distance at subband alignment cannot be reduced beyond a certain limit, which we find to be dependent on the body thickness and the material properties. [ABSTRACT FROM PUBLISHER]

In this paper, a detailed evaluation of sub-10-nm n-/p-type GaSb–InAs double-gate tunneling FETs (TFETs) is presented. Source underlapping is shown to achieve lower subthreshold swing (SS) in both n- and p-type GaSb–InAs TFETs and is verified with the analytical treatment. The impact of parameter variations on the performance of underlapped TFETs is investigated through atomistic, 2-D ballistic simulations using self-consistently coupled nonequilibrium Green’s function-Poisson approach. Variations in underlap length, underlap doping, fin thickness, and temperature are comprehensively studied. It is shown that the underlap length of 6 nm is optimal for achieving low SS and it is found that the underlapped TFETs can maintain sub-60-mV/decade SS even when 3-nm fin thickness is relaxed by 40%. We also study the potential of TFETs in ultralow-power and high-density dynamic memories. A novel 4T gain cell embedded Dynamic Random Access Memory (e-DRAM) is proposed, which utilizes the low-leakage current of the source-underlapped TFETs to improve the data-retention time to 25 \mu \texts at V\mathrm {DD}=0.35 V, thereby enabling the prospects of e-DRAM at nanoscale gate lengths operating at ultralow supply voltages. [ABSTRACT FROM PUBLISHER]

High source doping is essential in tunnel FETs (TFETs) to support high electric fields necessary to provide sufficient drive currents. High doping is associated with band-tails in the density of states that decay exponentially into the bandgap, comparable with the decay of the carrier density above the band edge due to Fermi-tails. This is expected to limit the subthreshold swing (SS) and OFF-current in the TFETs. In this paper, we analyze the effects of band-tails on the subthreshold characteristics of III–V TFETs based on GaSb/InAs heterojunction. It is shown that the decay constant comparable with room-temperature thermal energy, kBT = 26 meV, can result in significant degradation of SS in TFETs from their ideal value. Electrically doping the intrinsic source could be an alternative, but not only does it increase the coupling between the gate and source contact due to proximity but also complicates the fabrication process. As a solution, we propose an undoped-source GaSb/InAs broken-gap TFET in an i-i-n configuration, which achieves similar performance to that of a corresponding p-i-n TFET while having exactly the same geometry. In the proposed device, the high drive current is supported by the broken-gap tunnel junction, while the Fermi-level pinning near the valence band of GaSb helps in realizing an ohmic source contact for the carriers in the valence band, which eventually participate in interband tunneling at the broken-gap tunnel junction in the ON-state. [ABSTRACT FROM PUBLISHER]

In this paper, we show that the subthreshold current–voltage characteristic can be used for estimating the interface trap density as a function of the energy in fully depleted symmetric metal-oxide-semiconductor devices with a minimum amount of modeling. The method is analyzed using TCAD simulations, and illustrated with the measurements on n-type silicon-on-insulator FinFETs. The results indicate that the trap density can be extracted between $\sim 0.65$ and 0.90 eV. This range is limited by resolution issues at the lowest current levels, and by the transition from subthreshold to saturation behavior at the high current levels. [ABSTRACT FROM AUTHOR]

Self-heating of FinFET transistors is a reliability concern, especially for large devices with dense arrays of fins on Silicon On Insulator. In this paper, device-level temperature measurements acquired using an optical technique are presented. The 2-D time-resolved emission measurements through the substrate are used to monitor the temperature-dependent modulation of the OFF-state leakage current of individual transistors, noninvasively and with high time accuracy. Different device geometries and operating conditions are evaluated and compared. [ABSTRACT FROM AUTHOR]

This paper presents a simulation study of In0.53Ga0.47As/InP heterojunction gate-overlapped-source tunnel FETs (GoS-TFETs) with pocket counter-doping. The effect of channel quantization on the line tunneling is considered in the semiclassical simulations using a new model that modifies the band edge in the inversion layer. The small bandgap of the source material In0.53Ga0.47As results in an improved tunnel rate, while the wide bandgap of the channel/drain material InP reduces ambipolar leakage. The simulations show that, for the case of perfectly aligned p-n-junction and heterojunction, the type-I band alignment and the large band offsets delay suppress lateral (point) tunneling relative to vertical (line) tunneling which improves the subthreshold swing (SS). The counter-doped pocket in the source region advances the onset of line tunneling relative to point tunneling which also assists in mitigating the effects of point tunneling. In this way, both large band offset and counter-doped pocket improve the subthreshold behavior of the TFET. Placing the p-n-junction inside the InP region makes the vertical tunneling even more dominant and, thus, reduces the SS. The suggested modifications might be useful to improve the device performance beyond that of the conventional GoS-TFETs. [ABSTRACT FROM AUTHOR]

This paper presents the low-frequency noise (LFN) behavior of vertical tunnel FETs (TFETs). The experimental input characteristics with different source compositions (Si and Ge) and different HfO2 thicknesses in the gate-stack (2 and 3 nm) are presented. A brief analog parameters analysis, including the transconductance, output conductance, and intrinsic voltage gain behavior under different bias conditions, shows that TFETs are promising for analog applications. For the LFN study, the standard number fluctuations model for MOSFETs was used in order to verify and compare the TFETs noise behavior, exploring the influence of different conduction mechanisms in each bias region. In the proposed model, the effective channel length ( L\mathrm{eff} ) is replaced by the tunneling length, resulting in good agreement between the experimental data and the model. The temperature influence on the TFET noise behavior is also investigated. [ABSTRACT FROM AUTHOR]

This paper studies the phase diagram of source pinchoff of dual-gate JFETs and presents a source pinchoff modeling formalism that is smooth across the phase boundaries. Based on this, an I\textrm {ds} model is derived, which is numerically robust for any value of top- and bottom-gate voltages. The method is applied to both the exact model for I\textrm {ds} and an approximated form based on mid-point-potential linearization, and is verified by comparison with numerical simulation. Modeling of short-channel effects is included. [ABSTRACT FROM AUTHOR]

This paper reports various optimization aspects of an ambipolar silicon nanowire field-effect transistor with high- \kappa source–drain ( S/D ) spacer using coupled 3-D Technology Computer Aided Design numerical device simulations. The impact of variation in device features, such as spacer material type and length of spacer ( \vphantom \sum RRr L\textrm {sp} ), gate dielectric and its thickness ( t\textrm {ox} ) and intergate distance ( dG1G2 ) on vital performance parameters of the device, such as I\mathrm{\scriptscriptstyle ON} , I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} , Subthreshold swing ( S/S ), V_{t} , and g_{m}/I_{d} , is investigated and analyzed. It is observed that increasing the spacer length increases Band to band tunneling rate probability through the thin barriers at ON-state. Moreover, the permittivity of spacer material is found to be closely related to the lateral fringe lines emanated from gate, resulting in a boosted I\mathrm\scriptscriptstyle ON as well as gm/Id at higher \kappa \textrm {sp} . Scaling down the thickness of gate oxide is not found to be a good idea, as it causes a reduction in ON–OFF current ratio though $S/S$ remains mostly unaffected. However, intergate distance scaling is found to have a strong influence on device performance providing higher current drive and lower $S/S$ for both n- and p-programs at lower dG1G2 . [ABSTRACT FROM PUBLISHER]

In this paper, a SPICE compatible analytical surface-potential-based model for junctionless symmetric double-gate (JLDG) MOSFETs is described. By using the gradual-channel-approximation, the 1-D Poisson’s equation is solved to obtain the surface and central potential in the JLDG MOSFET for long channel case. A continuous drain current model with smooth transitions from fully depleted region to partially depleted and accumulation regions is then derived from the Pao-Sah’s dual integral as a function of the surface and central potential at the source and drain terminals. The model is verified and validated by numerical simulations over a wide range of doping concentrations and device geometries. The model has been implemented in a circuit simulator and used to simulate some circuit building blocks without any convergent problem. [ABSTRACT FROM PUBLISHER]

A simple two step wet etch approach to fabricate nanowires (NWs) with a tapered source/drain (S/D) architecture is presented. Based on the unique NW architecture, gate-all-around junctionless NW FETs with sub-15-nm channel length ( $L_{{\mathrm{CH}}}$ ), NW height ( $H_{{\mathrm{NW}}}$ ), and NW width ( $W_{{\mathrm{NW}}}$ ) were realized. Despite having a large equivalent oxide thickness of $\sim 4.5$ nm, high extrinsic transconductance ( $G_{{m,{\mathrm{ ext}}}}) of 820 \mu \textS/\mu \textm was achieved at V\mathrm{ D} of 0.5 V. Due to the unique tapered S/D structure, the device realized in this paper achieved S/D series resistance ( R\mathrm {SD} ) of 275 \Omega \cdot \mu \mathrm m , which is one of the lowest among the reported 3-D InGaAs MOSFETs. [ABSTRACT FROM PUBLISHER]

Symmetric double-gate ferroelectric FETs (SDG-FeFETs) have better short-channel electrical behavior and hold promise in reducing the subthreshold swing below the classical Boltzmann’s limit. Surface potential and drain current models for SDG-FeFETs have already been published in the literature. In this paper, we derive the quasi-static terminal-charge models for these devices, which can be seamlessly integrated into standard circuit simulators using the Verilog-A interface. The terminal-charge models proposed are shown to match very well with exact numerical integration of Ward–Dutton terminal-charge integrals, for all bias conditions. Core compact model for the SDG-FeFET is implemented in a SPICE circuit simulator, and the simulation of different circuits built using SDG-FeFET transistors shows improvement in their switching behavior. [ABSTRACT FROM PUBLISHER]

Polymer FETs generally have a wide subthreshold regime due to a lot of disorder, mainly originated from domain/grain boundaries. Deep state’s charge transport of polymer transistors has not been investigated due to the difficulty in determining the field-effect mobility in the subthreshold region. In this paper, the features of the charge transport in deep and shallow states of polymer transistors will be discussed in detail through an accurate modeling and an analysis of subthreshold behavior in transistors. Charge transport in shallow states can be described by multiple trap and release transport, while hopping transport models, such as variable range hopping or Gaussian disorder-based model, describe well the deeper state’s charge transport. In addition, the transition between the conduction regimes is a function of temperature and carrier density. [ABSTRACT FROM PUBLISHER]

Line-edge roughness induced fin-edge roughness (FER) is the primary source of VT variation in FinFETs. Conventionally, stochastic simulations are performed to predict the device variability due to FER for a technology, which are computationally expensive. An analytical formulation to predict variability due to FER enables understanding of the effect of input parameters as well as provides quantitative results at fractional computational costs. In this paper, we develop and present an analytical model to estimate saturation VT ( $V_{{T\rm {-sat}}}) variability due to FER. The model is capable of capturing the LG and W\mathrm{ fin} ) and variability parameters (correlation length $\Lambda $ and standard deviation $\Delta )$ accurately. The entire $V_{{T\rm {-sat}}}$ distribution obtained by the model is also presented and compared against the $V_{{T\rm {-sat}}} distribution of stochastic simulations to show that the model captures the distribution effectively. We show that not only \sigma VT but even \mu VT is affected by variability parameters. Hence, such modeling is critical to defining nominal FinFET structure ( LG and W\mathrm{ fin} ), which is affected by variability ( $\Lambda $ and $\Delta $ ) especially for scaled FinFETs, where quantum-confinement effects are enhanced. [ABSTRACT FROM PUBLISHER]

A 6T SRAM design at a sub-10-nm node calls for carefully designed transistors so that new leakage mechanisms, such as direct source-to-drain tunneling (DSDT) and short channel effects that lead to I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} degradation, are kept under control. In this paper, we explore asymmetric underlap for mitigating DSDT, thermionic leakage, and for improving I\mathrm{\scriptscriptstyle ON}/I\mathrm{\scriptscriptstyle OFF} of double-gate FinFETs. We demonstrate that for 6T SRAMs, asymmetric underlapped n-FinFETs are superior to symmetric underlap/overlap in improving access time and leakage power. We model the atomistic nature of sub-10-nm FinFET channels, quantum confinement, subband nonparabolicity, and anisotropy latent at such length scales using quantum physics-based simulators instead of the conventional semiclassical, drift-diffusion-based Technology Computer Aided Design tools. Using a device/circuit/system-level codesign approach consisting of NEMO5 quantum mechanical device simulations, HSPICE circuit simulations of a 6T SRAM bit cell, and a system-level analysis of a 8-kB L1 and 4-MB L2 cache, we show that the adoption of optimized asymmetric underlapped n-FinFETs can offer up to 6.5% improvement in L1 cache access times and a 2.3-mW reduction in L2 cache leakage power, while delivering noise margins close to symmetric underlapped n-FinFET-based caches. [ABSTRACT FROM PUBLISHER]

In this paper, we report the results of an experimental analysis of the degradation induced by ON-state stress in GaN-based Schottky barrier diodes (SBDs). When a high stress current is applied to the device, turn-ON voltage ( V\mathrm{TON} ), forward voltage ( VF ), and ON-resistance ( $R_{{{\mathrm{\scriptscriptstyle ON}}}})$ are affected by charge carrier trapping occurring at the AlGaN surface close to the anode corners and/or into the AlGaN barrier layer. We have investigated the degradation of SBDs under different stress conditions, analyzing the influence of temperature and voltage, investigating the activation energy of the traps, and hence the trapping mechanisms. In addition, thanks to this approach, the device lifetime has been evaluated, proving good device reliability. [ABSTRACT FROM AUTHOR]

This paper presents the development of electrostatically actuated polymer-based microelectromechanical relays as a potential replacement for organic field-effect thin-film transistors in order to enable near-zero-power flexible transparent large-area electronics. A low-temperature five-mask surface-micromachining process is developed to fabricate two types of prototype relays: purely polymeric and partially polymeric (inorganic–organic hybrid) relays. Experimental results demonstrate the operation of the prototypes as a switch, showing immeasurably low OFF-state leakage current ( $\sim 10$ fA), abrupt switching behavior and high ON/OFF-current ratio (>105 over an effective input voltage swing of ≤100 mV), small hysteresis voltages (≤100 mV), and low contact adhesive forces (<10 nN/ \mu \text{m}^{2}) . The influence of temperature on switching characteristics, including hysteresis voltages, is investigated as well. [ABSTRACT FROM AUTHOR]

This paper presents an analytical model for the intrinsic capacitances and transconductances of triple-gate junctionless nanowire transistors. The model is based on a surface-potential drain current model, which includes short-channel effects, and accounts for the dependences on the device dimensions, doping concentration, and quantum effects. It is validated with 3-D Technology Computer-Aided Design (TCAD) simulations for several device characteristics and biases as well as with the experimental results. [ABSTRACT FROM AUTHOR]

It is my great pleasure to introduce the Seventh Special Issue of the IEEE TRANSACTIONS ON ELECTRON DEVICES on Solid-State Image Sensors. Previous special issues were published in February 1976, August 1985, May 1991, October 1997, January 2003, and November 2009. During the six-year interval since the last special issue, significant changes have occurred in the field of solid-state image sensors. This is due, in particular, to the drive for low-power, high integration, compact imaging systems. Now that the speed of pixel shrinkage is slowing down, various new technologies are being developed to increase the functionality of the sensors, to make them more compact, to make them faster, to increase their dynamic range, etc. Papers reflecting these trends in the image sensor technology are well represented in this special issue. [ABSTRACT FROM AUTHOR]

Wider bandwidth property of traveling-wave tubes (TWTs) is continuously pursued to satisfy the increased data rates and multiple channels in modern communications. In this paper, the coalesced-mode operation instead of the general single-mode operation for the double staggered grating waveguide (DSGW) slow-wave structure (SWS) is proposed to achieve an ultrawideband property of the TWTs driven by sheet electron beam. Analytical results of the high-frequency properties for the SWS, including the dispersion characteristics, interaction impedance, and transmission property, demonstrate that the coalesced-mode operation for the DSGW is possible. A novel loading approach of the attenuator with good performance, and meanwhile, a compact configuration is proposed to suppress the potential oscillations, thus leading to a steady beam–wave interaction for the coalesced-mode operation. To verify the concept of coalesced-mode operation, particle-in-cell simulation is performed. Simulation results demonstrate that the optimized RF circuit indeed can steadily operate in coalesced mode and produce over 5-kW saturated output power ( $\sim 10$ % efficiency) in a very broad frequency ranging from 37 to 52 GHz, corresponding to a relative bandwidth of 33.7%. [ABSTRACT FROM AUTHOR]

Carbon nanotubes (CNTs) have been demonstrated to be one of the most interesting materials for gas sensing. This paper applies a simple method for the direct transfer of high-density CNTs from a SiO2/Si substrate to a flexible substrate for carbon dioxide (CO2), ammonia (NH3), and isopropyl alcohol gas sensing at room temperature. The flexible gas sensor exhibited high sensitivities of 4.8%, 5.4%, and 5.2% at room temperature for ambient CO2, NH3, and isopropyl alcohol gas concentrations of 800 ppm, respectively. In addition, the gas response of the CNT-based chemiresistor is attributed to p-type conductivity in the Au-modified semiconducting CNTs. Very good repeatability of the sensor response to gas concentration is demonstrated, representing a major step toward the low-cost large-scale production of this class of device. [ABSTRACT FROM AUTHOR]

The high-field electron transport properties of ZnMgO/ZnO heterostructures considering multisubband conduction were systematically investigated with an ensemble Monte Carlo program developed by us. Electronic band structures were obtained by first-principles calculations using density functional theory, which provides more accurate parameters to calculate the electronic states and transport characteristics of 2-D electron gas. Wave functions and energy levels describing the subband structure were achieved to determine the 2-D scattering rates by solving the Schrödinger and Poisson equations self-consistently. The highest electron mobility gained at room temperature was approximately 4.23\times 10^\mathrm 2 cm2/Vs. The negative differential mobility was observed with a threshold electric field of approximately 80 kV/cm. The peak drift velocity of the Zn0.694Mg0.306O/ZnO heterostructure at 200 KV was about 2.011\times 10^8 cm/s. This paper benefits the development of high-performance ZnMgO/ZnO heterostructure devices. [ABSTRACT FROM AUTHOR]

In this paper, for the first time, an InAs/Si heterojunction double-gate tunnel FET (H-DGTFET) has been analyzed for low-power high-frequency applications. For this purpose, the suitability of the device for low-power applications is investigated by extracting the threshold voltage of the device using a transconductance change method and a constant current method. Furthermore, the effects of uniform and Gaussian drain doping profile on dc characteristics and analog/RF performances are investigated for different channel lengths. A highly doped layer is placed in the channel near the source–channel junction, and this decreases the width of the depletion region, which improves the ON-current ( I\rm{\scriptscriptstyle ON} ) and the RF performance. Furthermore, the circuit-level performance assessment is done by implementing a common source amplifier using the H-DGTFET; a 3-dB roll-off frequency of 230.11 GHz and a unity-gain frequency of 5.4 THz were achieved. [ABSTRACT FROM AUTHOR]

This paper presents the first experimental results of an extended interaction oscillator (EIO) based on a pseudospark-sourced electron beam, which produced a peak output power over 38 W at $W$ -band. The advantages of the newly developed device are: 1) transport of the electron beam by the positive-ion focusing channel without the need of an external magnetic field and 2) high interaction impedance and high gain per unit length of the EIO circuit. The experimental results agree well with the 3-D particle-in-cell simulations. [ABSTRACT FROM AUTHOR]

Optimization of light-emitting diode (LED) design is highly dependent on the relationship between photometric, electric, and thermal parameters of the device. The photoelectrothermal (PET) theory connects all the features of LED device. In this paper, wall-plug efficiency equations of PET theory were extended to estimate heat-dissipation factor and optical power of low-power surface-mounted device (SMD) LED. The wall-plug efficiency as a function of ambient temperature and injection current is used to predict the heat-dissipation factor and the optical power of the SMD LED. The TeraLED and T3ster systems were utilized to provide optical and thermal test reports of the LED parameters at a certain range of injection current and ambient temperature. The presented equations were verified by testing on low-power SMD LED. Results demonstrate that the estimated and measured values were in good agreement for all the considered parameters. This validates the extension of PET theory equations for low-power SMD LED. [ABSTRACT FROM AUTHOR]

In this paper, a new scheme called diffusion and gate replacement (D&GR) metal-inserted polysilicon integration is demonstrated. The CMOS flow allows controlling the gate height asymmetry between the nMOS and the pMOS by driving the work function shifter directly into the high- $k$ , and then by removing the dopant source (dummy doped metal gate) and depositing a fresh TiN metal gate. Although the integration flow is compatible with a standard 45-/28-nm technological node, it has been specifically designed to be compatible with dynamic random access memory peripheral applications or other emerging memories (embedded applications). A material down-selection is done (TiN/Mg/TiN gate-stack for nMOS and Al2O3 capping layer for pMOS), and it is demonstrated that a process window exists and guarantees enough work function lowering without compromising the electrical parameters (electrical oxide thickness, mobility, subthreshold slope, and gate leakage). Regarding the CMOS integration, it is shown that an nMOS-first integration is preferable, and that there is no contamination issue of the pMOS work function shifter (in this case, Al2O3) on the nMOS side. Finally, CMOS device performance is on par with the non-D&GR baseline, validating the integration flow. [ABSTRACT FROM AUTHOR]

This paper investigated physical mechanisms underlying the effects of localized back-surface defects ( D\mathrm { {loc}}) on the performances of amorphous InGaZnO thin-film transistors (a-IGZO TFTs). Four bands of density of states were utilized to represent D\mathrm { {loc}} . The a-IGZO thickness ( t\mathrm { {IGZO}}) was varied from 20 to 300 nm. When D\mathrm {{loc}} was absent, the TFT with t\mathrm { {IGZO}} of 20 nm can exhibit the best TFT performance. However, it got the severest performance degradation when D\mathrm {{loc}} was taken into consideration. We further changed acceptor-like tail and deep-level defect states at the back-channel surface from 0 to 10^\mathrm 20 cm ^\mathrm -2 eV ^\mathrm -1 and quantitatively studied their effects on energy band bendings, electric field distributions, carrier concentration distributions, and electrical characteristics of a-IGZO TFTs. [ABSTRACT FROM AUTHOR]

III–V semiconductors, especially InAs, have much higher electron mobilities than Si and have been considered as promising candidates for n-channel materials for post-Si low-power CMOS logic applications. Combined with the inherent 3-D structure that enables the gate-all-around (GAA) geometry for superb gate electrostatic control, III–V nanowire (NW) MOSFETs are well positioned to extend the scaling beyond Si. This paper attempts to provide a review of the growth and fabrication approaches (both bottom–up and top–down), and the state-of-the-art device performance of III-V NW GAA MOSFETs, as well as an outlook of their scaling potential. [ABSTRACT FROM AUTHOR]

In this paper, using a 2-D Poisson equation (in cylindrical coordinates), an analytical drain current model of a nanoscale RingFET architecture has been developed for the first time. Major short-channel effects, such as channel length modulation, velocity scattering, and drain-induced barrier lowering, are taken under consideration while developing the model. A bandgap narrowing model has been employed to investigate the impact of higher channel doping. The modeled results of the surface potential, electric field, threshold voltage ( V\mathrm{ th} ), subthreshold slope, and drain current have been verified by comparing with those of the ATLAS 3-D device simulation. The influence of the drain radius and position of the source/drain regions on the electrical characteristics of the device has also been demonstrated. [ABSTRACT FROM PUBLISHER]

In this paper, we identify the level shifter (LS) for voltage up-conversion from the ultralow-voltage regime as a key application domain of tunnel FETs (TFETs). We propose a mixed TFET–MOSFET LS design methodology, which exploits the complementary characteristics of TFET and MOSFET devices. Simulation results show that the hybrid LS exhibits superior dynamic performance at the same static power consumption compared with the conventional MOSFET and pure TFET solutions. The advantage of the mixed design with respect to the conventional MOSFET approach is emphasized when lower voltage signals have to be up-converted, reaching an improvement of the energy-delay product up to three decades. When compared with the full MOSFET design, the mixed TFET–MOSFET solution appears to be less sensitive toward threshold voltage variations in terms of dynamic figures of merit, at the expense of higher leakage variability. Similar results are obtained for four different LS topologies, thus indicating that the hybrid TFET–MOSFET approach offers intrinsic advantages in the design of LS for voltage up-conversion from the ultralow-voltage regime compared with the conventional MOSFET and pure TFET solutions. [ABSTRACT FROM PUBLISHER]

In this paper, an accurate compact model based on physical mechanisms for dual-gate bilayer graphene FETs is presented. This model is developed based on the 2-D density of states of bilayer graphene and is implemented in Verilog-A. Furthermore, physical equations describing the behavior of the source and drain access regions under back-gate bias are proposed. The accuracy of the developed large-signal compact model has been verified by comparison with measurement data from the literature. [ABSTRACT FROM PUBLISHER]

In this paper, we benchmark the performance of monolayer and bilayer MoS2 FETs (MFETs) against various multigate (MuG) Si-FET options, such as FinFETs and lateral and vertical nanowire FETs, for a 5-nm node and beyond. We compare the performance metrics of all the device options at the ring-oscillator (RO) level, accounting for not only intrinsic and extrinsic parasitic elements but also interconnects. Using the atomistic two-band ballistic quantum transport simulations, we evaluate ON-current and intrinsic capacitances for MoS2-based devices. Furthermore, we calibrate two-band model currents with more sophisticated full-band diffusive simulations to obtain realistic performance metrics at the circuit level. We show that both the intrinsic and parasitic capacitances of a single-gate MFET are lesser than those of a double-gate (DG) MFET, resulting in 13% lesser energy consumption. A DG bilayer (DGBL) MFET shows the best performance among different MFETs. In comparison toMuG FETs, the DGBL MFET offers not only lower energy consumption but also 35%–45% lower speed. In the end, to meet the target performance, we evaluate the impact of the device current, contact resistance, and back-end-of-the-line load on the speed of RO with the DGBL MFET. [ABSTRACT FROM PUBLISHER]

We present a detailed analysis of hot-carrier degradation (HCD) in graphene field-effect transistors (GFETs) and compare those findings with the bias-temperature instability (BTI). Our results show that the HCD in GFETs is recoverable, similar to its BTI counterpart. Moreover, both the degradation mechanisms strongly interact. Particular attention is paid to the dynamics of HCD recovery, which can be well fitted with the capture/emission time (CET) map model and the universal relaxation function for some stress conditions, quite similar to the BTI in both GFETs and Si technologies. The main result of this paper is an extension of our systematic method for benchmarking new graphene technologies for the case of HCD. [ABSTRACT FROM AUTHOR]

Two-dimensional (2D) crystal semiconductors, such as the well-known molybdenum disulfide (MoS2), are witnessing an explosion in research activities due to their apparent potential for various electronic and optoelectronic applications. In this paper, dissipative quantum transport simulations using nonequilibrium Green’s function formalism are performed to rigorously evaluate the scalability and performance of monolayer/multilayer 2D semiconductor-based FETs for sub-10 nm gate length very large-scale integration (VLSI) technologies. Device design considerations in terms of the choice of prospective 2D material/structure/technology to fulfill sub-10 nm International Technology Roadmap for Semiconductors (ITRS) requirements are analyzed. First, it is found that MoS2 FETs can meet high-performance (HP) requirement up to 6.6 nm gate length using bilayer MoS2 as the channel material, while low-standby-power (LSTP) requirements present significant challenges for all sub-10 nm gate lengths. Second, by studying the effects of underlap (UL) structures, scattering strength, and carrier effective mass, it is found that the high mobility and suitably low effective mass of tungsten diselenide (WSe2), aided by the UL, enable 2D FETs for both HP and LSTP applications at the smallest foreseeable (5.9 nm) gate length. Finally, possible solutions for sub-5 nm gate lengths, specifically anisotropic 2D semiconductor materials for HP and sub- $kT/q$ switch (2D tunnel FET) for LSTP, are also proposed based on the effects of critical material parameters on the device performance. [ABSTRACT FROM AUTHOR]

While keeping the technological evolution and commercialization of FinFET technology in mind, this paper discloses a novel concept that enables area-scaled or vertical tunneling in Fin-based technologies. The concept provides a roadmap for beyond FinFET technologies, while enjoying the advantages of FinFET-like structure without demanding technological abruptness from the existing FinFET technology nodes to beyond FinFET nodes. The proposed device at 10-nm gate length, when compared with the conventional vertical tunneling FET or planar area-scaled device, offers 100% improvement in the ON-current, $15\times {}$ reduction in the OFF-current, $3\times {}$ increase in the transconductance, 30% improvement in the output resistance, 55% improvement in the unity gain frequency, and more importantly $6\times {}$ reduction in the footprint area for a given drive capability. Furthermore, the proposed device brings the average and minimum subthreshold slope down to 40 and 11 mV/decade at 10-nm gate length. This gives a path for beyond FinFET system-on-chip applications, while enjoying the analog, digital, and RF performance improvements. [ABSTRACT FROM PUBLISHER]

This paper presents a SPICE-like graphene field-effect transistor (GFET) model with an improved carrier mobility analysis. The model considers the mobility difference between the electrons and the holes in graphene, as well as the mobility variation against the carrier density. Closed-form analytical solutions have been derived, and the model has been implemented in Verilog-A language. This was compiled into an advanced design system. The proposed model gives excellent agreement between the simulation results and the measurement data for both the hole and electron conduction simultaneously. The model is suitable for the exploration of GFET-based applications, especially for those using the ambipolar transfer property of GFET. [ABSTRACT FROM PUBLISHER]

In this paper, we address an important issue of low ON current in a Schottky barrier (SB) MOSFET by proposing a novel structure of Schottky MOSFET on silicon on insulator. The proposed Schottky device employs a dual material at the source side and is being named as the source engineered SB MOSFET (SE-SB-MOSFET). Erbium silicide (ErSi1.7) is used as the main source material, and Hafnium is used as a source extension. The use of Hafnium as a source extension induces an n+-type charge plasma in an undoped silicon film, which significantly reduces the SB thickness. A calibrated simulation study has shown that the ON current ( $I_{{{\mathrm{{\scriptscriptstyle ON}}}}}$ ) and $I_{{{\mathrm{{\scriptscriptstyle ON}}}}}/I_{{{\mathrm{{\scriptscriptstyle OFF}}}}} have increased by 225 and 65\times , respectively, in the proposed device in comparison with the conventional SB-MOSFET device. The ac analysis has shown that the cutoff frequency ( f_{T} ) in the proposed SE-SB-MOSFET ( \sim 200$ GHz) has increased by $200\times $ as compared with the conventional SB-MOSFET ( $\sim 1$ GHz). Furthermore, the performance of the proposed device has been tested at the circuit level also. It has been observed from the transient analysis that a significant reduction in switching ON delay ( $65\times $ ) and switching OFF delay (33%) has been achieved in the proposed SE-SB-MOSFET-based inverter in comparison with the conventional device-based inverter. Furthermore, the use of the charge plasma concept makes the fabrication of the proposed device relatively easy as it uses low thermal budget. [ABSTRACT FROM PUBLISHER]